paul@62 | 1 | /* |
paul@62 | 2 | * CPU-specific routines from U-Boot. |
paul@62 | 3 | * See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c |
paul@62 | 4 | * See: u-boot/arch/mips/include/asm/cacheops.h |
paul@62 | 5 | * |
paul@62 | 6 | * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
paul@62 | 7 | * |
paul@62 | 8 | * This program is free software; you can redistribute it and/or |
paul@62 | 9 | * modify it under the terms of the GNU General Public License as |
paul@62 | 10 | * published by the Free Software Foundation; either version 2 of |
paul@62 | 11 | * the License, or (at your option) any later version. |
paul@62 | 12 | * |
paul@62 | 13 | * This program is distributed in the hope that it will be useful, |
paul@62 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@62 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@62 | 16 | * GNU General Public License for more details. |
paul@62 | 17 | * |
paul@62 | 18 | * You should have received a copy of the GNU General Public License |
paul@62 | 19 | * along with this program; if not, write to the Free Software |
paul@62 | 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@62 | 21 | * Boston, MA 02110-1301, USA |
paul@62 | 22 | */ |
paul@62 | 23 | |
paul@62 | 24 | #include "xburst_types.h" |
paul@62 | 25 | #include "sdram.h" |
paul@62 | 26 | |
paul@62 | 27 | #define Index_Store_Tag_I 0x08 |
paul@62 | 28 | #define Index_Writeback_Inv_D 0x15 |
paul@62 | 29 | |
paul@62 | 30 | void flush_icache_all(void) |
paul@62 | 31 | { |
paul@62 | 32 | u32 addr, t = 0; |
paul@62 | 33 | |
paul@62 | 34 | asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ |
paul@62 | 35 | asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ |
paul@62 | 36 | |
paul@62 | 37 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; |
paul@62 | 38 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
paul@62 | 39 | asm volatile ( |
paul@62 | 40 | ".set mips3\n\t" |
paul@62 | 41 | " cache %0, 0(%1)\n\t" |
paul@62 | 42 | ".set mips2\n\t" |
paul@62 | 43 | : |
paul@62 | 44 | : "I" (Index_Store_Tag_I), "r"(addr)); |
paul@62 | 45 | } |
paul@62 | 46 | |
paul@62 | 47 | /* invalicate btb */ |
paul@62 | 48 | asm volatile ( |
paul@62 | 49 | ".set mips32\n\t" |
paul@62 | 50 | "mfc0 %0, $16, 7\n\t" |
paul@62 | 51 | "nop\n\t" |
paul@62 | 52 | "ori %0,2\n\t" |
paul@62 | 53 | "mtc0 %0, $16, 7\n\t" |
paul@62 | 54 | ".set mips2\n\t" |
paul@62 | 55 | : |
paul@62 | 56 | : "r" (t)); |
paul@62 | 57 | } |
paul@62 | 58 | |
paul@62 | 59 | void flush_dcache_all(void) |
paul@62 | 60 | { |
paul@62 | 61 | u32 addr; |
paul@62 | 62 | |
paul@62 | 63 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; |
paul@62 | 64 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
paul@62 | 65 | asm volatile ( |
paul@62 | 66 | ".set mips3\n\t" |
paul@62 | 67 | " cache %0, 0(%1)\n\t" |
paul@62 | 68 | ".set mips2\n\t" |
paul@62 | 69 | : |
paul@62 | 70 | : "I" (Index_Writeback_Inv_D), "r"(addr)); |
paul@62 | 71 | } |
paul@62 | 72 | |
paul@62 | 73 | asm volatile ("sync"); |
paul@62 | 74 | } |
paul@62 | 75 | |
paul@62 | 76 | void flush_cache_all(void) |
paul@62 | 77 | { |
paul@62 | 78 | flush_dcache_all(); |
paul@62 | 79 | flush_icache_all(); |
paul@62 | 80 | } |