NanoPayload

Annotated stage2/head2.S

184:8b4c47d9d10a
2016-05-04 Paul Boddie Introduced MIPS register definition symbols.
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/*
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 * Initialisation code for the stage 2 payload.
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 *
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 * Copyright 2009 (C) Qi Hardware Inc.
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 * Author: Wolfgang Spraul <wolfgang@sharism.cc>
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 *
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 * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk>
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 *
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 * This program is free software: you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation, either version 3 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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 */
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#include "mips.h"
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#include "sdram.h"
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.text
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.extern c_main
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.extern _tlb_entry
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.extern _exc_entry
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.extern _irq_entry
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.extern _end_entries
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.extern _got_start
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.extern _got_end
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.extern _got_copy_start
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.globl _start
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.set noreorder
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_start:
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	b real_start
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	nop
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	/* Apparently reserved region which, if used, breaks the USB Boot process. */
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	.word 0
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	.word 0
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	.word 0
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	.word 0
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	.word 0
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	.word 0
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	.word 0
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	.word 0
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real_start:     
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	/* Initialise the stack. */
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	la $sp, 0x80080000
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	/* Initialise the globals pointer. */
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	lui $gp, %hi(_GLOBAL_OFFSET_TABLE_)
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	ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_)
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	move $k0, $ra
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	/* Copy TLB handling instructions. */
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	la $t0, _tlb_entry		/* start */
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	li $t1, 0x80000000
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	la $t2, _exc_entry		/* end */
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	jal _copy
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	nop
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	/* Copy exception handling instructions. */
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	la $t0, _exc_entry		/* start */
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	li $t1, 0x80000180
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	la $t2, _irq_entry		/* end */
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	jal _copy
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	nop
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	/* Copy IRQ handling instructions. */
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	la $t0, _irq_entry		/* start */
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	li $t1, 0x80000200
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	la $t2, _end_entries		/* end */
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	jal _copy
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	nop
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	/* Copy the offset table for user mode programs. */
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	la $t0, _got_start		/* start */
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	la $t1, _got_copy_start
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	la $t2, _got_end		/* end */
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	li $t3, 0x80000000		/* adjustment */
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	jal _copy_adjust
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	nop
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	move $ra, $k0
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	/* Enable caching. */
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	li $t0, CONFIG_CM_CACHABLE_NONCOHERENT
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	mtc0 $t0, CP0_CONFIG
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	nop
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	/* Start the program. */
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	la $t9, c_main			/* load the address of the routine */
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	j c_main
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	nop
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_copy:
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	/* Copy via $t3 the region from $t0 to $t2 into $t1. */
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	lw $t3, 0($t0)
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	addiu $t0, $t0, 4
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	sw $t3, 0($t1)
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	bne $t0, $t2, _copy
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	addiu $t1, $t1, 4		/* executed in delay slot before branch */
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	jr $ra
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	nop
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_copy_adjust:
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	/* Copy via $t4 the region from $t0 to $t2 into $t1, adjusting by $t3. */
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	lw $t4, 0($t0)
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	addiu $t0, $t0, 4
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	subu $t4, $t4, $t3
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	sw $t4, 0($t1)
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	bne $t0, $t2, _copy_adjust
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	addiu $t1, $t1, 4		/* executed in delay slot before branch */
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	jr $ra
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	nop
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.set reorder