paul@62 | 1 | /* |
paul@62 | 2 | * CPU-specific routines from U-Boot. |
paul@62 | 3 | * See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c |
paul@62 | 4 | * See: u-boot/arch/mips/include/asm/cacheops.h |
paul@62 | 5 | * |
paul@62 | 6 | * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
paul@62 | 7 | * |
paul@62 | 8 | * This program is free software; you can redistribute it and/or |
paul@62 | 9 | * modify it under the terms of the GNU General Public License as |
paul@62 | 10 | * published by the Free Software Foundation; either version 2 of |
paul@62 | 11 | * the License, or (at your option) any later version. |
paul@62 | 12 | * |
paul@62 | 13 | * This program is distributed in the hope that it will be useful, |
paul@62 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@62 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@62 | 16 | * GNU General Public License for more details. |
paul@62 | 17 | * |
paul@62 | 18 | * You should have received a copy of the GNU General Public License |
paul@62 | 19 | * along with this program; if not, write to the Free Software |
paul@62 | 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@62 | 21 | * Boston, MA 02110-1301, USA |
paul@62 | 22 | */ |
paul@62 | 23 | |
paul@62 | 24 | #include "xburst_types.h" |
paul@62 | 25 | #include "sdram.h" |
paul@62 | 26 | |
paul@62 | 27 | void flush_icache_all(void) |
paul@62 | 28 | { |
paul@62 | 29 | u32 addr, t = 0; |
paul@62 | 30 | |
paul@62 | 31 | asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ |
paul@62 | 32 | asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ |
paul@62 | 33 | |
paul@62 | 34 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; |
paul@62 | 35 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
paul@62 | 36 | asm volatile ( |
paul@62 | 37 | ".set mips3\n\t" |
paul@62 | 38 | " cache %0, 0(%1)\n\t" |
paul@62 | 39 | ".set mips2\n\t" |
paul@62 | 40 | : |
paul@62 | 41 | : "I" (Index_Store_Tag_I), "r"(addr)); |
paul@62 | 42 | } |
paul@62 | 43 | |
paul@62 | 44 | /* invalicate btb */ |
paul@62 | 45 | asm volatile ( |
paul@62 | 46 | ".set mips32\n\t" |
paul@62 | 47 | "mfc0 %0, $16, 7\n\t" |
paul@62 | 48 | "nop\n\t" |
paul@62 | 49 | "ori %0,2\n\t" |
paul@62 | 50 | "mtc0 %0, $16, 7\n\t" |
paul@62 | 51 | ".set mips2\n\t" |
paul@62 | 52 | : |
paul@62 | 53 | : "r" (t)); |
paul@62 | 54 | } |
paul@62 | 55 | |
paul@62 | 56 | void flush_dcache_all(void) |
paul@62 | 57 | { |
paul@62 | 58 | u32 addr; |
paul@62 | 59 | |
paul@62 | 60 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; |
paul@62 | 61 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
paul@62 | 62 | asm volatile ( |
paul@62 | 63 | ".set mips3\n\t" |
paul@62 | 64 | " cache %0, 0(%1)\n\t" |
paul@62 | 65 | ".set mips2\n\t" |
paul@62 | 66 | : |
paul@62 | 67 | : "I" (Index_Writeback_Inv_D), "r"(addr)); |
paul@62 | 68 | } |
paul@62 | 69 | |
paul@62 | 70 | asm volatile ("sync"); |
paul@62 | 71 | } |
paul@62 | 72 | |
paul@62 | 73 | void flush_cache_all(void) |
paul@62 | 74 | { |
paul@62 | 75 | flush_dcache_all(); |
paul@62 | 76 | flush_icache_all(); |
paul@62 | 77 | } |
paul@67 | 78 | |
paul@73 | 79 | void handle_error_level(void) |
paul@73 | 80 | { |
paul@73 | 81 | asm volatile( |
paul@73 | 82 | "mfc0 $t3, $12\n" /* CP0_STATUS */ |
paul@73 | 83 | "nop\n" |
paul@73 | 84 | "li $t4, 0xfffffffb\n" /* ERL = 0 */ |
paul@73 | 85 | "and $t3, $t3, $t4\n" |
paul@73 | 86 | "mtc0 $t3, $12\n" |
paul@73 | 87 | "nop\n"); |
paul@73 | 88 | } |
paul@73 | 89 | |
paul@67 | 90 | void enable_interrupts(void) |
paul@67 | 91 | { |
paul@67 | 92 | asm volatile( |
paul@67 | 93 | "mfc0 $t3, $12\n" /* CP0_STATUS */ |
paul@67 | 94 | "nop\n" |
paul@73 | 95 | "li $t4, 0x0000fc01\n" /* IE = enable interrupts */ |
paul@67 | 96 | "or $t3, $t3, $t4\n" |
paul@67 | 97 | "mtc0 $t3, $12\n" |
paul@67 | 98 | "nop\n"); |
paul@67 | 99 | } |
paul@73 | 100 | |
paul@73 | 101 | void init_interrupts(void) |
paul@73 | 102 | { |
paul@73 | 103 | /* Set exception registers. */ |
paul@73 | 104 | |
paul@73 | 105 | asm volatile( |
paul@73 | 106 | "mtc0 $zero, $18\n" /* CP0_WATCHLO */ |
paul@73 | 107 | "nop\n" |
paul@73 | 108 | "li $t3, 0x00800000\n" /* IV = 1 (use 0x80000200 for interrupts) */ |
paul@73 | 109 | "mtc0 $t3, $13\n" /* CP0_CAUSE */ |
paul@73 | 110 | "nop\n" |
paul@73 | 111 | "mtc0 $zero, $12\n" /* CP0_STATUS */ |
paul@73 | 112 | "nop\n"); |
paul@73 | 113 | } |
paul@73 | 114 | |
paul@73 | 115 | void init_tlb(void) |
paul@73 | 116 | { |
paul@73 | 117 | asm volatile( |
paul@73 | 118 | "li $t0, 0x001fe000\n" /* 1MB */ |
paul@73 | 119 | "mtc0 $t0, $5\n" /* CP0_PAGEMASK */ |
paul@73 | 120 | "nop\n" |
paul@73 | 121 | "mtc0 $zero, $6\n" /* CP0_WIRED */ |
paul@73 | 122 | "nop\n" |
paul@73 | 123 | |
paul@73 | 124 | /* Set physical address. */ |
paul@73 | 125 | |
paul@78 | 126 | "li $t0, 0x0000001b\n" /* 0x000000.. C=3, global, valid */ |
paul@73 | 127 | "mtc0 $t0, $2\n" /* CP0_ENTRYLO0 */ |
paul@73 | 128 | "nop\n" |
paul@78 | 129 | "li $t0, 0x0000001b\n" /* 0x000000.. C=3, global, valid */ |
paul@78 | 130 | "mtc0 $t0, $3\n" /* CP0_ENTRYLO1 */ |
paul@73 | 131 | "nop\n" |
paul@73 | 132 | |
paul@73 | 133 | /* Set virtual address. */ |
paul@73 | 134 | |
paul@76 | 135 | "li $t0, 0x80000000\n" /* 0x80000... ASID=0 */ |
paul@73 | 136 | "mtc0 $t0, $10\n" /* CP0_ENTRYHI */ |
paul@73 | 137 | "nop\n" |
paul@73 | 138 | |
paul@76 | 139 | "tlbwr\n" |
paul@76 | 140 | "nop"); |
paul@73 | 141 | } |