paul@62 | 1 | /* |
paul@90 | 2 | * CPU-specific routines originally from U-Boot. |
paul@62 | 3 | * See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c |
paul@62 | 4 | * See: u-boot/arch/mips/include/asm/cacheops.h |
paul@62 | 5 | * |
paul@62 | 6 | * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
paul@90 | 7 | * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk> |
paul@62 | 8 | * |
paul@62 | 9 | * This program is free software; you can redistribute it and/or |
paul@62 | 10 | * modify it under the terms of the GNU General Public License as |
paul@62 | 11 | * published by the Free Software Foundation; either version 2 of |
paul@62 | 12 | * the License, or (at your option) any later version. |
paul@62 | 13 | * |
paul@62 | 14 | * This program is distributed in the hope that it will be useful, |
paul@62 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@62 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@62 | 17 | * GNU General Public License for more details. |
paul@62 | 18 | * |
paul@62 | 19 | * You should have received a copy of the GNU General Public License |
paul@62 | 20 | * along with this program; if not, write to the Free Software |
paul@62 | 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@62 | 22 | * Boston, MA 02110-1301, USA |
paul@62 | 23 | */ |
paul@62 | 24 | |
paul@62 | 25 | #include "xburst_types.h" |
paul@62 | 26 | #include "sdram.h" |
paul@62 | 27 | |
paul@62 | 28 | void flush_icache_all(void) |
paul@62 | 29 | { |
paul@62 | 30 | u32 addr, t = 0; |
paul@62 | 31 | |
paul@62 | 32 | asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ |
paul@62 | 33 | asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ |
paul@62 | 34 | |
paul@62 | 35 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; |
paul@62 | 36 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
paul@62 | 37 | asm volatile ( |
paul@62 | 38 | ".set mips3\n\t" |
paul@62 | 39 | " cache %0, 0(%1)\n\t" |
paul@62 | 40 | ".set mips2\n\t" |
paul@62 | 41 | : |
paul@62 | 42 | : "I" (Index_Store_Tag_I), "r"(addr)); |
paul@62 | 43 | } |
paul@62 | 44 | |
paul@62 | 45 | /* invalicate btb */ |
paul@62 | 46 | asm volatile ( |
paul@62 | 47 | ".set mips32\n\t" |
paul@62 | 48 | "mfc0 %0, $16, 7\n\t" |
paul@62 | 49 | "nop\n\t" |
paul@62 | 50 | "ori %0,2\n\t" |
paul@62 | 51 | "mtc0 %0, $16, 7\n\t" |
paul@62 | 52 | ".set mips2\n\t" |
paul@62 | 53 | : |
paul@62 | 54 | : "r" (t)); |
paul@62 | 55 | } |
paul@62 | 56 | |
paul@62 | 57 | void flush_dcache_all(void) |
paul@62 | 58 | { |
paul@62 | 59 | u32 addr; |
paul@62 | 60 | |
paul@62 | 61 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; |
paul@62 | 62 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
paul@62 | 63 | asm volatile ( |
paul@62 | 64 | ".set mips3\n\t" |
paul@62 | 65 | " cache %0, 0(%1)\n\t" |
paul@62 | 66 | ".set mips2\n\t" |
paul@62 | 67 | : |
paul@62 | 68 | : "I" (Index_Writeback_Inv_D), "r"(addr)); |
paul@62 | 69 | } |
paul@62 | 70 | |
paul@62 | 71 | asm volatile ("sync"); |
paul@62 | 72 | } |
paul@62 | 73 | |
paul@62 | 74 | void flush_cache_all(void) |
paul@62 | 75 | { |
paul@62 | 76 | flush_dcache_all(); |
paul@62 | 77 | flush_icache_all(); |
paul@62 | 78 | } |
paul@67 | 79 | |
paul@73 | 80 | void handle_error_level(void) |
paul@73 | 81 | { |
paul@73 | 82 | asm volatile( |
paul@73 | 83 | "mfc0 $t3, $12\n" /* CP0_STATUS */ |
paul@73 | 84 | "nop\n" |
paul@73 | 85 | "li $t4, 0xfffffffb\n" /* ERL = 0 */ |
paul@73 | 86 | "and $t3, $t3, $t4\n" |
paul@73 | 87 | "mtc0 $t3, $12\n" |
paul@73 | 88 | "nop\n"); |
paul@73 | 89 | } |
paul@73 | 90 | |
paul@67 | 91 | void enable_interrupts(void) |
paul@67 | 92 | { |
paul@67 | 93 | asm volatile( |
paul@67 | 94 | "mfc0 $t3, $12\n" /* CP0_STATUS */ |
paul@67 | 95 | "nop\n" |
paul@73 | 96 | "li $t4, 0x0000fc01\n" /* IE = enable interrupts */ |
paul@67 | 97 | "or $t3, $t3, $t4\n" |
paul@67 | 98 | "mtc0 $t3, $12\n" |
paul@67 | 99 | "nop\n"); |
paul@67 | 100 | } |
paul@73 | 101 | |
paul@73 | 102 | void init_interrupts(void) |
paul@73 | 103 | { |
paul@73 | 104 | /* Set exception registers. */ |
paul@73 | 105 | |
paul@73 | 106 | asm volatile( |
paul@73 | 107 | "mtc0 $zero, $18\n" /* CP0_WATCHLO */ |
paul@73 | 108 | "nop\n" |
paul@73 | 109 | "li $t3, 0x00800000\n" /* IV = 1 (use 0x80000200 for interrupts) */ |
paul@73 | 110 | "mtc0 $t3, $13\n" /* CP0_CAUSE */ |
paul@73 | 111 | "nop\n" |
paul@84 | 112 | "mfc0 $t3, $12\n" /* CP0_STATUS */ |
paul@84 | 113 | "nop\n" |
paul@84 | 114 | "li $t4, 0xffbfffff\n" /* BEV=0 */ |
paul@84 | 115 | "and $t3, $t3, $t4\n" |
paul@84 | 116 | "mtc0 $t3, $12\n" |
paul@73 | 117 | "nop\n"); |
paul@73 | 118 | } |
paul@73 | 119 | |
paul@73 | 120 | void init_tlb(void) |
paul@73 | 121 | { |
paul@73 | 122 | asm volatile( |
paul@83 | 123 | "li $t0, 0x01ffe000\n" /* 16MB */ |
paul@73 | 124 | "mtc0 $t0, $5\n" /* CP0_PAGEMASK */ |
paul@73 | 125 | "nop\n" |
paul@90 | 126 | "li $t0, 2\n" /* index of first randomly-replaced entry */ |
paul@90 | 127 | "mtc0 $t0, $6\n" /* CP0_WIRED */ |
paul@73 | 128 | "nop\n" |
paul@73 | 129 | |
paul@90 | 130 | /* 0x80000000..0x82000000 -> 0x00000000..0x02000000 */ |
paul@83 | 131 | |
paul@83 | 132 | "mtc0 $zero, $0\n" /* CP0_INDEX */ |
paul@83 | 133 | "nop\n" |
paul@83 | 134 | |
paul@73 | 135 | /* Set physical address. */ |
paul@73 | 136 | |
paul@83 | 137 | "li $t0, 0x0000001f\n" /* 0x00000000, C=3, dirty, global, valid */ |
paul@73 | 138 | "mtc0 $t0, $2\n" /* CP0_ENTRYLO0 */ |
paul@73 | 139 | "nop\n" |
paul@90 | 140 | "li $t0, 0x0004001f\n" /* 0x01000000, C=3, dirty, global, valid */ |
paul@78 | 141 | "mtc0 $t0, $3\n" /* CP0_ENTRYLO1 */ |
paul@73 | 142 | "nop\n" |
paul@73 | 143 | |
paul@73 | 144 | /* Set virtual address. */ |
paul@73 | 145 | |
paul@83 | 146 | "li $t0, 0x80000000\n" /* 0x80000000, ASID=0 */ |
paul@73 | 147 | "mtc0 $t0, $10\n" /* CP0_ENTRYHI */ |
paul@73 | 148 | "nop\n" |
paul@73 | 149 | |
paul@83 | 150 | "tlbwi\n" |
paul@83 | 151 | "nop\n" |
paul@83 | 152 | |
paul@99 | 153 | /* 0x00000000..0x02000000 -> 0x00000000..0x02000000 */ |
paul@83 | 154 | |
paul@83 | 155 | "li $t0, 1\n" |
paul@83 | 156 | "mtc0 $t0, $0\n" /* CP0_INDEX */ |
paul@83 | 157 | "nop\n" |
paul@83 | 158 | |
paul@83 | 159 | /* Set physical address. */ |
paul@83 | 160 | |
paul@90 | 161 | "li $t0, 0x0000001f\n" /* 0x00000000, C=3, dirty, global, valid */ |
paul@83 | 162 | "mtc0 $t0, $2\n" /* CP0_ENTRYLO0 */ |
paul@83 | 163 | "nop\n" |
paul@90 | 164 | "li $t0, 0x0004001f\n" /* 0x01000000, C=3, dirty, global, valid */ |
paul@83 | 165 | "mtc0 $t0, $3\n" /* CP0_ENTRYLO1 */ |
paul@83 | 166 | "nop\n" |
paul@83 | 167 | |
paul@83 | 168 | /* Set virtual address. */ |
paul@83 | 169 | |
paul@90 | 170 | "li $t0, 0x00000000\n" /* 0x00000000, ASID=0 */ |
paul@83 | 171 | "mtc0 $t0, $10\n" /* CP0_ENTRYHI */ |
paul@83 | 172 | "nop\n" |
paul@83 | 173 | |
paul@83 | 174 | "tlbwi\n" |
paul@76 | 175 | "nop"); |
paul@73 | 176 | } |