paul@0 | 1 | /* |
paul@9 | 2 | * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> |
paul@27 | 3 | * Copyright (C) 2009 Qi Hardware Inc. |
paul@27 | 4 | * Authors: Xiangfu Liu <xiangfu@openmobilefree.net> |
paul@0 | 5 | * |
paul@0 | 6 | * This program is free software; you can redistribute it and/or |
paul@0 | 7 | * modify it under the terms of the GNU General Public License |
paul@0 | 8 | * as published by the Free Software Foundation; either version |
paul@0 | 9 | * 3 of the License, or (at your option) any later version. |
paul@27 | 10 | * |
paul@27 | 11 | * This program is distributed in the hope that it will be useful, |
paul@27 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@27 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@27 | 14 | * GNU General Public License for more details. |
paul@27 | 15 | * |
paul@27 | 16 | * You should have received a copy of the GNU General Public License |
paul@27 | 17 | * along with this program; if not, write to the Free Software |
paul@27 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@27 | 19 | * Boston, MA 02110-1301, USA |
paul@0 | 20 | */ |
paul@0 | 21 | |
paul@0 | 22 | /* |
paul@0 | 23 | * This file contains the configuration parameters for the NanoNote. |
paul@0 | 24 | */ |
paul@27 | 25 | #ifndef __NANONOTE_H__ |
paul@27 | 26 | #define __NANONOTE_H__ |
paul@27 | 27 | |
paul@27 | 28 | #include "jz4740_lcd.h" |
paul@0 | 29 | |
paul@0 | 30 | /* |
paul@12 | 31 | * Display configuration |
paul@12 | 32 | */ |
paul@12 | 33 | #define LCD_BPP LCD_COLOR32 |
paul@12 | 34 | |
paul@12 | 35 | /* |
paul@15 | 36 | * RAM configuration |
paul@15 | 37 | */ |
paul@15 | 38 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
paul@15 | 39 | |
paul@15 | 40 | /* |
paul@27 | 41 | * SDRAM configuration (timings in ns) |
paul@27 | 42 | */ |
paul@27 | 43 | #define CONFIG_NR_DRAM_BANKS 1 |
paul@27 | 44 | |
paul@27 | 45 | #define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ |
paul@27 | 46 | #define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ |
paul@27 | 47 | #define SDRAM_ROW 13 /* Row address: 11 to 13 */ |
paul@27 | 48 | #define SDRAM_COL 9 /* Column address: 8 to 12 */ |
paul@27 | 49 | #define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ |
paul@27 | 50 | #define SDRAM_TRAS 45 /* RAS# Active Time */ |
paul@27 | 51 | #define SDRAM_RCD 20 /* RAS# to CAS# Delay */ |
paul@27 | 52 | #define SDRAM_TPC 20 /* RAS# Precharge Time */ |
paul@27 | 53 | #define SDRAM_TRWL 7 /* Write Latency Time */ |
paul@27 | 54 | #define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ |
paul@27 | 55 | |
paul@27 | 56 | /* |
paul@12 | 57 | * Cache configuration |
paul@9 | 58 | */ |
paul@9 | 59 | #define CONFIG_SYS_DCACHE_SIZE 16384 |
paul@9 | 60 | #define CONFIG_SYS_ICACHE_SIZE 16384 |
paul@9 | 61 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
paul@29 | 62 | |
paul@29 | 63 | /* |
paul@29 | 64 | * Memory configuration |
paul@29 | 65 | */ |
paul@9 | 66 | #define KSEG0 0x80000000 |
paul@29 | 67 | #define PAGE_SIZE 4096 |
paul@9 | 68 | |
paul@9 | 69 | /* |
paul@0 | 70 | * GPIO definition |
paul@5 | 71 | * See: http://en.qi-hardware.com/wiki/Hardware_basics |
paul@0 | 72 | */ |
paul@9 | 73 | #define GPIO_LCD_CS (2 * 32 + 21) |
paul@9 | 74 | #define GPIO_AMP_EN (3 * 32 + 4) |
paul@0 | 75 | |
paul@9 | 76 | #define GPIO_SDPW_EN (3 * 32 + 2) |
paul@9 | 77 | #define GPIO_SD_DETECT (3 * 32 + 0) |
paul@0 | 78 | |
paul@9 | 79 | #define GPIO_BUZZ_PWM (3 * 32 + 27) |
paul@9 | 80 | #define GPIO_USB_DETECT (3 * 32 + 28) |
paul@0 | 81 | |
paul@9 | 82 | #define GPIO_AUDIO_POP (1 * 32 + 29) |
paul@9 | 83 | #define GPIO_COB_TEST (1 * 32 + 30) |
paul@0 | 84 | |
paul@9 | 85 | #define GPIO_KEYOUT_BASE (2 * 32 + 10) |
paul@9 | 86 | #define GPIO_KEYIN_BASE (3 * 32 + 18) |
paul@9 | 87 | #define GPIO_KEYIN_8 (3 * 32 + 26) |
paul@0 | 88 | |
paul@9 | 89 | #define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */ |
paul@9 | 90 | #define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */ |
paul@0 | 91 | |
paul@9 | 92 | #define GPIO_SD_CMD (3 * 32 + 8) |
paul@6 | 93 | |
paul@9 | 94 | #define SPEN GPIO_LCD_CS /* LCDCS :Serial command enable */ |
paul@9 | 95 | #define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */ |
paul@9 | 96 | #define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */ |
paul@9 | 97 | |
paul@27 | 98 | #endif /* __NANONOTE_H__ */ |