136:d429015dc262
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2016-02-26 |
Paul Boddie |
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Introduced more immediate TLB miss handling in order to avoid stack usage and
the potential for a TLB miss upon trying to save registers to the stack.
Moved handle_error_level back into irq_init, separating out enable_interrupts
instead. |
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stage2/cpu.c stage2/cpu.h stage2/entry.S stage2/handlers.S stage2/irq.c stage2/stage2.c
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135:00392b6b6878
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2016-02-26 |
Paul Boddie |
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Added a potentially useful TLB page miss mapping function. |
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stage2/cpu.c stage2/cpu.h stage2/irq.c
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134:a2d51d81fa86
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2016-02-26 |
Paul Boddie |
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Introduced a method of invoking task routines for testing. |
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stage2/irq.c stage2/stage2.c
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133:7981e27344ab
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2016-02-26 |
Paul Boddie |
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Added elements of a task switching mechanism. |
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stage2/cpu.c stage2/cpu.h stage2/handlers.S stage2/irq.c stage2/irq.h stage2/stage2.c
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132:033671d0e462
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2016-02-26 |
Paul Boddie |
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Introduced the start of a more complicated page mapping scheme. |
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stage2/irq.c
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131:2bfc95ec6a5f
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2016-02-25 |
Paul Boddie |
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Separated error level and interrupt initialisation.
Made use of the EntryHi register instead of the Context register when handling
TLB misses in order to obtain the ASID. |
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stage2/irq.c stage2/stage2.c
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130:33216055a16c
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2016-02-25 |
Paul Boddie |
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Added missing ASID sections to EntryHi register values. |
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stage2/cpu.c
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129:d5fb9ec3001a
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2016-02-25 |
Paul Boddie |
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Moved status register saving and adjustment, saving the unmodified value. |
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stage2/entry.S stage2/handlers.S
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128:2919aadc3118
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2016-02-25 |
Paul Boddie |
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Make a copy of the global offset table for user mode use. |
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stage2/head2.S stage2/stage2.ld
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127:f95ea4416370
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2016-02-24 |
Paul Boddie |
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Attempt to prevent a system hang by saving certain registers early. |
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stage2/entry.S stage2/handlers.S
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