1.1 --- a/include/jz4730.h Sun Jul 09 19:04:49 2017 +0200
1.2 +++ b/include/jz4730.h Tue Jul 11 00:03:30 2017 +0200
1.3 @@ -33,6 +33,10 @@
1.4 #define CONFIG_SYS_EXTAL 3686400 /* EXTAL freq: 3.7 MHz */
1.5 #define CONFIG_SYS_HZ (CONFIG_SYS_CPU_SPEED / (3*256)) /* incrementer freq */
1.6
1.7 +#define JZ_EXTAL CONFIG_SYS_EXTAL
1.8 +#define JZ_EXTAL2 32768 /* RTC clock */
1.9 +
1.10 +/* Register Definitions */
1.11 #define HARB_BASE 0xB3000000
1.12 #define EMC_BASE 0xB3010000
1.13 #define DMAC_BASE 0xB3020000
1.14 @@ -2198,41 +2202,8 @@
1.15 /*************************************************************************
1.16 * CPM
1.17 *************************************************************************/
1.18 -#define CPM_CFCR (CPM_BASE+0x00)
1.19 -#define CPM_PLCR1 (CPM_BASE+0x10)
1.20 -#define CPM_OCR (CPM_BASE+0x1c)
1.21 -#define CPM_CFCR2 (CPM_BASE+0x60)
1.22 -#define CPM_LPCR (CPM_BASE+0x04)
1.23 -#define CPM_RSTR (CPM_BASE+0x08)
1.24 -#define CPM_MSCR (CPM_BASE+0x20)
1.25 -#define CPM_SCR (CPM_BASE+0x24)
1.26 -#define CPM_WRER (CPM_BASE+0x28)
1.27 -#define CPM_WFER (CPM_BASE+0x2c)
1.28 -#define CPM_WER (CPM_BASE+0x30)
1.29 -#define CPM_WSR (CPM_BASE+0x34)
1.30 -#define CPM_GSR0 (CPM_BASE+0x38)
1.31 -#define CPM_GSR1 (CPM_BASE+0x3c)
1.32 -#define CPM_GSR2 (CPM_BASE+0x40)
1.33 -#define CPM_SPR (CPM_BASE+0x44)
1.34 -#define CPM_GSR3 (CPM_BASE+0x48)
1.35 -
1.36 -#define REG_CPM_CFCR REG32(CPM_CFCR)
1.37 -#define REG_CPM_PLCR1 REG32(CPM_PLCR1)
1.38 -#define REG_CPM_OCR REG32(CPM_OCR)
1.39 -#define REG_CPM_CFCR2 REG32(CPM_CFCR2)
1.40 -#define REG_CPM_LPCR REG32(CPM_LPCR)
1.41 -#define REG_CPM_RSTR REG32(CPM_RSTR)
1.42 -#define REG_CPM_MSCR REG32(CPM_MSCR)
1.43 -#define REG_CPM_SCR REG32(CPM_SCR)
1.44 -#define REG_CPM_WRER REG32(CPM_WRER)
1.45 -#define REG_CPM_WFER REG32(CPM_WFER)
1.46 -#define REG_CPM_WER REG32(CPM_WER)
1.47 -#define REG_CPM_WSR REG32(CPM_WSR)
1.48 -#define REG_CPM_GSR0 REG32(CPM_GSR0)
1.49 -#define REG_CPM_GSR1 REG32(CPM_GSR1)
1.50 -#define REG_CPM_GSR2 REG32(CPM_GSR2)
1.51 -#define REG_CPM_SPR REG32(CPM_SPR)
1.52 -#define REG_CPM_GSR3 REG32(CPM_GSR3)
1.53 +
1.54 +/* Register definitions with absolute positioning have been removed. */
1.55
1.56 #define CPM_CFCR_SSI (1 << 31)
1.57 #define CPM_CFCR_LCD (1 << 30)
1.58 @@ -4477,204 +4448,8 @@
1.59 /***************************************************************************
1.60 * CPM
1.61 ***************************************************************************/
1.62 -#define __cpm_plcr1_fd() \
1.63 - ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT)
1.64 -#define __cpm_plcr1_rd() \
1.65 - ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT)
1.66 -#define __cpm_plcr1_od() \
1.67 - ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT)
1.68 -#define __cpm_cfcr_mfr() \
1.69 - ((REG_CPM_CFCR & CPM_CFCR_MFR_MASK) >> CPM_CFCR_MFR_BIT)
1.70 -#define __cpm_cfcr_pfr() \
1.71 - ((REG_CPM_CFCR & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT)
1.72 -#define __cpm_cfcr_sfr() \
1.73 - ((REG_CPM_CFCR & CPM_CFCR_SFR_MASK) >> CPM_CFCR_SFR_BIT)
1.74 -#define __cpm_cfcr_ifr() \
1.75 - ((REG_CPM_CFCR & CPM_CFCR_IFR_MASK) >> CPM_CFCR_IFR_BIT)
1.76 -
1.77 -static __inline__ unsigned int __cpm_divisor_encode(unsigned int n)
1.78 -{
1.79 - unsigned int encode[10] = {1,2,3,4,6,8,12,16,24,32};
1.80 - int i;
1.81 - for (i=0;i<10;i++)
1.82 - if (n < encode[i])
1.83 - break;
1.84 - return i;
1.85 -}
1.86 -
1.87 -#define __cpm_set_mclk_div(n) \
1.88 -do { \
1.89 - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_MFR_MASK) | \
1.90 - ((n) << (CPM_CFCR_MFR_BIT)); \
1.91 -} while (0)
1.92 -
1.93 -#define __cpm_set_pclk_div(n) \
1.94 -do { \
1.95 - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_PFR_MASK) | \
1.96 - ((n) << (CPM_CFCR_PFR_BIT)); \
1.97 -} while (0)
1.98 -
1.99 -#define __cpm_set_sclk_div(n) \
1.100 -do { \
1.101 - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_SFR_MASK) | \
1.102 - ((n) << (CPM_CFCR_SFR_BIT)); \
1.103 -} while (0)
1.104 -
1.105 -#define __cpm_set_iclk_div(n) \
1.106 -do { \
1.107 - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_IFR_MASK) | \
1.108 - ((n) << (CPM_CFCR_IFR_BIT)); \
1.109 -} while (0)
1.110 -
1.111 -#define __cpm_set_lcdclk_div(n) \
1.112 -do { \
1.113 - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_LFR_MASK) | \
1.114 - ((n) << (CPM_CFCR_LFR_BIT)); \
1.115 -} while (0)
1.116 -
1.117 -#define __cpm_enable_cko1() (REG_CPM_CFCR |= CPM_CFCR_CKOEN1)
1.118 -#define __cpm_enable_cko2() (REG_CPM_CFCR |= CPM_CFCR_CKOEN2)
1.119 -#define __cpm_disable_cko1() (REG_CPM_CFCR &= ~CPM_CFCR_CKOEN1)
1.120 -#define __cpm_disable_cko2() (REG_CPM_CFCR &= ~CPM_CFCR_CKOEN2)
1.121 -
1.122 -#define __cpm_idle_mode() \
1.123 - (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \
1.124 - CPM_LPCR_LPM_IDLE)
1.125 -#define __cpm_sleep_mode() \
1.126 - (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \
1.127 - CPM_LPCR_LPM_SLEEP)
1.128 -#define __cpm_hibernate_mode() \
1.129 - (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \
1.130 - CPM_LPCR_LPM_HIBERNATE)
1.131 -
1.132 -#define __cpm_start_uart0() \
1.133 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART0))
1.134 -#define __cpm_start_uart1() \
1.135 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART1))
1.136 -#define __cpm_start_uart2() \
1.137 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART2))
1.138 -#define __cpm_start_uart3() \
1.139 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART3))
1.140 -#define __cpm_start_ost() \
1.141 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_OST))
1.142 -#define __cpm_start_dmac() \
1.143 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_DMAC))
1.144 -#define __cpm_start_uhc() \
1.145 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UHC))
1.146 -#define __cpm_start_lcd() \
1.147 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_LCD))
1.148 -#define __cpm_start_i2c() \
1.149 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_I2C))
1.150 -#define __cpm_start_aic_pclk() \
1.151 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_AICPCLK))
1.152 -#define __cpm_start_aic_bitclk() \
1.153 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_AICBCLK))
1.154 -#define __cpm_start_pwm0() \
1.155 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_PWM0))
1.156 -#define __cpm_start_pwm1() \
1.157 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_PWM1))
1.158 -#define __cpm_start_ssi() \
1.159 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_SSI))
1.160 -#define __cpm_start_msc() \
1.161 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_MSC))
1.162 -#define __cpm_start_scc() \
1.163 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_SCC))
1.164 -#define __cpm_start_eth() \
1.165 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_ETH))
1.166 -#define __cpm_start_kbc() \
1.167 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_KBC))
1.168 -#define __cpm_start_cim() \
1.169 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_CIM))
1.170 -#define __cpm_start_udc() \
1.171 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UDC))
1.172 -#define __cpm_start_uprt() \
1.173 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UPRT))
1.174 -#define __cpm_start_all() (REG_CPM_MSCR = 0)
1.175 -
1.176 -#define __cpm_stop_uart0() \
1.177 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART0))
1.178 -#define __cpm_stop_uart1() \
1.179 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART1))
1.180 -#define __cpm_stop_uart2() \
1.181 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART2))
1.182 -#define __cpm_stop_uart3() \
1.183 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART3))
1.184 -#define __cpm_stop_ost() \
1.185 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_OST))
1.186 -#define __cpm_stop_dmac() \
1.187 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_DMAC))
1.188 -#define __cpm_stop_uhc() \
1.189 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UHC))
1.190 -#define __cpm_stop_lcd() \
1.191 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_LCD))
1.192 -#define __cpm_stop_i2c() \
1.193 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_I2C))
1.194 -#define __cpm_stop_aic_pclk() \
1.195 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_AICPCLK))
1.196 -#define __cpm_stop_aic_bitclk() \
1.197 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_AICBCLK))
1.198 -#define __cpm_stop_pwm0() \
1.199 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_PWM0))
1.200 -#define __cpm_stop_pwm1() \
1.201 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_PWM1))
1.202 -#define __cpm_stop_ssi() \
1.203 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_SSI))
1.204 -#define __cpm_stop_msc() \
1.205 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_MSC))
1.206 -#define __cpm_stop_scc() \
1.207 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_SCC))
1.208 -#define __cpm_stop_eth() \
1.209 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_ETH))
1.210 -#define __cpm_stop_kbc() \
1.211 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_KBC))
1.212 -#define __cpm_stop_cim() \
1.213 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_CIM))
1.214 -#define __cpm_stop_udc() \
1.215 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UDC))
1.216 -#define __cpm_stop_uprt() \
1.217 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UPRT))
1.218 -#define __cpm_stop_all() (REG_CPM_MSCR = 0xffffffff)
1.219 -
1.220 -#define __cpm_set_pin(n) \
1.221 -do { \
1.222 - unsigned int p, o; \
1.223 - p = (n) / 32; \
1.224 - o = (n) % 32; \
1.225 - if (p == 0) \
1.226 - REG_CPM_GSR0 |= (1 << o); \
1.227 - else if (p == 1) \
1.228 - REG_CPM_GSR1 |= (1 << o); \
1.229 - else if (p == 2) \
1.230 - REG_CPM_GSR2 |= (1 << o); \
1.231 - else if (p == 3) \
1.232 - REG_CPM_GSR3 |= (1 << o); \
1.233 -} while (0)
1.234 -
1.235 -#define __cpm_clear_pin(n) \
1.236 -do { \
1.237 - unsigned int p, o; \
1.238 - p = (n) / 32; \
1.239 - o = (n) % 32; \
1.240 - if (p == 0) \
1.241 - REG_CPM_GSR0 &= ~(1 << o); \
1.242 - else if (p == 1) \
1.243 - REG_CPM_GSR1 &= ~(1 << o); \
1.244 - else if (p == 2) \
1.245 - REG_CPM_GSR2 &= ~(1 << o); \
1.246 - else if (p == 3) \
1.247 - REG_CPM_GSR3 &= ~(1 << o); \
1.248 -} while (0)
1.249 -
1.250 -
1.251 -#define __cpm_select_msc_clk(type) \
1.252 -do { \
1.253 - if (type == 0) \
1.254 - REG_CPM_CFCR &= ~CPM_CFCR_MSC; \
1.255 - else \
1.256 - REG_CPM_CFCR |= CPM_CFCR_MSC; \
1.257 - REG_CPM_CFCR |= CPM_CFCR_UPE; \
1.258 -} while(0)
1.259 -
1.260 +
1.261 +/* Register operations using absolute positioning have been removed. */
1.262
1.263 /***************************************************************************
1.264 * SSI
1.265 @@ -4837,101 +4612,6 @@
1.266 #define __wdt_start() ( REG_WDT_WTCSR |= WDT_WTCSR_START )
1.267 #define __wdt_stop() ( REG_WDT_WTCSR &= ~WDT_WTCSR_START )
1.268
1.269 -
1.270 -/***************************************************************************
1.271 - ***************************************************************************/
1.272 -
1.273 -/*
1.274 - * CPU clocks
1.275 - */
1.276 -#define JZ_EXTAL CONFIG_SYS_EXTAL
1.277 -#define JZ_EXTAL2 32768 /* RTC clock */
1.278 -
1.279 -static __inline__ unsigned int __cpm_get_pllout(void)
1.280 -{
1.281 - unsigned int nf, nr, no, pllout;
1.282 - unsigned long plcr = REG_CPM_PLCR1;
1.283 - unsigned long od[4] = {1, 2, 2, 4};
1.284 - if (plcr & CPM_PLCR1_PLL1EN) {
1.285 - nf = (plcr & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT;
1.286 - nr = (plcr & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT;
1.287 - no = od[((plcr & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT)];
1.288 - pllout = (JZ_EXTAL) / ((nr+2) * no) * (nf+2);
1.289 - } else
1.290 - pllout = JZ_EXTAL;
1.291 - return pllout;
1.292 -}
1.293 -
1.294 -static __inline__ unsigned int __cpm_get_iclk(void)
1.295 -{
1.296 - unsigned int iclk;
1.297 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.298 - unsigned long cfcr = REG_CPM_CFCR;
1.299 - unsigned long plcr = REG_CPM_PLCR1;
1.300 - if (plcr & CPM_PLCR1_PLL1EN)
1.301 - iclk = __cpm_get_pllout() /
1.302 - div[(cfcr & CPM_CFCR_IFR_MASK) >> CPM_CFCR_IFR_BIT];
1.303 - else
1.304 - iclk = JZ_EXTAL;
1.305 - return iclk;
1.306 -}
1.307 -
1.308 -static __inline__ unsigned int __cpm_get_sclk(void)
1.309 -{
1.310 - unsigned int sclk;
1.311 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.312 - unsigned long cfcr = REG_CPM_CFCR;
1.313 - unsigned long plcr = REG_CPM_PLCR1;
1.314 - if (plcr & CPM_PLCR1_PLL1EN)
1.315 - sclk = __cpm_get_pllout() /
1.316 - div[(cfcr & CPM_CFCR_SFR_MASK) >> CPM_CFCR_SFR_BIT];
1.317 - else
1.318 - sclk = JZ_EXTAL;
1.319 - return sclk;
1.320 -}
1.321 -
1.322 -static __inline__ unsigned int __cpm_get_mclk(void)
1.323 -{
1.324 - unsigned int mclk;
1.325 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.326 - unsigned long cfcr = REG_CPM_CFCR;
1.327 - unsigned long plcr = REG_CPM_PLCR1;
1.328 - if (plcr & CPM_PLCR1_PLL1EN)
1.329 - mclk = __cpm_get_pllout() /
1.330 - div[(cfcr & CPM_CFCR_MFR_MASK) >> CPM_CFCR_MFR_BIT];
1.331 - else
1.332 - mclk = JZ_EXTAL;
1.333 - return mclk;
1.334 -}
1.335 -
1.336 -static __inline__ unsigned int __cpm_get_pclk(void)
1.337 -{
1.338 - unsigned int devclk;
1.339 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.340 - unsigned long cfcr = REG_CPM_CFCR;
1.341 - unsigned long plcr = REG_CPM_PLCR1;
1.342 - if (plcr & CPM_PLCR1_PLL1EN)
1.343 - devclk = __cpm_get_pllout() /
1.344 - div[(cfcr & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT];
1.345 - else
1.346 - devclk = JZ_EXTAL;
1.347 - return devclk;
1.348 -}
1.349 -
1.350 -static __inline__ unsigned int __cpm_get_devclk(void)
1.351 -{
1.352 - unsigned int devclk;
1.353 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.354 - unsigned long cfcr = REG_CPM_CFCR;
1.355 - unsigned long plcr = REG_CPM_PLCR1;
1.356 - if (plcr & CPM_PLCR1_PLL1EN)
1.357 - devclk = __cpm_get_pllout() /
1.358 - div[(cfcr & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT];
1.359 - else
1.360 - devclk = JZ_EXTAL;
1.361 - return devclk;
1.362 -}
1.363 -
1.364 #endif /* !__ASSEMBLY__ */
1.365
1.366 #endif /* __JZ4730_H__ */