1.1 --- a/include/jz4740.h Sun Jul 09 19:04:49 2017 +0200
1.2 +++ b/include/jz4740.h Tue Jul 11 00:03:30 2017 +0200
1.3 @@ -4,7 +4,7 @@
1.4 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
1.5 * Copyright (C) 2009 Qi Hardware Inc.
1.6 * Author: Xiangfu Liu <xiangfu@sharism.cc>
1.7 - * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
1.8 + * Copyright (C) 2015, 2017 Paul Boddie <paul@boddie.org.uk>
1.9 *
1.10 * This program is free software; you can redistribute it and/or
1.11 * modify it under the terms of the GNU General Public License as
1.12 @@ -32,6 +32,9 @@
1.13 #define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
1.14 #define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */
1.15
1.16 +#define JZ_EXTAL CONFIG_SYS_EXTAL
1.17 +#define JZ_EXTAL2 32768 /* RTC clock */
1.18 +
1.19 /* Boot ROM Specification */
1.20 /* NOR Boot config */
1.21 #define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
1.22 @@ -180,47 +183,6 @@
1.23
1.24 /* Register definitions with absolute positioning have been removed. */
1.25
1.26 -#define CPM_CPCCR (CPM_BASE+0x00)
1.27 -#define CPM_CPPCR (CPM_BASE+0x10)
1.28 -#define CPM_I2SCDR (CPM_BASE+0x60)
1.29 -#define CPM_LPCDR (CPM_BASE+0x64)
1.30 -#define CPM_MSCCDR (CPM_BASE+0x68)
1.31 -#define CPM_UHCCDR (CPM_BASE+0x6C)
1.32 -
1.33 -#define CPM_LCR (CPM_BASE+0x04)
1.34 -#define CPM_CLKGR (CPM_BASE+0x20)
1.35 -#define CPM_SCR (CPM_BASE+0x24)
1.36 -
1.37 -#define CPM_HCR (CPM_BASE+0x30)
1.38 -#define CPM_HWFCR (CPM_BASE+0x34)
1.39 -#define CPM_HRCR (CPM_BASE+0x38)
1.40 -#define CPM_HWCR (CPM_BASE+0x3c)
1.41 -#define CPM_HWSR (CPM_BASE+0x40)
1.42 -#define CPM_HSPR (CPM_BASE+0x44)
1.43 -
1.44 -#define CPM_RSR (CPM_BASE+0x08)
1.45 -
1.46 -
1.47 -#define REG_CPM_CPCCR REG32(CPM_CPCCR)
1.48 -#define REG_CPM_CPPCR REG32(CPM_CPPCR)
1.49 -#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
1.50 -#define REG_CPM_LPCDR REG32(CPM_LPCDR)
1.51 -#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
1.52 -#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
1.53 -
1.54 -#define REG_CPM_LCR REG32(CPM_LCR)
1.55 -#define REG_CPM_CLKGR REG32(CPM_CLKGR)
1.56 -#define REG_CPM_SCR REG32(CPM_SCR)
1.57 -#define REG_CPM_HCR REG32(CPM_HCR)
1.58 -#define REG_CPM_HWFCR REG32(CPM_HWFCR)
1.59 -#define REG_CPM_HRCR REG32(CPM_HRCR)
1.60 -#define REG_CPM_HWCR REG32(CPM_HWCR)
1.61 -#define REG_CPM_HWSR REG32(CPM_HWSR)
1.62 -#define REG_CPM_HSPR REG32(CPM_HSPR)
1.63 -
1.64 -#define REG_CPM_RSR REG32(CPM_RSR)
1.65 -
1.66 -
1.67 /* Clock Control Register */
1.68 #define CPM_CPCCR_I2CS (1 << 31)
1.69 #define CPM_CPCCR_CLKOEN (1 << 30)
1.70 @@ -246,7 +208,7 @@
1.71
1.72 /* LCD Pixel Clock Divider Register */
1.73 #define CPM_LPCDR_PIXDIV_BIT 0
1.74 -#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT)
1.75 +#define CPM_LPCDR_PIXDIV_MASK (0x7ff << CPM_LPCDR_PIXDIV_BIT)
1.76
1.77 /* MSC Clock Divider Register */
1.78 #define CPM_MSCCDR_MSCDIV_BIT 0
1.79 @@ -3054,248 +3016,8 @@
1.80 /***************************************************************************
1.81 * CPM
1.82 ***************************************************************************/
1.83 -#define __cpm_get_pllm() \
1.84 - ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
1.85 -#define __cpm_get_plln() \
1.86 - ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
1.87 -#define __cpm_get_pllod() \
1.88 - ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
1.89 -
1.90 -#define __cpm_get_cdiv() \
1.91 - ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
1.92 -#define __cpm_get_hdiv() \
1.93 - ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
1.94 -#define __cpm_get_pdiv() \
1.95 - ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
1.96 -#define __cpm_get_mdiv() \
1.97 - ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
1.98 -#define __cpm_get_ldiv() \
1.99 - ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT)
1.100 -#define __cpm_get_udiv() \
1.101 - ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT)
1.102 -#define __cpm_get_i2sdiv() \
1.103 - ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
1.104 -#define __cpm_get_pixdiv() \
1.105 - ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
1.106 -#define __cpm_get_mscdiv() \
1.107 - ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
1.108 -
1.109 -#define __cpm_set_cdiv(v) \
1.110 - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
1.111 -#define __cpm_set_hdiv(v) \
1.112 - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
1.113 -#define __cpm_set_pdiv(v) \
1.114 - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
1.115 -#define __cpm_set_mdiv(v) \
1.116 - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
1.117 -#define __cpm_set_ldiv(v) \
1.118 - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
1.119 -#define __cpm_set_udiv(v) \
1.120 - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
1.121 -#define __cpm_set_i2sdiv(v) \
1.122 - (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
1.123 -#define __cpm_set_pixdiv(v) \
1.124 - (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
1.125 -#define __cpm_set_mscdiv(v) \
1.126 - (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
1.127 -
1.128 -#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS)
1.129 -#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS)
1.130 -#define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN)
1.131 -#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
1.132 -#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
1.133 -#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE)
1.134 -#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS)
1.135 -#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
1.136 -
1.137 -#define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS)
1.138 -#define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP)
1.139 -#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
1.140 -
1.141 -#define __cpm_get_cclk_doze_duty() \
1.142 - ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
1.143 -#define __cpm_set_cclk_doze_duty(v) \
1.144 - (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
1.145 -
1.146 -#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
1.147 -#define __cpm_idle_mode() \
1.148 - (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
1.149 -#define __cpm_sleep_mode() \
1.150 - (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
1.151 -
1.152 -#define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff)
1.153 -#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1)
1.154 -#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC)
1.155 -#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU)
1.156 -#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC)
1.157 -#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC)
1.158 -#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
1.159 -#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM)
1.160 -#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC)
1.161 -#define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC)
1.162 -#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1)
1.163 -#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2)
1.164 -#define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI)
1.165 -#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C)
1.166 -#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC)
1.167 -#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU)
1.168 -#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0)
1.169 -
1.170 -#define __cpm_start_all() (REG_CPM_CLKGR = 0x0)
1.171 -#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1)
1.172 -#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC)
1.173 -#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU)
1.174 -#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC)
1.175 -#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC)
1.176 -#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
1.177 -#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM)
1.178 -#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC)
1.179 -#define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC)
1.180 -#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1)
1.181 -#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2)
1.182 -#define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI)
1.183 -#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C)
1.184 -#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC)
1.185 -#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
1.186 -#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0)
1.187 -
1.188 -#define __cpm_get_o1st() \
1.189 - ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT)
1.190 -#define __cpm_set_o1st(v) \
1.191 - (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT)))
1.192 -#define __cpm_suspend_udcphy() (REG_CPM_SCR &= ~CPM_SCR_UDCPHY_ENABLE)
1.193 -#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_DISABLE)
1.194 -#define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE)
1.195 -
1.196 -#define JZ_EXTAL CONFIG_SYS_EXTAL
1.197 -#define JZ_EXTAL2 32768 /* RTC clock */
1.198 -
1.199 -/* PLL output frequency */
1.200 -static __inline__ unsigned int __cpm_get_pllout(void)
1.201 -{
1.202 - unsigned long m, n, no, pllout;
1.203 - unsigned long cppcr = REG_CPM_CPPCR;
1.204 - unsigned long od[4] = {1, 2, 2, 4};
1.205 - if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
1.206 - m = __cpm_get_pllm() + 2;
1.207 - n = __cpm_get_plln() + 2;
1.208 - no = od[__cpm_get_pllod()];
1.209 - pllout = ((JZ_EXTAL) / (n * no)) * m;
1.210 - } else
1.211 - pllout = JZ_EXTAL;
1.212 - return pllout;
1.213 -}
1.214 -
1.215 -/* PLL output frequency for MSC/I2S/LCD/USB */
1.216 -static __inline__ unsigned int __cpm_get_pllout2(void)
1.217 -{
1.218 - if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
1.219 - return __cpm_get_pllout();
1.220 - else
1.221 - return __cpm_get_pllout()/2;
1.222 -}
1.223 -
1.224 -/* CPU core clock */
1.225 -static __inline__ unsigned int __cpm_get_cclk(void)
1.226 -{
1.227 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.228 -
1.229 - return __cpm_get_pllout() / div[__cpm_get_cdiv()];
1.230 -}
1.231 -
1.232 -/* AHB system bus clock */
1.233 -static __inline__ unsigned int __cpm_get_hclk(void)
1.234 -{
1.235 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.236 -
1.237 - return __cpm_get_pllout() / div[__cpm_get_hdiv()];
1.238 -}
1.239 -
1.240 -/* Memory bus clock */
1.241 -static __inline__ unsigned int __cpm_get_mclk(void)
1.242 -{
1.243 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.244 -
1.245 - return __cpm_get_pllout() / div[__cpm_get_mdiv()];
1.246 -}
1.247 -
1.248 -/* APB peripheral bus clock */
1.249 -static __inline__ unsigned int __cpm_get_pclk(void)
1.250 -{
1.251 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.252 -
1.253 - return __cpm_get_pllout() / div[__cpm_get_pdiv()];
1.254 -}
1.255 -
1.256 -/* LCDC module clock */
1.257 -static __inline__ unsigned int __cpm_get_lcdclk(void)
1.258 -{
1.259 - return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1);
1.260 -}
1.261 -
1.262 -/* LCD pixel clock */
1.263 -static __inline__ unsigned int __cpm_get_pixclk(void)
1.264 -{
1.265 - return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
1.266 -}
1.267 -
1.268 -/* I2S clock */
1.269 -static __inline__ unsigned int __cpm_get_i2sclk(void)
1.270 -{
1.271 - if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) {
1.272 - return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
1.273 - }
1.274 - else {
1.275 - return JZ_EXTAL;
1.276 - }
1.277 -}
1.278 -
1.279 -/* USB clock */
1.280 -static __inline__ unsigned int __cpm_get_usbclk(void)
1.281 -{
1.282 - if (REG_CPM_CPCCR & CPM_CPCCR_UCS) {
1.283 - return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
1.284 - }
1.285 - else {
1.286 - return JZ_EXTAL;
1.287 - }
1.288 -}
1.289 -
1.290 -/* MSC clock */
1.291 -static __inline__ unsigned int __cpm_get_mscclk(void)
1.292 -{
1.293 - return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1);
1.294 -}
1.295 -
1.296 -/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
1.297 -static __inline__ unsigned int __cpm_get_extalclk(void)
1.298 -{
1.299 - return JZ_EXTAL;
1.300 -}
1.301 -
1.302 -/* RTC clock for CPM,INTC,RTC,TCU,WDT */
1.303 -static __inline__ unsigned int __cpm_get_rtcclk(void)
1.304 -{
1.305 - return JZ_EXTAL2;
1.306 -}
1.307 -
1.308 -/*
1.309 - * Output 24MHz for SD and 16MHz for MMC.
1.310 - */
1.311 -static inline void __cpm_select_msc_clk(int sd)
1.312 -{
1.313 - unsigned int pllout2 = __cpm_get_pllout2();
1.314 - unsigned int div = 0;
1.315 -
1.316 - if (sd) {
1.317 - div = pllout2 / 24000000;
1.318 - }
1.319 - else {
1.320 - div = pllout2 / 16000000;
1.321 - }
1.322 -
1.323 - REG_CPM_MSCCDR = div - 1;
1.324 -}
1.325 +
1.326 +/* Register operations using absolute positioning have been removed. */
1.327
1.328 /*
1.329 * TCU