1.1 --- a/stage1/board.c Sun Jul 09 19:04:49 2017 +0200
1.2 +++ b/stage1/board.c Tue Jul 11 00:03:30 2017 +0200
1.3 @@ -30,6 +30,7 @@
1.4
1.5 #include "memory.h"
1.6 #include "sdram.h"
1.7 +#include "cpm.h"
1.8 #include "usb_boot_defines.h"
1.9
1.10 /* These arguments are initialised by usbboot and are defined in...
1.11 @@ -111,7 +112,7 @@
1.12 pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
1.13
1.14 /* Divisor == UHCCDR + 1 */
1.15 - REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
1.16 + jz4740_cpm_ctrl_set((void *) CPM_BASE, CPM_UHCCDR, pllout2 / 48000000 - 1);
1.17 #endif
1.18
1.19 nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
1.20 @@ -122,15 +123,14 @@
1.21
1.22 /* Update PLL and wait. */
1.23
1.24 - REG_CPM_CPCCR = cfcr;
1.25 - REG_CPM_CPPCR = plcr1;
1.26 - while (!__cpm_pll_is_on());
1.27 + jz4740_cpm_ctrl_set((void *) CPM_BASE, CPM_CPCCR, cfcr);
1.28 + jz4740_cpm_ctrl_set((void *) CPM_BASE, CPM_CPPCR, plcr1);
1.29 + while (!jz4740_cpm_have_pll((void *) CPM_BASE));
1.30 }
1.31
1.32 void sdram_init()
1.33 {
1.34 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
1.35 - unsigned int pllout = __cpm_get_pllout();
1.36
1.37 unsigned int cas_latency_sdmr[2] = {
1.38 EMC_SDMR_CAS_2,
1.39 @@ -142,12 +142,8 @@
1.40 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
1.41 };
1.42
1.43 - /* Divisors for CPCCR values. */
1.44 -
1.45 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.46 -
1.47 - cpu_clk = pllout / div[__cpm_get_cdiv()];
1.48 - mem_clk = pllout / div[__cpm_get_mdiv()];
1.49 + cpu_clk = jz4740_cpm_get_cpu_frequency((void *) CPM_BASE);
1.50 + mem_clk = jz4740_cpm_get_memory_frequency((void *) CPM_BASE);
1.51
1.52 REG_EMC_BCR = 0; /* Disable bus release */
1.53 REG_EMC_RTCSR = 0; /* Disable clock for counting */