1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/stage2/cpm.h Tue Jul 11 00:03:30 2017 +0200
1.3 @@ -0,0 +1,77 @@
1.4 +#ifndef __CPM_H__
1.5 +#define __CPM_H__
1.6 +
1.7 +#include <stdint.h>
1.8 +
1.9 +/* Public functions. */
1.10 +
1.11 +int jz4740_init();
1.12 +
1.13 +int jz4740_cpm_have_pll(void *cpm_base);
1.14 +
1.15 +int jz4740_cpm_have_clock(void *cpm_base);
1.16 +void jz4740_cpm_start_clock(void *cpm_base);
1.17 +
1.18 +uint32_t jz4740_cpm_get_cpu_frequency(void *cpm_base);
1.19 +uint32_t jz4740_cpm_get_memory_frequency(void *cpm_base);
1.20 +
1.21 +void jz4740_cpm_set_lcd_frequencies(void *cpm_base, uint32_t pclk, uint8_t ratio);
1.22 +void jz4740_cpm_update_output_frequency(void *cpm_base);
1.23 +
1.24 +void jz4740_cpm_start_lcd(void *cpm_base);
1.25 +void jz4740_cpm_stop_lcd(void *cpm_base);
1.26 +
1.27 +uint32_t jz4740_cpm_ctrl_get(void *cpm_base, uint32_t reg);
1.28 +void jz4740_cpm_ctrl_set(void *cpm_base, uint32_t reg, uint32_t value);
1.29 +
1.30 +/* Register offsets. */
1.31 +
1.32 +#define CPM_CPCCR 0x00
1.33 +#define CPM_LCR 0x04
1.34 +#define CPM_RSR 0x08
1.35 +#define CPM_CPPCR 0x10
1.36 +
1.37 +#ifdef CONFIG_CPU_JZ4730
1.38 +
1.39 +/* Names used by the jz4730. */
1.40 +
1.41 +#define CPM_CFCR CPM_CPCCR
1.42 +#define CPM_LPCR CPM_LCR
1.43 +#define CPM_RSTR CPM_RSR
1.44 +#define CPM_PLCR1 CPM_CPPCR
1.45 +#define CPM_CFCR2 CPM_I2SCDR /* apparently used by the LCD */
1.46 +
1.47 +/* Registers used by the jz4730. */
1.48 +
1.49 +#define CPM_OCR 0x1c
1.50 +#define CPM_MSCR 0x20 /* different layout to CLKGR */
1.51 +#define CPM_WRER 0x28
1.52 +#define CPM_WFER 0x2c
1.53 +#define CPM_WER 0x30
1.54 +#define CPM_WSR 0x34
1.55 +#define CPM_GSR0 0x38
1.56 +#define CPM_GSR1 0x3c
1.57 +#define CPM_GSR2 0x40
1.58 +#define CPM_SPR 0x44
1.59 +#define CPM_GSR3 0x48
1.60 +
1.61 +#else
1.62 +
1.63 +/* Registers used by the jz4740. */
1.64 +
1.65 +#define CPM_CLKGR 0x20
1.66 +#define CPM_SCR 0x24
1.67 +#define CPM_HCR 0x30
1.68 +#define CPM_HWFCR 0x34
1.69 +#define CPM_HRCR 0x38
1.70 +#define CPM_HWCR 0x3c
1.71 +#define CPM_HWSR 0x40
1.72 +#define CPM_HSPR 0x44
1.73 +#define CPM_I2SCDR 0x60
1.74 +#define CPM_LPCDR 0x64
1.75 +#define CPM_MSCCDR 0x68
1.76 +#define CPM_UHCCDR 0x6C
1.77 +
1.78 +#endif
1.79 +
1.80 +#endif /* __CPM_H__ */