1.1 --- a/stage2/lcd.c Sun Jul 09 16:48:29 2017 +0200
1.2 +++ b/stage2/lcd.c Sun Jul 09 17:14:00 2017 +0200
1.3 @@ -22,11 +22,14 @@
1.4
1.5 #include "jzlcd.h"
1.6 #include "sdram.h"
1.7 +#include "cpu.h"
1.8 #include "board.h"
1.9
1.10 extern vidinfo_t panel_info;
1.11 static uint32_t lcd_base;
1.12
1.13 +
1.14 +
1.15 static uint16_t get_line_length()
1.16 {
1.17 return ALIGN((panel_info.jz_fb->w * panel_info.jz_fb->bpp) / 8, sizeof(uint32_t));
1.18 @@ -254,8 +257,101 @@
1.19 }
1.20 }
1.21
1.22 +
1.23 +
1.24 /* LCD initialisation. */
1.25
1.26 +#ifdef CONFIG_CPU_JZ4730
1.27 +void jz4730_set_lcd_frequencies(uint32_t pclk, uint8_t ratio)
1.28 +{
1.29 + uint32_t val;
1.30 +
1.31 + val = __cpm_get_pllout() / pclk;
1.32 + REG_CPM_CFCR2 = val - 1;
1.33 + val = pclk * ratio;
1.34 +
1.35 + if (val > 150000000) {
1.36 + val = 150000000;
1.37 + }
1.38 +
1.39 + val = __cpm_get_pllout() / val;
1.40 + val--;
1.41 +
1.42 + if (val > 0xF)
1.43 + val = 0xF;
1.44 +
1.45 + __cpm_set_ldiv(val);
1.46 + REG_CPM_CPCCR = REG_CPM_CPCCR | CPM_CPCCR_CE; /* update divide */
1.47 +}
1.48 +#else
1.49 +void jz4740_set_lcd_frequencies(uint32_t pclk, uint8_t ratio)
1.50 +{
1.51 + uint32_t val;
1.52 + int pll_div;
1.53 +
1.54 + pll_div = REG_CPM_CPCCR & CPM_CPCCR_PCS; /* clock source,0:pllout/2 1: pllout */
1.55 + pll_div = pll_div ? 1 : 2;
1.56 + val = (__cpm_get_pllout() / pll_div) / pclk;
1.57 + val--;
1.58 +
1.59 + if ( val > 0x1ff ) {
1.60 + val = 0x1ff;
1.61 + }
1.62 +
1.63 + __cpm_set_pixdiv(val);
1.64 +
1.65 + val = pclk * ratio; /* LCDClock > 2.5*Pixclock */
1.66 +
1.67 + if ( val > 150000000 ) {
1.68 + val = 150000000;
1.69 + }
1.70 +
1.71 + val = (__cpm_get_pllout() / pll_div) / val;
1.72 + val--;
1.73 +
1.74 + if (val > 0x1f)
1.75 + val = 0x1f;
1.76 +
1.77 + __cpm_set_ldiv(val);
1.78 + REG_CPM_CPCCR = REG_CPM_CPCCR | CPM_CPCCR_CE; /* update divide */
1.79 +}
1.80 +#endif
1.81 +
1.82 +void lcd_set_timing(vidinfo_t *vid)
1.83 +{
1.84 + uint32_t pclk = jz4740_lcd_get_pixel_clock(vid);
1.85 +
1.86 + __cpm_stop_lcd();
1.87 +
1.88 +#ifdef CONFIG_CPU_JZ4730
1.89 + jz4730_set_lcd_frequencies(pclk, 4);
1.90 +#else
1.91 + jz4740_set_lcd_frequencies(pclk, 3);
1.92 +#endif
1.93 +
1.94 + __cpm_start_lcd();
1.95 + udelay(1000);
1.96 +}
1.97 +
1.98 +uint32_t lcd_ctrl_init()
1.99 +{
1.100 + vidinfo_t *vid = &panel_info;
1.101 + struct jz_mem_info *fbi = &vid->jz_mem;
1.102 + void *fb_vaddr;
1.103 +
1.104 + /* Start from the top of memory and obtain the framebuffer region. */
1.105 +
1.106 + fb_vaddr = (void *) (get_memory_size() - jz4740_lcd_get_total_size(vid));
1.107 +
1.108 + jz4740_lcd_ctrl_init((void *) LCD_BASE_KSEG1, fb_vaddr, vid);
1.109 + flush_cache_all();
1.110 + jz4740_lcd_hw_init(vid);
1.111 + lcd_set_timing(vid);
1.112 + jz4740_lcd_dma_init(vid);
1.113 +
1.114 + return fbi->screen;
1.115 +}
1.116 +
1.117 void lcd_init()
1.118 {
1.119 __lcd_display_pin_init();