1.1 --- a/stage2/board.c Sun Jun 14 21:14:30 2015 +0200
1.2 +++ b/stage2/board.c Sun Jun 14 21:17:08 2015 +0200
1.3 @@ -1,7 +1,6 @@
1.4 /*
1.5 * Common routines supporting board initialisation.
1.6 *
1.7 - * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
1.8 * Copyright (C) 2005-2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
1.9 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com>
1.10 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
1.11 @@ -157,63 +156,3 @@
1.12 {
1.13 return TIMER_HZ;
1.14 }
1.15 -
1.16 -/* CPU-specific routines from U-Boot.
1.17 - See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c
1.18 - See: u-boot/arch/mips/include/asm/cacheops.h
1.19 -*/
1.20 -
1.21 -#define Index_Store_Tag_I 0x08
1.22 -#define Index_Writeback_Inv_D 0x15
1.23 -
1.24 -void flush_icache_all(void)
1.25 -{
1.26 - u32 addr, t = 0;
1.27 -
1.28 - asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
1.29 - asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
1.30 -
1.31 - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE;
1.32 - addr += CONFIG_SYS_CACHELINE_SIZE) {
1.33 - asm volatile (
1.34 - ".set mips3\n\t"
1.35 - " cache %0, 0(%1)\n\t"
1.36 - ".set mips2\n\t"
1.37 - :
1.38 - : "I" (Index_Store_Tag_I), "r"(addr));
1.39 - }
1.40 -
1.41 - /* invalicate btb */
1.42 - asm volatile (
1.43 - ".set mips32\n\t"
1.44 - "mfc0 %0, $16, 7\n\t"
1.45 - "nop\n\t"
1.46 - "ori %0,2\n\t"
1.47 - "mtc0 %0, $16, 7\n\t"
1.48 - ".set mips2\n\t"
1.49 - :
1.50 - : "r" (t));
1.51 -}
1.52 -
1.53 -void flush_dcache_all(void)
1.54 -{
1.55 - u32 addr;
1.56 -
1.57 - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
1.58 - addr += CONFIG_SYS_CACHELINE_SIZE) {
1.59 - asm volatile (
1.60 - ".set mips3\n\t"
1.61 - " cache %0, 0(%1)\n\t"
1.62 - ".set mips2\n\t"
1.63 - :
1.64 - : "I" (Index_Writeback_Inv_D), "r"(addr));
1.65 - }
1.66 -
1.67 - asm volatile ("sync");
1.68 -}
1.69 -
1.70 -void flush_cache_all(void)
1.71 -{
1.72 - flush_dcache_all();
1.73 - flush_icache_all();
1.74 -}