1.1 --- a/stage2/jzlcd.h Sun Jul 09 01:47:02 2017 +0200
1.2 +++ b/stage2/jzlcd.h Sun Jul 09 16:00:26 2017 +0200
1.3 @@ -136,6 +136,34 @@
1.4 #define DATA_NORMAL (0 << 17)
1.5 #define DATA_INVERSE (1 << 17)
1.6
1.7 +/* LCD register base. */
1.8 +
1.9 +#define LCD_BASE_KSEG1 0xB3050000
1.10 +
1.11 +/* Register offsets. */
1.12 +
1.13 +#define LCD_CFG 0x00 /* LCD Configure Register */
1.14 +#define LCD_VSYNC 0x04 /* Vertical Synchronize Register */
1.15 +#define LCD_HSYNC 0x08 /* Horizontal Synchronize Register */
1.16 +#define LCD_VAT 0x0c /* Virtual Area Setting Register */
1.17 +#define LCD_DAH 0x10 /* Display Area Horizontal Start/End Point */
1.18 +#define LCD_DAV 0x14 /* Display Area Vertical Start/End Point */
1.19 +#define LCD_PS 0x18 /* PS Signal Setting */
1.20 +#define LCD_CLS 0x1c /* CLS Signal Setting */
1.21 +#define LCD_SPL 0x20 /* SPL Signal Setting */
1.22 +#define LCD_REV 0x24 /* REV Signal Setting */
1.23 +#define LCD_CTRL 0x30 /* LCD Control Register */
1.24 +#define LCD_STATE 0x34 /* LCD Status Register */
1.25 +#define LCD_IID 0x38 /* Interrupt ID Register */
1.26 +#define LCD_DA0 0x40 /* Descriptor Address Register 0 */
1.27 +#define LCD_SA0 0x44 /* Source Address Register 0 */
1.28 +#define LCD_FID0 0x48 /* Frame ID Register 0 */
1.29 +#define LCD_CMD0 0x4c /* DMA Command Register 0 */
1.30 +#define LCD_DA1 0x50 /* Descriptor Address Register 1 */
1.31 +#define LCD_SA1 0x54 /* Source Address Register 1 */
1.32 +#define LCD_FID1 0x58 /* Frame ID Register 1 */
1.33 +#define LCD_CMD1 0x5c /* DMA Command Register 1 */
1.34 +
1.35 /* Palette buffer (LCD_CMDx.PAL). */
1.36
1.37 #define LCD_CMD_PAL (1 << 28)