1.1 --- a/stage2/cpu.c Wed Jun 28 00:20:14 2017 +0200
1.2 +++ b/stage2/cpu.c Wed Jun 28 01:04:22 2017 +0200
1.3 @@ -4,7 +4,7 @@
1.4 * See: u-boot/arch/mips/include/asm/cacheops.h
1.5 *
1.6 * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
1.7 - * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk>
1.8 + * Copyright (C) 2015, 2016, 2017 Paul Boddie <paul@boddie.org.uk>
1.9 *
1.10 * This program is free software; you can redistribute it and/or
1.11 * modify it under the terms of the GNU General Public License as
1.12 @@ -30,7 +30,7 @@
1.13
1.14 void flush_icache_all()
1.15 {
1.16 - u32 addr;
1.17 + uint32_t addr;
1.18
1.19 flush_icache_tag();
1.20
1.21 @@ -42,7 +42,7 @@
1.22
1.23 void flush_dcache_all()
1.24 {
1.25 - u32 addr;
1.26 + uint32_t addr;
1.27
1.28 for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE)
1.29 flush_dcache_region(addr);
1.30 @@ -56,9 +56,9 @@
1.31 flush_icache_all();
1.32 }
1.33
1.34 -void init_registers(u32 *base, u32 got, void (*function)(), u32 args[], u8 nargs)
1.35 +void init_registers(uint32_t *base, uint32_t got, void (*function)(), uint32_t args[], uint8_t nargs)
1.36 {
1.37 - u8 i;
1.38 + uint8_t i;
1.39
1.40 /* Provide arguments to the function. */
1.41
1.42 @@ -69,14 +69,14 @@
1.43
1.44 /* Store essential data for the function environment. */
1.45
1.46 - base[25] = (u32) function - 0x80000000; /* store the function address as t9 */
1.47 + base[25] = (uint32_t) function - 0x80000000; /* store the function address as t9 */
1.48 base[26] = got - 0x80000000; /* store the global pointer */
1.49 - base[29] = (u32) function - 0x80000000; /* store the function address as EPC (for the handler) */
1.50 + base[29] = (uint32_t) function - 0x80000000; /* store the function address as EPC (for the handler) */
1.51 }
1.52
1.53 -void init_tlb(u8 first_random)
1.54 +void init_tlb(uint8_t first_random)
1.55 {
1.56 - u32 limit = configure_tlb(first_random), i;
1.57 + uint32_t limit = configure_tlb(first_random), i;
1.58
1.59 /* Reset the mappings. The total number is bits 30..25 of Config1. */
1.60
1.61 @@ -86,10 +86,10 @@
1.62 }
1.63 }
1.64
1.65 -void init_page_table(u32 page_table, u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid)
1.66 +void init_page_table(uint32_t page_table, uint32_t virtual, uint32_t physical, uint32_t pagesize, uint8_t flags, uint8_t asid)
1.67 {
1.68 - u32 lower = ((physical & 0xfffff000) >> 6) | flags;
1.69 - u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags;
1.70 + uint32_t lower = ((physical & 0xfffff000) >> 6) | flags;
1.71 + uint32_t upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags;
1.72
1.73 /*
1.74 With a complete address space mapping involving pairs of 4KB pages
1.75 @@ -121,12 +121,12 @@
1.76 0x1000 * 8 == 0x8000 bytes
1.77 */
1.78
1.79 - u32 base = page_table + STAGE2_PAGE_TABLE_TASK * asid;
1.80 + uint32_t base = page_table + STAGE2_PAGE_TABLE_TASK * asid;
1.81
1.82 /* Each page table entry corresponds to a pair of 4KB pages and holds two values. */
1.83
1.84 - u32 entry = ((virtual & 0xffffe000) >> 13) * 8;
1.85 - u32 *address = (u32 *) (base + entry);
1.86 + uint32_t entry = ((virtual & 0xffffe000) >> 13) * 8;
1.87 + uint32_t *address = (uint32_t *) (base + entry);
1.88
1.89 /* The page tables should be permanently mapped to avoid hierarchical TLB miss handling. */
1.90
1.91 @@ -134,22 +134,22 @@
1.92 *(address + 1) = upper;
1.93 }
1.94
1.95 -void map_page(u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid)
1.96 +void map_page(uint32_t virtual, uint32_t physical, uint32_t pagesize, uint8_t flags, uint8_t asid)
1.97 {
1.98 - u32 start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/
1.99 - u32 lower = ((physical & 0xfffff000) >> 6) | flags;
1.100 - u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags;
1.101 - u32 pagemask = ((pagesize - 1) & 0xfffff000) << 1;
1.102 + uint32_t start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/
1.103 + uint32_t lower = ((physical & 0xfffff000) >> 6) | flags;
1.104 + uint32_t upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags;
1.105 + uint32_t pagemask = ((pagesize - 1) & 0xfffff000) << 1;
1.106
1.107 map_page_op(lower, upper, start, pagemask);
1.108 }
1.109
1.110 -void map_page_index(u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid, u32 index)
1.111 +void map_page_index(uint32_t virtual, uint32_t physical, uint32_t pagesize, uint8_t flags, uint8_t asid, uint32_t index)
1.112 {
1.113 - u32 start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/
1.114 - u32 lower = ((physical & 0xfffff000) >> 6) | flags;
1.115 - u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags;
1.116 - u32 pagemask = ((pagesize - 1) & 0xfffff000) << 1;
1.117 + uint32_t start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/
1.118 + uint32_t lower = ((physical & 0xfffff000) >> 6) | flags;
1.119 + uint32_t upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags;
1.120 + uint32_t pagemask = ((pagesize - 1) & 0xfffff000) << 1;
1.121
1.122 map_page_set_index(index);
1.123 map_page_index_op(lower, upper, start, pagemask);