1.1 --- a/include/jz4740.h Sun Jul 09 17:14:00 2017 +0200
1.2 +++ b/include/jz4740.h Sun Jul 09 18:31:15 2017 +0200
1.3 @@ -177,6 +177,9 @@
1.4 /*************************************************************************
1.5 * CPM (Clock reset and Power control Management)
1.6 *************************************************************************/
1.7 +
1.8 +/* Register definitions with absolute positioning have been removed. */
1.9 +
1.10 #define CPM_CPCCR (CPM_BASE+0x00)
1.11 #define CPM_CPPCR (CPM_BASE+0x10)
1.12 #define CPM_I2SCDR (CPM_BASE+0x60)
1.13 @@ -4327,216 +4330,8 @@
1.14 /***************************************************************************
1.15 * LCD
1.16 ***************************************************************************/
1.17 -#define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) )
1.18 -#define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) )
1.19 -
1.20 -#define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS )
1.21 -#define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
1.22 -
1.23 -#define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA )
1.24 -#define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
1.25 -
1.26 -/* n=1,2,4,8,16 */
1.27 -#define __lcd_set_bpp(n) \
1.28 - ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
1.29 -
1.30 -/* n=4,8,16 */
1.31 -#define __lcd_set_burst_length(n) \
1.32 -do { \
1.33 - REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \
1.34 - REG_LCD_CTRL |= LCD_CTRL_BST_n##; \
1.35 -} while (0)
1.36 -
1.37 -#define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
1.38 -#define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
1.39 -
1.40 -#define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP )
1.41 -#define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
1.42 -
1.43 -/* n=2,4,16 */
1.44 -#define __lcd_set_stn_frc(n) \
1.45 -do { \
1.46 - REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \
1.47 - REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \
1.48 -} while (0)
1.49 -
1.50 -
1.51 -#define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN )
1.52 -#define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
1.53 -
1.54 -#define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN )
1.55 -#define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
1.56 -
1.57 -#define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM )
1.58 -#define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
1.59 -
1.60 -#define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM )
1.61 -#define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
1.62 -
1.63 -#define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM )
1.64 -#define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
1.65 -
1.66 -#define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
1.67 -#define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
1.68 -
1.69 -#define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
1.70 -#define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
1.71 -
1.72 -#define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM )
1.73 -#define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
1.74 -
1.75 -#define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM )
1.76 -#define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
1.77 -
1.78 -
1.79 -/* LCD status register indication */
1.80 -
1.81 -#define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD )
1.82 -#define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD )
1.83 -#define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 )
1.84 -#define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 )
1.85 -#define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU )
1.86 -#define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF )
1.87 -#define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF )
1.88 -
1.89 -#define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU )
1.90 -#define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF )
1.91 -#define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF )
1.92 -
1.93 -#define __lcd_panel_white() ( REG_LCD_CFG |= LCD_CFG_WHITE )
1.94 -#define __lcd_panel_black() ( REG_LCD_CFG &= ~LCD_CFG_WHITE )
1.95 -
1.96 -/* n=1,2,4,8 for single mono-STN
1.97 - * n=4,8 for dual mono-STN
1.98 - */
1.99 -#define __lcd_set_panel_datawidth(n) \
1.100 -do { \
1.101 - REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \
1.102 - REG_LCD_CFG |= LCD_CFG_PDW_n##; \
1.103 -} while (0)
1.104 -
1.105 -/* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */
1.106 -#define __lcd_set_panel_mode(m) \
1.107 -do { \
1.108 - REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \
1.109 - REG_LCD_CFG |= (m); \
1.110 -} while(0)
1.111 -
1.112 -/* n = 0-255 */
1.113 -#define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff )
1.114 -#define __lcd_set_ac_bias(n) \
1.115 -do { \
1.116 - REG_LCD_IO &= ~LCD_IO_ACB_MASK; \
1.117 - REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \
1.118 -} while(0)
1.119 -
1.120 -#define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR )
1.121 -#define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR )
1.122 -
1.123 -#define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP )
1.124 -#define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP )
1.125 -
1.126 -#define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP )
1.127 -#define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP )
1.128 -
1.129 -#define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP )
1.130 -#define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP )
1.131 -
1.132 -#define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP )
1.133 -#define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP )
1.134 -
1.135 -#define __lcd_vsync_get_vps() \
1.136 - ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
1.137 -
1.138 -#define __lcd_vsync_get_vpe() \
1.139 - ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
1.140 -#define __lcd_vsync_set_vpe(n) \
1.141 -do { \
1.142 - REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \
1.143 - REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \
1.144 -} while (0)
1.145 -
1.146 -#define __lcd_hsync_get_hps() \
1.147 - ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
1.148 -#define __lcd_hsync_set_hps(n) \
1.149 -do { \
1.150 - REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \
1.151 - REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \
1.152 -} while (0)
1.153 -
1.154 -#define __lcd_hsync_get_hpe() \
1.155 - ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
1.156 -#define __lcd_hsync_set_hpe(n) \
1.157 -do { \
1.158 - REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \
1.159 - REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \
1.160 -} while (0)
1.161 -
1.162 -#define __lcd_vat_get_ht() \
1.163 - ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
1.164 -#define __lcd_vat_set_ht(n) \
1.165 -do { \
1.166 - REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \
1.167 - REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \
1.168 -} while (0)
1.169 -
1.170 -#define __lcd_vat_get_vt() \
1.171 - ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
1.172 -#define __lcd_vat_set_vt(n) \
1.173 -do { \
1.174 - REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \
1.175 - REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \
1.176 -} while (0)
1.177 -
1.178 -#define __lcd_dah_get_hds() \
1.179 - ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
1.180 -#define __lcd_dah_set_hds(n) \
1.181 -do { \
1.182 - REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \
1.183 - REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \
1.184 -} while (0)
1.185 -
1.186 -#define __lcd_dah_get_hde() \
1.187 - ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
1.188 -#define __lcd_dah_set_hde(n) \
1.189 -do { \
1.190 - REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \
1.191 - REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \
1.192 -} while (0)
1.193 -
1.194 -#define __lcd_dav_get_vds() \
1.195 - ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
1.196 -#define __lcd_dav_set_vds(n) \
1.197 -do { \
1.198 - REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \
1.199 - REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \
1.200 -} while (0)
1.201 -
1.202 -#define __lcd_dav_get_vde() \
1.203 - ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
1.204 -#define __lcd_dav_set_vde(n) \
1.205 -do { \
1.206 - REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \
1.207 - REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \
1.208 -} while (0)
1.209 -
1.210 -#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
1.211 -#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
1.212 -#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
1.213 -#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
1.214 -
1.215 -#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
1.216 -#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
1.217 -#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
1.218 -#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
1.219 -
1.220 -#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL )
1.221 -#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
1.222 -
1.223 -#define __lcd_cmd0_get_len() \
1.224 - ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
1.225 -#define __lcd_cmd1_get_len() \
1.226 - ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
1.227 +
1.228 +/* Register operations using absolute positioning have been removed. */
1.229
1.230 /***************************************************************************
1.231 * RTC ops