1.1 --- a/stage2/jzlcd.h Sun Jul 09 18:31:15 2017 +0200
1.2 +++ b/stage2/jzlcd.h Sun Jul 09 19:04:49 2017 +0200
1.3 @@ -1,8 +1,10 @@
1.4 /*
1.5 - * U-Boot and JzRISC LCD controller definitions
1.6 + * U-Boot and jz4740 LCD controller definitions.
1.7 *
1.8 * Copyright (C) 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
1.9 * Copyright (C) 2005-2007, Ingenic Semiconductor Inc.
1.10 + * Copyright (C) 2009 Qi Hardware Inc.
1.11 + * Author: Xiangfu Liu <xiangfu@sharism.cc>
1.12 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
1.13 * Copyright (C) 2015, 2016, 2017 Paul Boddie <paul@boddie.org.uk>
1.14 *
1.15 @@ -67,6 +69,8 @@
1.16 struct jz_fb_dma_descriptor *dmadesc_fb1;
1.17 struct jz_fb_dma_descriptor *dmadesc_palette;
1.18
1.19 + /* Region addresses. */
1.20 +
1.21 uint32_t screen; /* address of first frame buffer (base of memory used) */
1.22 uint32_t palette; /* address of palette memory */
1.23 uint32_t total; /* total memory used */
1.24 @@ -80,6 +84,8 @@
1.25 void *lcd; /* address of LCD controller registers */
1.26 } vidinfo_t;
1.27
1.28 +
1.29 +
1.30 /* Public functions. */
1.31
1.32 uint32_t jz4740_lcd_get_total_size(vidinfo_t *vid);
1.33 @@ -87,17 +93,19 @@
1.34 void jz4740_lcd_ctrl_init(void *lcd_base, void *fb_vaddr, vidinfo_t *vid);
1.35 void jz4740_lcd_hw_init(vidinfo_t *vid);
1.36 void jz4740_lcd_dma_init(vidinfo_t *vid);
1.37 -void lcd_set_bpp(uint8_t bpp);
1.38 -uint32_t lcd_ctrl_init();
1.39 -void lcd_enable();
1.40 -void lcd_disable();
1.41 +void jz4740_lcd_set_bpp(uint8_t bpp, vidinfo_t *vid);
1.42 +void jz4740_lcd_enable(vidinfo_t *vid);
1.43 +void jz4740_lcd_disable(vidinfo_t *vid);
1.44 +void jz4740_lcd_quick_disable(vidinfo_t *vid);
1.45 +
1.46 +
1.47
1.48 /* Alignment/rounding macros. */
1.49
1.50 #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
1.51 #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
1.52
1.53 -/* Transfer and display types. */
1.54 +/* Display device mode select (LCD_CFG.MODE). */
1.55
1.56 #define MODE_MASK 0x0f
1.57 #define MODE_TFT_GEN 0x00
1.58 @@ -112,40 +120,54 @@
1.59 #define MODE_STN_MONO_DUAL 0x0b
1.60 #define MODE_8BIT_SERIAL_TFT 0x0c
1.61
1.62 +/* 16-bit or 18-bit TFT panel selection (LCD_CFG.18/16). */
1.63 +
1.64 #define MODE_TFT_18BIT (1<<7)
1.65
1.66 -#define STN_DAT_PIN1 (0x00 << 4)
1.67 -#define STN_DAT_PIN2 (0x01 << 4)
1.68 -#define STN_DAT_PIN4 (0x02 << 4)
1.69 -#define STN_DAT_PIN8 (0x03 << 4)
1.70 -#define STN_DAT_PINMASK STN_DAT_PIN8
1.71 +/* STN pin utilisation (LCD_CFG.PDW). */
1.72 +
1.73 +#define STN_DAT_PIN1 (0x00 << 4)
1.74 +#define STN_DAT_PIN2 (0x01 << 4)
1.75 +#define STN_DAT_PIN4 (0x02 << 4)
1.76 +#define STN_DAT_PIN8 (0x03 << 4)
1.77 +#define STN_DAT_PINMASK STN_DAT_PIN8
1.78 +
1.79 +/* Pin reset states (LCD_CFG). */
1.80
1.81 -#define STFT_PSHI (1 << 15)
1.82 -#define STFT_CLSHI (1 << 14)
1.83 -#define STFT_SPLHI (1 << 13)
1.84 -#define STFT_REVHI (1 << 12)
1.85 +#define STFT_PSHI (1 << 15)
1.86 +#define STFT_CLSHI (1 << 14)
1.87 +#define STFT_SPLHI (1 << 13)
1.88 +#define STFT_REVHI (1 << 12)
1.89
1.90 -#define SYNC_MASTER (0 << 16)
1.91 -#define SYNC_SLAVE (1 << 16)
1.92 +/* Sync direction (LCD_CFG.SYNDIR). */
1.93 +
1.94 +#define SYNC_MASTER (0 << 16)
1.95 +#define SYNC_SLAVE (1 << 16)
1.96 +
1.97 +/* Data enable polarity (LCD_CFG.DEP). */
1.98
1.99 -#define DE_P (0 << 9)
1.100 -#define DE_N (1 << 9)
1.101 +#define DE_P (0 << 9)
1.102 +#define DE_N (1 << 9)
1.103 +
1.104 +/* Pixel clock polarity (LCD_CFG.PCP). */
1.105
1.106 -#define PCLK_P (0 << 10)
1.107 -#define PCLK_N (1 << 10)
1.108 +#define PCLK_P (0 << 10)
1.109 +#define PCLK_N (1 << 10)
1.110
1.111 -#define HSYNC_P (0 << 11)
1.112 -#define HSYNC_N (1 << 11)
1.113 +/* Horizontal sync polarity (LCD_CFG.HSP). */
1.114
1.115 -#define VSYNC_P (0 << 8)
1.116 -#define VSYNC_N (1 << 8)
1.117 +#define HSYNC_P (0 << 11)
1.118 +#define HSYNC_N (1 << 11)
1.119 +
1.120 +/* Vertical sync polarity (LCD_CFG.VSP). */
1.121
1.122 -#define DATA_NORMAL (0 << 17)
1.123 -#define DATA_INVERSE (1 << 17)
1.124 +#define VSYNC_P (0 << 8)
1.125 +#define VSYNC_N (1 << 8)
1.126
1.127 -/* LCD register base. */
1.128 +/* Inverse output data (LCD_CFG.INVDAT). */
1.129
1.130 -#define LCD_BASE_KSEG1 0xB3050000
1.131 +#define DATA_NORMAL (0 << 17)
1.132 +#define DATA_INVERSE (1 << 17)
1.133
1.134 /* Register offsets. */
1.135