1.1 --- a/stage2/nanonote_gpm940b0.c Tue Jul 11 18:45:08 2017 +0200
1.2 +++ b/stage2/nanonote_gpm940b0.c Wed Jul 12 15:46:53 2017 +0200
1.3 @@ -1,5 +1,5 @@
1.4 /*
1.5 - * Ben NanoNote screen details
1.6 + * Ben NanoNote screen details and panel-specific functions.
1.7 *
1.8 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
1.9 * Copyright (C) 2015, 2016, 2017 Paul Boddie <paul@boddie.org.uk>
1.10 @@ -20,9 +20,10 @@
1.11 * Boston, MA 02110-1301, USA
1.12 */
1.13
1.14 -#include "nanonote_gpm940b0.h"
1.15 +#include "board.h"
1.16 #include "jzlcd.h"
1.17 #include "nanonote.h"
1.18 +#include "gpio.h"
1.19
1.20 struct jzfb_info jzfb = {
1.21 .cfg=MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
1.22 @@ -38,3 +39,52 @@
1.23 .jz_fb=&jzfb, // this will need correcting for user mode usage
1.24 .lcd=0, // base address for registers
1.25 };
1.26 +
1.27 +/* Display configuration functions. */
1.28 +
1.29 +static void spi_write_reg1(uint8_t reg, uint8_t val)
1.30 +{
1.31 + uint8_t no;
1.32 + uint16_t value;
1.33 + void *gpio_port_base = jz4740_gpio_get_port((void *) GPIO_BASE, GPIO_PORT_LCD);
1.34 +
1.35 + jz4740_gpio_set_pin(gpio_port_base, SPEN);
1.36 + jz4740_gpio_set_pin(gpio_port_base, SPCK);
1.37 + jz4740_gpio_clear_pin(gpio_port_base, SPDA);
1.38 + jz4740_gpio_clear_pin(gpio_port_base, SPEN);
1.39 +
1.40 + value = ((reg << 8) | (val & 0xFF));
1.41 +
1.42 + for (no = 0; no < 16; no++)
1.43 + {
1.44 + jz4740_gpio_clear_pin(gpio_port_base, SPCK);
1.45 + jz4740_gpio_set_value(gpio_port_base, SPDA, value & 0x8000 ? 1 : 0);
1.46 + jz4740_gpio_set_pin(gpio_port_base, SPCK);
1.47 + value = (value << 1);
1.48 + }
1.49 +
1.50 + jz4740_gpio_set_pin(gpio_port_base, SPEN);
1.51 +}
1.52 +
1.53 +void lcd_display_pin_init()
1.54 +{
1.55 + void *gpio_port_base = jz4740_gpio_get_port((void *) GPIO_BASE, GPIO_PORT_LCD);
1.56 +
1.57 + jz4740_gpio_as_output(gpio_port_base, SPEN);
1.58 + jz4740_gpio_as_output(gpio_port_base, SPCK);
1.59 + jz4740_gpio_as_output(gpio_port_base, SPDA);
1.60 +}
1.61 +
1.62 +void lcd_display_on()
1.63 +{
1.64 + spi_write_reg1(0x05, 0x1e);
1.65 + spi_write_reg1(0x05, 0x5e);
1.66 + spi_write_reg1(0x07, 0x8d);
1.67 + spi_write_reg1(0x13, 0x01);
1.68 + spi_write_reg1(0x05, 0x5f);
1.69 +}
1.70 +
1.71 +void lcd_display_off()
1.72 +{
1.73 + spi_write_reg1(0x05, 0x5e);
1.74 +}