1.1 --- a/include/nanonote.h Tue Jun 09 00:03:27 2015 +0200
1.2 +++ b/include/nanonote.h Tue Jun 09 21:10:40 2015 +0200
1.3 @@ -1,7 +1,7 @@
1.4 /*
1.5 - * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
1.6 * Copyright (C) 2009 Qi Hardware Inc.
1.7 * Authors: Xiangfu Liu <xiangfu@openmobilefree.net>
1.8 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
1.9 *
1.10 * This program is free software; you can redistribute it and/or
1.11 * modify it under the terms of the GNU General Public License
1.12 @@ -33,44 +33,6 @@
1.13 #define LCD_BPP LCD_COLOR32
1.14
1.15 /*
1.16 - * RAM configuration
1.17 - */
1.18 -#define CONFIG_SYS_SDRAM_BASE 0x80000000
1.19 -
1.20 -/*
1.21 - * SDRAM configuration (timings in ns)
1.22 - */
1.23 -#define CONFIG_NR_DRAM_BANKS 1
1.24 -
1.25 -#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
1.26 -#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
1.27 -#define SDRAM_ROW 13 /* Row address: 11 to 13 */
1.28 -#define SDRAM_COL 9 /* Column address: 8 to 12 */
1.29 -#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
1.30 -#define SDRAM_TRAS 45 /* RAS# Active Time */
1.31 -#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
1.32 -#define SDRAM_TPC 20 /* RAS# Precharge Time */
1.33 -#define SDRAM_TRWL 7 /* Write Latency Time */
1.34 -#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
1.35 -
1.36 -#define SDRAM_ROW0 11 /* Row address minimum */
1.37 -#define SDRAM_COL0 8 /* Column address minimum */
1.38 -#define SDRAM_BANK40 0 /* Bank minimum */
1.39 -
1.40 -/*
1.41 - * Cache configuration
1.42 - */
1.43 -#define CONFIG_SYS_DCACHE_SIZE 16384
1.44 -#define CONFIG_SYS_ICACHE_SIZE 16384
1.45 -#define CONFIG_SYS_CACHELINE_SIZE 32
1.46 -
1.47 -/*
1.48 - * Memory configuration
1.49 - */
1.50 -#define KSEG0 0x80000000
1.51 -#define PAGE_SIZE 4096
1.52 -
1.53 -/*
1.54 * GPIO definition
1.55 * See: http://en.qi-hardware.com/wiki/Hardware_basics
1.56 */