1.1 --- a/stage1/board-nanonote.c Tue Jun 09 00:03:27 2015 +0200
1.2 +++ b/stage1/board-nanonote.c Tue Jun 09 21:10:40 2015 +0200
1.3 @@ -3,7 +3,7 @@
1.4 *
1.5 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
1.6 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com>
1.7 - * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
1.8 + * Copyright (C) 2005-2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
1.9 * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
1.10 *
1.11 * This program is free software; you can redistribute it and/or modify it under
1.12 @@ -21,7 +21,7 @@
1.13 */
1.14
1.15 #include "jz4740.h"
1.16 -#include "nanonote.h"
1.17 +#include "sdram.h"
1.18 #include "usb_boot_defines.h"
1.19
1.20 /* These arguments are initialised by usbboot and are defined in...
1.21 @@ -82,16 +82,19 @@
1.22 (2 << CPM_CPCCR_MDIV_BIT) |
1.23 (2 << CPM_CPCCR_LDIV_BIT);
1.24
1.25 - /* Determine the divider clock output based on the PCS bit. */
1.26 -
1.27 - pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
1.28 -
1.29 /* Init USB Host clock.
1.30 - * Divisor == UHCCDR + 1
1.31 * Desired frequency == 48MHz
1.32 */
1.33
1.34 +#ifdef CONFIG_CPU_JZ4730
1.35 + cfcr |= ((CFG_CPU_SPEED / 48000000 - 1) << 25);
1.36 +#else
1.37 + /* Determine the divider clock output based on the PCS bit. */
1.38 + pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
1.39 +
1.40 + /* Divisor == UHCCDR + 1 */
1.41 REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
1.42 +#endif
1.43
1.44 nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
1.45 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
1.46 @@ -172,10 +175,23 @@
1.47 EMC_SDMR_BL_4 |
1.48 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
1.49
1.50 + /* jz4730 additional measures */
1.51 +#ifdef CONFIG_CPU_JZ4730
1.52 + if (FW_SDRAM_BW16)
1.53 + sdmode <<= 1;
1.54 + else
1.55 + sdmode <<= 2;
1.56 +#endif
1.57 +
1.58 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
1.59 REG_EMC_DMCR = dmcr;
1.60 REG8(EMC_SDMR0|sdmode) = 0;
1.61
1.62 + /* jz4730 additional measures */
1.63 +#ifdef CONFIG_CPU_JZ4730
1.64 + REG8(EMC_SDMR1|sdmode) = 0;
1.65 +#endif
1.66 +
1.67 /* Wait for precharge, > 200us */
1.68 tmp = (cpu_clk / 1000000) * 1000;
1.69 while (tmp--);
1.70 @@ -198,6 +214,11 @@
1.71 REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
1.72 REG8(EMC_SDMR0|sdmode) = 0;
1.73
1.74 + /* jz4730 additional measures */
1.75 +#ifdef CONFIG_CPU_JZ4730
1.76 + REG8(EMC_SDMR1|sdmode) = 0;
1.77 +#endif
1.78 +
1.79 /* Set back to basic DMCR value */
1.80 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
1.81