1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/stage2/jzlcd.h Tue Jun 09 21:10:40 2015 +0200
1.3 @@ -0,0 +1,103 @@
1.4 +/*
1.5 + * JzRISC lcd controller
1.6 + *
1.7 + * Copyright (C) 2005-2007, Ingenic Semiconductor Inc.
1.8 + *
1.9 + * This program is free software; you can redistribute it and/or
1.10 + * modify it under the terms of the GNU General Public License as
1.11 + * published by the Free Software Foundation; either version 2 of
1.12 + * the License, or (at your option) any later version.
1.13 + *
1.14 + * This program is distributed in the hope that it will be useful,
1.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.17 + * GNU General Public License for more details.
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License
1.20 + * along with this program; if not, write to the Free Software
1.21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1.22 + * MA 02111-1307 USA
1.23 + */
1.24 +
1.25 +#ifndef __JZLCD_H__
1.26 +#define __JZLCD_H__
1.27 +
1.28 +unsigned long lcd_get_size(void);
1.29 +void lcd_ctrl_init(void *lcdbase);
1.30 +void lcd_enable(void);
1.31 +void lcd_disable(void);
1.32 +
1.33 +struct lcd_desc{
1.34 + unsigned int next_desc; /* LCDDAx */
1.35 + unsigned int databuf; /* LCDSAx */
1.36 + unsigned int frame_id; /* LCDFIDx */
1.37 + unsigned int cmd; /* LCDCMDx */
1.38 +};
1.39 +
1.40 +struct jzfb_info {
1.41 + unsigned int cfg; /* panel mode and pin usage etc. */
1.42 + unsigned int w;
1.43 + unsigned int h;
1.44 + unsigned int bpp; /* bit per pixel */
1.45 + unsigned int fclk; /* frame clk */
1.46 + unsigned int hsw; /* hsync width, in pclk */
1.47 + unsigned int vsw; /* vsync width, in line count */
1.48 + unsigned int elw; /* end of line, in pclk */
1.49 + unsigned int blw; /* begin of line, in pclk */
1.50 + unsigned int efw; /* end of frame, in line count */
1.51 + unsigned int bfw; /* begin of frame, in line count */
1.52 +};
1.53 +
1.54 +#define MODE_MASK 0x0f
1.55 +#define MODE_TFT_GEN 0x00
1.56 +#define MODE_TFT_SHARP 0x01
1.57 +#define MODE_TFT_CASIO 0x02
1.58 +#define MODE_TFT_SAMSUNG 0x03
1.59 +#define MODE_CCIR656_NONINT 0x04
1.60 +#define MODE_CCIR656_INT 0x05
1.61 +#define MODE_STN_COLOR_SINGLE 0x08
1.62 +#define MODE_STN_MONO_SINGLE 0x09
1.63 +#define MODE_STN_COLOR_DUAL 0x0a
1.64 +#define MODE_STN_MONO_DUAL 0x0b
1.65 +#define MODE_8BIT_SERIAL_TFT 0x0c
1.66 +
1.67 +#define MODE_TFT_18BIT (1<<7)
1.68 +
1.69 +#define STN_DAT_PIN1 (0x00 << 4)
1.70 +#define STN_DAT_PIN2 (0x01 << 4)
1.71 +#define STN_DAT_PIN4 (0x02 << 4)
1.72 +#define STN_DAT_PIN8 (0x03 << 4)
1.73 +#define STN_DAT_PINMASK STN_DAT_PIN8
1.74 +
1.75 +#define STFT_PSHI (1 << 15)
1.76 +#define STFT_CLSHI (1 << 14)
1.77 +#define STFT_SPLHI (1 << 13)
1.78 +#define STFT_REVHI (1 << 12)
1.79 +
1.80 +#define SYNC_MASTER (0 << 16)
1.81 +#define SYNC_SLAVE (1 << 16)
1.82 +
1.83 +#define DE_P (0 << 9)
1.84 +#define DE_N (1 << 9)
1.85 +
1.86 +#define PCLK_P (0 << 10)
1.87 +#define PCLK_N (1 << 10)
1.88 +
1.89 +#define HSYNC_P (0 << 11)
1.90 +#define HSYNC_N (1 << 11)
1.91 +
1.92 +#define VSYNC_P (0 << 8)
1.93 +#define VSYNC_N (1 << 8)
1.94 +
1.95 +#define DATA_NORMAL (0 << 17)
1.96 +#define DATA_INVERSE (1 << 17)
1.97 +
1.98 +
1.99 +/* Jz LCDFB supported I/O controls. */
1.100 +#define FBIOSETBACKLIGHT 0x4688
1.101 +#define FBIODISPON 0x4689
1.102 +#define FBIODISPOFF 0x468a
1.103 +#define FBIORESET 0x468b
1.104 +#define FBIOPRINT_REG 0x468c
1.105 +
1.106 +#endif /* __JZLCD_H__ */