1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/include/jz4740.h Fri May 22 18:37:44 2015 +0200
1.3 @@ -0,0 +1,4837 @@
1.4 +/*
1.5 + * Include file for Ingenic Semiconductor's JZ4740 CPU.
1.6 + *
1.7 + * Copyright 2009 (C) Qi Hardware Inc.,
1.8 + * Author: Xiangfu Liu <xiangfu@sharism.cc>
1.9 + *
1.10 + * This program is free software; you can redistribute it and/or
1.11 + * modify it under the terms of the GNU General Public License
1.12 + * version 3 as published by the Free Software Foundation.
1.13 + *
1.14 + * This program is distributed in the hope that it will be useful,
1.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.17 + * GNU General Public License for more details.
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License
1.20 + * along with this program; if not, write to the Free Software
1.21 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
1.22 + * Boston, MA 02110-1301, USA
1.23 + */
1.24 +#ifndef __JZ4740_H__
1.25 +#define __JZ4740_H__
1.26 +
1.27 +#include "xburst_types.h"
1.28 +
1.29 +#if 0
1.30 +static inline void jz_flush_dcache(void)
1.31 +{
1.32 + unsigned long start;
1.33 + unsigned long end;
1.34 +
1.35 + start = KSEG0;
1.36 + end = start + CFG_DCACHE_SIZE;
1.37 + while (start < end) {
1.38 + cache_unroll(start,Index_Writeback_Inv_D);
1.39 + start += CFG_CACHELINE_SIZE;
1.40 + }
1.41 +}
1.42 +
1.43 +static inline void jz_flush_icache(void)
1.44 +{
1.45 + unsigned long start;
1.46 + unsigned long end;
1.47 +
1.48 + start = KSEG0;
1.49 + end = start + CFG_ICACHE_SIZE;
1.50 + while(start < end) {
1.51 + cache_unroll(start,Index_Invalidate_I);
1.52 + start += CFG_CACHELINE_SIZE;
1.53 + }
1.54 +}
1.55 +
1.56 +#endif
1.57 +#define cache_unroll(base,op) \
1.58 + __asm__ __volatile__(" \
1.59 + .set noreorder; \
1.60 + .set mips3; \
1.61 + cache %1, (%0); \
1.62 + .set mips0; \
1.63 + .set reorder" \
1.64 + : \
1.65 + : "r" (base), \
1.66 + "i" (op));
1.67 +/* cpu pipeline flush */
1.68 +static inline void jz_sync(void)
1.69 +{
1.70 + __asm__ volatile ("sync");
1.71 +}
1.72 +
1.73 +static inline void jz_writeb(u32 address, u8 value)
1.74 +{
1.75 + *((volatile u8 *)address) = value;
1.76 +}
1.77 +
1.78 +static inline void jz_writew(u32 address, u16 value)
1.79 +{
1.80 + *((volatile u16 *)address) = value;
1.81 +}
1.82 +
1.83 +static inline void jz_writel(u32 address, u32 value)
1.84 +{
1.85 + *((volatile u32 *)address) = value;
1.86 +}
1.87 +
1.88 +static inline u8 jz_readb(u32 address)
1.89 +{
1.90 + return *((volatile u8 *)address);
1.91 +}
1.92 +
1.93 +static inline u16 jz_readw(u32 address)
1.94 +{
1.95 + return *((volatile u16 *)address);
1.96 +}
1.97 +
1.98 +static inline u32 jz_readl(u32 address)
1.99 +{
1.100 + return *((volatile u32 *)address);
1.101 +}
1.102 +
1.103 +/* Boot ROM Specification */
1.104 +
1.105 +/* NOR Boot config */
1.106 +#define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
1.107 +#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
1.108 +#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
1.109 +
1.110 +/* NAND Boot config */
1.111 +#define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
1.112 +#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
1.113 +#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
1.114 +#define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
1.115 +
1.116 +
1.117 +/* Register Definitions */
1.118 +#define CPM_BASE 0xB0000000
1.119 +#define INTC_BASE 0xB0001000
1.120 +#define TCU_BASE 0xB0002000
1.121 +#define WDT_BASE 0xB0002000
1.122 +#define RTC_BASE 0xB0003000
1.123 +#define GPIO_BASE 0xB0010000
1.124 +#define AIC_BASE 0xB0020000
1.125 +#define ICDC_BASE 0xB0020000
1.126 +#define MSC_BASE 0xB0021000
1.127 +#define UART0_BASE 0xB0030000
1.128 +#define I2C_BASE 0xB0042000
1.129 +#define SSI_BASE 0xB0043000
1.130 +#define SADC_BASE 0xB0070000
1.131 +#define EMC_BASE 0xB3010000
1.132 +#define DMAC_BASE 0xB3020000
1.133 +#define UHC_BASE 0xB3030000
1.134 +#define UDC_BASE 0xB3040000
1.135 +#define LCD_BASE 0xB3050000
1.136 +#define SLCD_BASE 0xB3050000
1.137 +#define CIM_BASE 0xB3060000
1.138 +#define ETH_BASE 0xB3100000
1.139 +
1.140 +
1.141 +/*************************************************************************
1.142 + * INTC (Interrupt Controller)
1.143 + *************************************************************************/
1.144 +#define INTC_ISR (INTC_BASE + 0x00)
1.145 +#define INTC_IMR (INTC_BASE + 0x04)
1.146 +#define INTC_IMSR (INTC_BASE + 0x08)
1.147 +#define INTC_IMCR (INTC_BASE + 0x0c)
1.148 +#define INTC_IPR (INTC_BASE + 0x10)
1.149 +
1.150 +#define REG_INTC_ISR REG32(INTC_ISR)
1.151 +#define REG_INTC_IMR REG32(INTC_IMR)
1.152 +#define REG_INTC_IMSR REG32(INTC_IMSR)
1.153 +#define REG_INTC_IMCR REG32(INTC_IMCR)
1.154 +#define REG_INTC_IPR REG32(INTC_IPR)
1.155 +
1.156 +/* 1st-level interrupts */
1.157 +#define IRQ_I2C 1
1.158 +#define IRQ_UHC 3
1.159 +#define IRQ_UART0 9
1.160 +#define IRQ_SADC 12
1.161 +#define IRQ_MSC 14
1.162 +#define IRQ_RTC 15
1.163 +#define IRQ_SSI 16
1.164 +#define IRQ_CIM 17
1.165 +#define IRQ_AIC 18
1.166 +#define IRQ_ETH 19
1.167 +#define IRQ_DMAC 20
1.168 +#define IRQ_TCU2 21
1.169 +#define IRQ_TCU1 22
1.170 +#define IRQ_TCU0 23
1.171 +#define IRQ_UDC 24
1.172 +#define IRQ_GPIO3 25
1.173 +#define IRQ_GPIO2 26
1.174 +#define IRQ_GPIO1 27
1.175 +#define IRQ_GPIO0 28
1.176 +#define IRQ_IPU 29
1.177 +#define IRQ_LCD 30
1.178 +
1.179 +/* 2nd-level interrupts */
1.180 +#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
1.181 +#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
1.182 +
1.183 +
1.184 +/*************************************************************************
1.185 + * RTC
1.186 + *************************************************************************/
1.187 +#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
1.188 +#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
1.189 +#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
1.190 +#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
1.191 +
1.192 +#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
1.193 +#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
1.194 +#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
1.195 +#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
1.196 +#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
1.197 +#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
1.198 +
1.199 +#define REG_RTC_RCR REG32(RTC_RCR)
1.200 +#define REG_RTC_RSR REG32(RTC_RSR)
1.201 +#define REG_RTC_RSAR REG32(RTC_RSAR)
1.202 +#define REG_RTC_RGR REG32(RTC_RGR)
1.203 +#define REG_RTC_HCR REG32(RTC_HCR)
1.204 +#define REG_RTC_HWFCR REG32(RTC_HWFCR)
1.205 +#define REG_RTC_HRCR REG32(RTC_HRCR)
1.206 +#define REG_RTC_HWCR REG32(RTC_HWCR)
1.207 +#define REG_RTC_HWRSR REG32(RTC_HWRSR)
1.208 +#define REG_RTC_HSPR REG32(RTC_HSPR)
1.209 +
1.210 +/* RTC Control Register */
1.211 +#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
1.212 +#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */
1.213 +#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */
1.214 +#define RTC_RCR_AF (1 << 4) /* Alarm Flag */
1.215 +#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
1.216 +#define RTC_RCR_AE (1 << 2) /* Alarm Enable */
1.217 +#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
1.218 +
1.219 +/* RTC Regulator Register */
1.220 +#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
1.221 +#define RTC_RGR_ADJC_BIT 16
1.222 +#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
1.223 +#define RTC_RGR_NC1HZ_BIT 0
1.224 +#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
1.225 +
1.226 +/* Hibernate Control Register */
1.227 +#define RTC_HCR_PD (1 << 0) /* Power Down */
1.228 +
1.229 +/* Hibernate Wakeup Filter Counter Register */
1.230 +#define RTC_HWFCR_BIT 5
1.231 +#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
1.232 +
1.233 +/* Hibernate Reset Counter Register */
1.234 +#define RTC_HRCR_BIT 5
1.235 +#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
1.236 +
1.237 +/* Hibernate Wakeup Control Register */
1.238 +#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
1.239 +
1.240 +/* Hibernate Wakeup Status Register */
1.241 +#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
1.242 +#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
1.243 +#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
1.244 +#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
1.245 +
1.246 +
1.247 +/*************************************************************************
1.248 + * CPM (Clock reset and Power control Management)
1.249 + *************************************************************************/
1.250 +#define CPM_CPCCR (CPM_BASE+0x00)
1.251 +#define CPM_CPPCR (CPM_BASE+0x10)
1.252 +#define CPM_I2SCDR (CPM_BASE+0x60)
1.253 +#define CPM_LPCDR (CPM_BASE+0x64)
1.254 +#define CPM_MSCCDR (CPM_BASE+0x68)
1.255 +#define CPM_UHCCDR (CPM_BASE+0x6C)
1.256 +
1.257 +#define CPM_LCR (CPM_BASE+0x04)
1.258 +#define CPM_CLKGR (CPM_BASE+0x20)
1.259 +#define CPM_SCR (CPM_BASE+0x24)
1.260 +
1.261 +#define CPM_HCR (CPM_BASE+0x30)
1.262 +#define CPM_HWFCR (CPM_BASE+0x34)
1.263 +#define CPM_HRCR (CPM_BASE+0x38)
1.264 +#define CPM_HWCR (CPM_BASE+0x3c)
1.265 +#define CPM_HWSR (CPM_BASE+0x40)
1.266 +#define CPM_HSPR (CPM_BASE+0x44)
1.267 +
1.268 +#define CPM_RSR (CPM_BASE+0x08)
1.269 +
1.270 +
1.271 +#define REG_CPM_CPCCR REG32(CPM_CPCCR)
1.272 +#define REG_CPM_CPPCR REG32(CPM_CPPCR)
1.273 +#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
1.274 +#define REG_CPM_LPCDR REG32(CPM_LPCDR)
1.275 +#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
1.276 +#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
1.277 +
1.278 +#define REG_CPM_LCR REG32(CPM_LCR)
1.279 +#define REG_CPM_CLKGR REG32(CPM_CLKGR)
1.280 +#define REG_CPM_SCR REG32(CPM_SCR)
1.281 +#define REG_CPM_HCR REG32(CPM_HCR)
1.282 +#define REG_CPM_HWFCR REG32(CPM_HWFCR)
1.283 +#define REG_CPM_HRCR REG32(CPM_HRCR)
1.284 +#define REG_CPM_HWCR REG32(CPM_HWCR)
1.285 +#define REG_CPM_HWSR REG32(CPM_HWSR)
1.286 +#define REG_CPM_HSPR REG32(CPM_HSPR)
1.287 +
1.288 +#define REG_CPM_RSR REG32(CPM_RSR)
1.289 +
1.290 +
1.291 +/* Clock Control Register */
1.292 +#define CPM_CPCCR_I2CS (1 << 31)
1.293 +#define CPM_CPCCR_CLKOEN (1 << 30)
1.294 +#define CPM_CPCCR_UCS (1 << 29)
1.295 +#define CPM_CPCCR_UDIV_BIT 23
1.296 +#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
1.297 +#define CPM_CPCCR_CE (1 << 22)
1.298 +#define CPM_CPCCR_PCS (1 << 21)
1.299 +#define CPM_CPCCR_LDIV_BIT 16
1.300 +#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
1.301 +#define CPM_CPCCR_MDIV_BIT 12
1.302 +#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
1.303 +#define CPM_CPCCR_PDIV_BIT 8
1.304 +#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
1.305 +#define CPM_CPCCR_HDIV_BIT 4
1.306 +#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
1.307 +#define CPM_CPCCR_CDIV_BIT 0
1.308 +#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
1.309 +
1.310 +/* I2S Clock Divider Register */
1.311 +#define CPM_I2SCDR_I2SDIV_BIT 0
1.312 +#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
1.313 +
1.314 +/* LCD Pixel Clock Divider Register */
1.315 +#define CPM_LPCDR_PIXDIV_BIT 0
1.316 +#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT)
1.317 +
1.318 +/* MSC Clock Divider Register */
1.319 +#define CPM_MSCCDR_MSCDIV_BIT 0
1.320 +#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
1.321 +
1.322 +/* PLL Control Register */
1.323 +#define CPM_CPPCR_PLLM_BIT 23
1.324 +#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
1.325 +#define CPM_CPPCR_PLLN_BIT 18
1.326 +#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
1.327 +#define CPM_CPPCR_PLLOD_BIT 16
1.328 +#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
1.329 +#define CPM_CPPCR_PLLS (1 << 10)
1.330 +#define CPM_CPPCR_PLLBP (1 << 9)
1.331 +#define CPM_CPPCR_PLLEN (1 << 8)
1.332 +#define CPM_CPPCR_PLLST_BIT 0
1.333 +#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
1.334 +
1.335 +/* Low Power Control Register */
1.336 +#define CPM_LCR_DOZE_DUTY_BIT 3
1.337 +#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
1.338 +#define CPM_LCR_DOZE_ON (1 << 2)
1.339 +#define CPM_LCR_LPM_BIT 0
1.340 +#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
1.341 + #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
1.342 + #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
1.343 +
1.344 +/* Clock Gate Register */
1.345 +#define CPM_CLKGR_UART1 (1 << 15)
1.346 +#define CPM_CLKGR_UHC (1 << 14)
1.347 +#define CPM_CLKGR_IPU (1 << 13)
1.348 +#define CPM_CLKGR_DMAC (1 << 12)
1.349 +#define CPM_CLKGR_UDC (1 << 11)
1.350 +#define CPM_CLKGR_LCD (1 << 10)
1.351 +#define CPM_CLKGR_CIM (1 << 9)
1.352 +#define CPM_CLKGR_SADC (1 << 8)
1.353 +#define CPM_CLKGR_MSC (1 << 7)
1.354 +#define CPM_CLKGR_AIC1 (1 << 6)
1.355 +#define CPM_CLKGR_AIC2 (1 << 5)
1.356 +#define CPM_CLKGR_SSI (1 << 4)
1.357 +#define CPM_CLKGR_I2C (1 << 3)
1.358 +#define CPM_CLKGR_RTC (1 << 2)
1.359 +#define CPM_CLKGR_TCU (1 << 1)
1.360 +#define CPM_CLKGR_UART0 (1 << 0)
1.361 +
1.362 +/* Sleep Control Register */
1.363 +#define CPM_SCR_O1ST_BIT 8
1.364 +#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
1.365 +#define CPM_SCR_USBPHY_ENABLE (1 << 6)
1.366 +#define CPM_SCR_OSC_ENABLE (1 << 4)
1.367 +
1.368 +/* Hibernate Control Register */
1.369 +#define CPM_HCR_PD (1 << 0)
1.370 +
1.371 +/* Wakeup Filter Counter Register in Hibernate Mode */
1.372 +#define CPM_HWFCR_TIME_BIT 0
1.373 +#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
1.374 +
1.375 +/* Reset Counter Register in Hibernate Mode */
1.376 +#define CPM_HRCR_TIME_BIT 0
1.377 +#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
1.378 +
1.379 +/* Wakeup Control Register in Hibernate Mode */
1.380 +#define CPM_HWCR_WLE_LOW (0 << 2)
1.381 +#define CPM_HWCR_WLE_HIGH (1 << 2)
1.382 +#define CPM_HWCR_PIN_WAKEUP (1 << 1)
1.383 +#define CPM_HWCR_RTC_WAKEUP (1 << 0)
1.384 +
1.385 +/* Wakeup Status Register in Hibernate Mode */
1.386 +#define CPM_HWSR_WSR_PIN (1 << 1)
1.387 +#define CPM_HWSR_WSR_RTC (1 << 0)
1.388 +
1.389 +/* Reset Status Register */
1.390 +#define CPM_RSR_HR (1 << 2)
1.391 +#define CPM_RSR_WR (1 << 1)
1.392 +#define CPM_RSR_PR (1 << 0)
1.393 +
1.394 +
1.395 +/*************************************************************************
1.396 + * TCU (Timer Counter Unit)
1.397 + *************************************************************************/
1.398 +#define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */
1.399 +#define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */
1.400 +#define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */
1.401 +#define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */
1.402 +#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
1.403 +#define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */
1.404 +#define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */
1.405 +#define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */
1.406 +#define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */
1.407 +#define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */
1.408 +#define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */
1.409 +#define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */
1.410 +#define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */
1.411 +#define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */
1.412 +#define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */
1.413 +#define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */
1.414 +#define TCU_TDFR1 (TCU_BASE + 0x50)
1.415 +#define TCU_TDHR1 (TCU_BASE + 0x54)
1.416 +#define TCU_TCNT1 (TCU_BASE + 0x58)
1.417 +#define TCU_TCSR1 (TCU_BASE + 0x5C)
1.418 +#define TCU_TDFR2 (TCU_BASE + 0x60)
1.419 +#define TCU_TDHR2 (TCU_BASE + 0x64)
1.420 +#define TCU_TCNT2 (TCU_BASE + 0x68)
1.421 +#define TCU_TCSR2 (TCU_BASE + 0x6C)
1.422 +#define TCU_TDFR3 (TCU_BASE + 0x70)
1.423 +#define TCU_TDHR3 (TCU_BASE + 0x74)
1.424 +#define TCU_TCNT3 (TCU_BASE + 0x78)
1.425 +#define TCU_TCSR3 (TCU_BASE + 0x7C)
1.426 +#define TCU_TDFR4 (TCU_BASE + 0x80)
1.427 +#define TCU_TDHR4 (TCU_BASE + 0x84)
1.428 +#define TCU_TCNT4 (TCU_BASE + 0x88)
1.429 +#define TCU_TCSR4 (TCU_BASE + 0x8C)
1.430 +#define TCU_TDFR5 (TCU_BASE + 0x90)
1.431 +#define TCU_TDHR5 (TCU_BASE + 0x94)
1.432 +#define TCU_TCNT5 (TCU_BASE + 0x98)
1.433 +#define TCU_TCSR5 (TCU_BASE + 0x9C)
1.434 +
1.435 +#define REG_TCU_TSR REG32(TCU_TSR)
1.436 +#define REG_TCU_TSSR REG32(TCU_TSSR)
1.437 +#define REG_TCU_TSCR REG32(TCU_TSCR)
1.438 +#define REG_TCU_TER REG8(TCU_TER)
1.439 +#define REG_TCU_TESR REG8(TCU_TESR)
1.440 +#define REG_TCU_TECR REG8(TCU_TECR)
1.441 +#define REG_TCU_TFR REG32(TCU_TFR)
1.442 +#define REG_TCU_TFSR REG32(TCU_TFSR)
1.443 +#define REG_TCU_TFCR REG32(TCU_TFCR)
1.444 +#define REG_TCU_TMR REG32(TCU_TMR)
1.445 +#define REG_TCU_TMSR REG32(TCU_TMSR)
1.446 +#define REG_TCU_TMCR REG32(TCU_TMCR)
1.447 +#define REG_TCU_TDFR0 REG16(TCU_TDFR0)
1.448 +#define REG_TCU_TDHR0 REG16(TCU_TDHR0)
1.449 +#define REG_TCU_TCNT0 REG16(TCU_TCNT0)
1.450 +#define REG_TCU_TCSR0 REG16(TCU_TCSR0)
1.451 +#define REG_TCU_TDFR1 REG16(TCU_TDFR1)
1.452 +#define REG_TCU_TDHR1 REG16(TCU_TDHR1)
1.453 +#define REG_TCU_TCNT1 REG16(TCU_TCNT1)
1.454 +#define REG_TCU_TCSR1 REG16(TCU_TCSR1)
1.455 +#define REG_TCU_TDFR2 REG16(TCU_TDFR2)
1.456 +#define REG_TCU_TDHR2 REG16(TCU_TDHR2)
1.457 +#define REG_TCU_TCNT2 REG16(TCU_TCNT2)
1.458 +#define REG_TCU_TCSR2 REG16(TCU_TCSR2)
1.459 +#define REG_TCU_TDFR3 REG16(TCU_TDFR3)
1.460 +#define REG_TCU_TDHR3 REG16(TCU_TDHR3)
1.461 +#define REG_TCU_TCNT3 REG16(TCU_TCNT3)
1.462 +#define REG_TCU_TCSR3 REG16(TCU_TCSR3)
1.463 +#define REG_TCU_TDFR4 REG16(TCU_TDFR4)
1.464 +#define REG_TCU_TDHR4 REG16(TCU_TDHR4)
1.465 +#define REG_TCU_TCNT4 REG16(TCU_TCNT4)
1.466 +#define REG_TCU_TCSR4 REG16(TCU_TCSR4)
1.467 +
1.468 +/* n = 0,1,2,3,4,5 */
1.469 +#define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
1.470 +#define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
1.471 +#define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
1.472 +#define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */
1.473 +
1.474 +#define REG_TCU_TDFR(n) REG16(TCU_TDFR((n)))
1.475 +#define REG_TCU_TDHR(n) REG16(TCU_TDHR((n)))
1.476 +#define REG_TCU_TCNT(n) REG16(TCU_TCNT((n)))
1.477 +#define REG_TCU_TCSR(n) REG16(TCU_TCSR((n)))
1.478 +
1.479 +/* Register definitions */
1.480 +#define TCU_TCSR_PWM_SD (1 << 9)
1.481 +#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
1.482 +#define TCU_TCSR_PWM_EN (1 << 7)
1.483 +#define TCU_TCSR_PRESCALE_BIT 3
1.484 +#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
1.485 + #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
1.486 + #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
1.487 + #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
1.488 + #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
1.489 + #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
1.490 + #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
1.491 +#define TCU_TCSR_EXT_EN (1 << 2)
1.492 +#define TCU_TCSR_RTC_EN (1 << 1)
1.493 +#define TCU_TCSR_PCK_EN (1 << 0)
1.494 +
1.495 +#define TCU_TER_TCEN5 (1 << 5)
1.496 +#define TCU_TER_TCEN4 (1 << 4)
1.497 +#define TCU_TER_TCEN3 (1 << 3)
1.498 +#define TCU_TER_TCEN2 (1 << 2)
1.499 +#define TCU_TER_TCEN1 (1 << 1)
1.500 +#define TCU_TER_TCEN0 (1 << 0)
1.501 +
1.502 +#define TCU_TESR_TCST5 (1 << 5)
1.503 +#define TCU_TESR_TCST4 (1 << 4)
1.504 +#define TCU_TESR_TCST3 (1 << 3)
1.505 +#define TCU_TESR_TCST2 (1 << 2)
1.506 +#define TCU_TESR_TCST1 (1 << 1)
1.507 +#define TCU_TESR_TCST0 (1 << 0)
1.508 +
1.509 +#define TCU_TECR_TCCL5 (1 << 5)
1.510 +#define TCU_TECR_TCCL4 (1 << 4)
1.511 +#define TCU_TECR_TCCL3 (1 << 3)
1.512 +#define TCU_TECR_TCCL2 (1 << 2)
1.513 +#define TCU_TECR_TCCL1 (1 << 1)
1.514 +#define TCU_TECR_TCCL0 (1 << 0)
1.515 +
1.516 +#define TCU_TFR_HFLAG5 (1 << 21)
1.517 +#define TCU_TFR_HFLAG4 (1 << 20)
1.518 +#define TCU_TFR_HFLAG3 (1 << 19)
1.519 +#define TCU_TFR_HFLAG2 (1 << 18)
1.520 +#define TCU_TFR_HFLAG1 (1 << 17)
1.521 +#define TCU_TFR_HFLAG0 (1 << 16)
1.522 +#define TCU_TFR_FFLAG5 (1 << 5)
1.523 +#define TCU_TFR_FFLAG4 (1 << 4)
1.524 +#define TCU_TFR_FFLAG3 (1 << 3)
1.525 +#define TCU_TFR_FFLAG2 (1 << 2)
1.526 +#define TCU_TFR_FFLAG1 (1 << 1)
1.527 +#define TCU_TFR_FFLAG0 (1 << 0)
1.528 +
1.529 +#define TCU_TFSR_HFLAG5 (1 << 21)
1.530 +#define TCU_TFSR_HFLAG4 (1 << 20)
1.531 +#define TCU_TFSR_HFLAG3 (1 << 19)
1.532 +#define TCU_TFSR_HFLAG2 (1 << 18)
1.533 +#define TCU_TFSR_HFLAG1 (1 << 17)
1.534 +#define TCU_TFSR_HFLAG0 (1 << 16)
1.535 +#define TCU_TFSR_FFLAG5 (1 << 5)
1.536 +#define TCU_TFSR_FFLAG4 (1 << 4)
1.537 +#define TCU_TFSR_FFLAG3 (1 << 3)
1.538 +#define TCU_TFSR_FFLAG2 (1 << 2)
1.539 +#define TCU_TFSR_FFLAG1 (1 << 1)
1.540 +#define TCU_TFSR_FFLAG0 (1 << 0)
1.541 +
1.542 +#define TCU_TFCR_HFLAG5 (1 << 21)
1.543 +#define TCU_TFCR_HFLAG4 (1 << 20)
1.544 +#define TCU_TFCR_HFLAG3 (1 << 19)
1.545 +#define TCU_TFCR_HFLAG2 (1 << 18)
1.546 +#define TCU_TFCR_HFLAG1 (1 << 17)
1.547 +#define TCU_TFCR_HFLAG0 (1 << 16)
1.548 +#define TCU_TFCR_FFLAG5 (1 << 5)
1.549 +#define TCU_TFCR_FFLAG4 (1 << 4)
1.550 +#define TCU_TFCR_FFLAG3 (1 << 3)
1.551 +#define TCU_TFCR_FFLAG2 (1 << 2)
1.552 +#define TCU_TFCR_FFLAG1 (1 << 1)
1.553 +#define TCU_TFCR_FFLAG0 (1 << 0)
1.554 +
1.555 +#define TCU_TMR_HMASK5 (1 << 21)
1.556 +#define TCU_TMR_HMASK4 (1 << 20)
1.557 +#define TCU_TMR_HMASK3 (1 << 19)
1.558 +#define TCU_TMR_HMASK2 (1 << 18)
1.559 +#define TCU_TMR_HMASK1 (1 << 17)
1.560 +#define TCU_TMR_HMASK0 (1 << 16)
1.561 +#define TCU_TMR_FMASK5 (1 << 5)
1.562 +#define TCU_TMR_FMASK4 (1 << 4)
1.563 +#define TCU_TMR_FMASK3 (1 << 3)
1.564 +#define TCU_TMR_FMASK2 (1 << 2)
1.565 +#define TCU_TMR_FMASK1 (1 << 1)
1.566 +#define TCU_TMR_FMASK0 (1 << 0)
1.567 +
1.568 +#define TCU_TMSR_HMST5 (1 << 21)
1.569 +#define TCU_TMSR_HMST4 (1 << 20)
1.570 +#define TCU_TMSR_HMST3 (1 << 19)
1.571 +#define TCU_TMSR_HMST2 (1 << 18)
1.572 +#define TCU_TMSR_HMST1 (1 << 17)
1.573 +#define TCU_TMSR_HMST0 (1 << 16)
1.574 +#define TCU_TMSR_FMST5 (1 << 5)
1.575 +#define TCU_TMSR_FMST4 (1 << 4)
1.576 +#define TCU_TMSR_FMST3 (1 << 3)
1.577 +#define TCU_TMSR_FMST2 (1 << 2)
1.578 +#define TCU_TMSR_FMST1 (1 << 1)
1.579 +#define TCU_TMSR_FMST0 (1 << 0)
1.580 +
1.581 +#define TCU_TMCR_HMCL5 (1 << 21)
1.582 +#define TCU_TMCR_HMCL4 (1 << 20)
1.583 +#define TCU_TMCR_HMCL3 (1 << 19)
1.584 +#define TCU_TMCR_HMCL2 (1 << 18)
1.585 +#define TCU_TMCR_HMCL1 (1 << 17)
1.586 +#define TCU_TMCR_HMCL0 (1 << 16)
1.587 +#define TCU_TMCR_FMCL5 (1 << 5)
1.588 +#define TCU_TMCR_FMCL4 (1 << 4)
1.589 +#define TCU_TMCR_FMCL3 (1 << 3)
1.590 +#define TCU_TMCR_FMCL2 (1 << 2)
1.591 +#define TCU_TMCR_FMCL1 (1 << 1)
1.592 +#define TCU_TMCR_FMCL0 (1 << 0)
1.593 +
1.594 +#define TCU_TSR_WDTS (1 << 16)
1.595 +#define TCU_TSR_STOP5 (1 << 5)
1.596 +#define TCU_TSR_STOP4 (1 << 4)
1.597 +#define TCU_TSR_STOP3 (1 << 3)
1.598 +#define TCU_TSR_STOP2 (1 << 2)
1.599 +#define TCU_TSR_STOP1 (1 << 1)
1.600 +#define TCU_TSR_STOP0 (1 << 0)
1.601 +
1.602 +#define TCU_TSSR_WDTSS (1 << 16)
1.603 +#define TCU_TSSR_STPS5 (1 << 5)
1.604 +#define TCU_TSSR_STPS4 (1 << 4)
1.605 +#define TCU_TSSR_STPS3 (1 << 3)
1.606 +#define TCU_TSSR_STPS2 (1 << 2)
1.607 +#define TCU_TSSR_STPS1 (1 << 1)
1.608 +#define TCU_TSSR_STPS0 (1 << 0)
1.609 +
1.610 +#define TCU_TSSR_WDTSC (1 << 16)
1.611 +#define TCU_TSSR_STPC5 (1 << 5)
1.612 +#define TCU_TSSR_STPC4 (1 << 4)
1.613 +#define TCU_TSSR_STPC3 (1 << 3)
1.614 +#define TCU_TSSR_STPC2 (1 << 2)
1.615 +#define TCU_TSSR_STPC1 (1 << 1)
1.616 +#define TCU_TSSR_STPC0 (1 << 0)
1.617 +
1.618 +
1.619 +/*************************************************************************
1.620 + * WDT (WatchDog Timer)
1.621 + *************************************************************************/
1.622 +#define WDT_TDR (WDT_BASE + 0x00)
1.623 +#define WDT_TCER (WDT_BASE + 0x04)
1.624 +#define WDT_TCNT (WDT_BASE + 0x08)
1.625 +#define WDT_TCSR (WDT_BASE + 0x0C)
1.626 +
1.627 +#define REG_WDT_TDR REG16(WDT_TDR)
1.628 +#define REG_WDT_TCER REG8(WDT_TCER)
1.629 +#define REG_WDT_TCNT REG16(WDT_TCNT)
1.630 +#define REG_WDT_TCSR REG16(WDT_TCSR)
1.631 +
1.632 +/* Register definition */
1.633 +#define WDT_TCSR_PRESCALE_BIT 3
1.634 +#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
1.635 + #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
1.636 + #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
1.637 + #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
1.638 + #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
1.639 + #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
1.640 + #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
1.641 +#define WDT_TCSR_EXT_EN (1 << 2)
1.642 +#define WDT_TCSR_RTC_EN (1 << 1)
1.643 +#define WDT_TCSR_PCK_EN (1 << 0)
1.644 +
1.645 +#define WDT_TCER_TCEN (1 << 0)
1.646 +
1.647 +
1.648 +/*************************************************************************
1.649 + * DMAC (DMA Controller)
1.650 + *************************************************************************/
1.651 +
1.652 +#define MAX_DMA_NUM 6 /* max 6 channels */
1.653 +
1.654 +#define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
1.655 +#define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
1.656 +#define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
1.657 +#define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
1.658 +#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
1.659 +#define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
1.660 +#define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
1.661 +#define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */
1.662 +#define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */
1.663 +#define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */
1.664 +#define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */
1.665 +
1.666 +/* channel 0 */
1.667 +#define DMAC_DSAR0 DMAC_DSAR(0)
1.668 +#define DMAC_DTAR0 DMAC_DTAR(0)
1.669 +#define DMAC_DTCR0 DMAC_DTCR(0)
1.670 +#define DMAC_DRSR0 DMAC_DRSR(0)
1.671 +#define DMAC_DCCSR0 DMAC_DCCSR(0)
1.672 +#define DMAC_DCMD0 DMAC_DCMD(0)
1.673 +#define DMAC_DDA0 DMAC_DDA(0)
1.674 +
1.675 +/* channel 1 */
1.676 +#define DMAC_DSAR1 DMAC_DSAR(1)
1.677 +#define DMAC_DTAR1 DMAC_DTAR(1)
1.678 +#define DMAC_DTCR1 DMAC_DTCR(1)
1.679 +#define DMAC_DRSR1 DMAC_DRSR(1)
1.680 +#define DMAC_DCCSR1 DMAC_DCCSR(1)
1.681 +#define DMAC_DCMD1 DMAC_DCMD(1)
1.682 +#define DMAC_DDA1 DMAC_DDA(1)
1.683 +
1.684 +/* channel 2 */
1.685 +#define DMAC_DSAR2 DMAC_DSAR(2)
1.686 +#define DMAC_DTAR2 DMAC_DTAR(2)
1.687 +#define DMAC_DTCR2 DMAC_DTCR(2)
1.688 +#define DMAC_DRSR2 DMAC_DRSR(2)
1.689 +#define DMAC_DCCSR2 DMAC_DCCSR(2)
1.690 +#define DMAC_DCMD2 DMAC_DCMD(2)
1.691 +#define DMAC_DDA2 DMAC_DDA(2)
1.692 +
1.693 +/* channel 3 */
1.694 +#define DMAC_DSAR3 DMAC_DSAR(3)
1.695 +#define DMAC_DTAR3 DMAC_DTAR(3)
1.696 +#define DMAC_DTCR3 DMAC_DTCR(3)
1.697 +#define DMAC_DRSR3 DMAC_DRSR(3)
1.698 +#define DMAC_DCCSR3 DMAC_DCCSR(3)
1.699 +#define DMAC_DCMD3 DMAC_DCMD(3)
1.700 +#define DMAC_DDA3 DMAC_DDA(3)
1.701 +
1.702 +/* channel 4 */
1.703 +#define DMAC_DSAR4 DMAC_DSAR(4)
1.704 +#define DMAC_DTAR4 DMAC_DTAR(4)
1.705 +#define DMAC_DTCR4 DMAC_DTCR(4)
1.706 +#define DMAC_DRSR4 DMAC_DRSR(4)
1.707 +#define DMAC_DCCSR4 DMAC_DCCSR(4)
1.708 +#define DMAC_DCMD4 DMAC_DCMD(4)
1.709 +#define DMAC_DDA4 DMAC_DDA(4)
1.710 +
1.711 +/* channel 5 */
1.712 +#define DMAC_DSAR5 DMAC_DSAR(5)
1.713 +#define DMAC_DTAR5 DMAC_DTAR(5)
1.714 +#define DMAC_DTCR5 DMAC_DTCR(5)
1.715 +#define DMAC_DRSR5 DMAC_DRSR(5)
1.716 +#define DMAC_DCCSR5 DMAC_DCCSR(5)
1.717 +#define DMAC_DCMD5 DMAC_DCMD(5)
1.718 +#define DMAC_DDA5 DMAC_DDA(5)
1.719 +
1.720 +#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
1.721 +#define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n)))
1.722 +#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
1.723 +#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
1.724 +#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
1.725 +#define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n)))
1.726 +#define REG_DMAC_DDA(n) REG32(DMAC_DDA((n)))
1.727 +#define REG_DMAC_DMACR REG32(DMAC_DMACR)
1.728 +#define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR)
1.729 +#define REG_DMAC_DMADBR REG32(DMAC_DMADBR)
1.730 +#define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR)
1.731 +
1.732 +/* DMA request source register */
1.733 +#define DMAC_DRSR_RS_BIT 0
1.734 +#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
1.735 + #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
1.736 + #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
1.737 + #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
1.738 + #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT)
1.739 + #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT)
1.740 + #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
1.741 + #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
1.742 + #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT)
1.743 + #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT)
1.744 + #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
1.745 + #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
1.746 + #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT)
1.747 +
1.748 +/* DMA channel control/status register */
1.749 +#define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
1.750 +#define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
1.751 +#define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT)
1.752 +#define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */
1.753 +#define DMAC_DCCSR_AR (1 << 4) /* address error */
1.754 +#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
1.755 +#define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */
1.756 +#define DMAC_DCCSR_CT (1 << 1) /* count terminated */
1.757 +#define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */
1.758 +
1.759 +/* DMA channel command register */
1.760 +#define DMAC_DCMD_SAI (1 << 23) /* source address increment */
1.761 +#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
1.762 +#define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */
1.763 +#define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT)
1.764 + #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT)
1.765 + #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT)
1.766 + #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT)
1.767 + #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT)
1.768 + #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT)
1.769 + #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT)
1.770 + #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT)
1.771 + #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT)
1.772 + #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT)
1.773 + #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT)
1.774 + #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT)
1.775 + #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT)
1.776 + #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT)
1.777 + #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT)
1.778 + #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT)
1.779 + #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT)
1.780 +#define DMAC_DCMD_SWDH_BIT 14 /* source port width */
1.781 +#define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
1.782 + #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
1.783 + #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
1.784 + #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
1.785 +#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
1.786 +#define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
1.787 + #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
1.788 + #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
1.789 + #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
1.790 +#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
1.791 +#define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
1.792 + #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
1.793 + #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
1.794 + #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
1.795 + #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
1.796 + #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
1.797 +#define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */
1.798 +#define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */
1.799 +#define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */
1.800 +#define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */
1.801 +#define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
1.802 +#define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
1.803 +
1.804 +/* DMA descriptor address register */
1.805 +#define DMAC_DDA_BASE_BIT 12 /* descriptor base address */
1.806 +#define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT)
1.807 +#define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
1.808 +#define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT)
1.809 +
1.810 +/* DMA control register */
1.811 +#define DMAC_DMACR_PR_BIT 8 /* channel priority mode */
1.812 +#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
1.813 + #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
1.814 + #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT)
1.815 + #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT)
1.816 + #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */
1.817 +#define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
1.818 +#define DMAC_DMACR_AR (1 << 2) /* address error flag */
1.819 +#define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
1.820 +
1.821 +/* DMA doorbell register */
1.822 +#define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */
1.823 +#define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */
1.824 +#define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */
1.825 +#define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */
1.826 +#define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */
1.827 +#define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */
1.828 +
1.829 +/* DMA doorbell set register */
1.830 +#define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */
1.831 +#define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */
1.832 +#define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */
1.833 +#define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */
1.834 +#define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */
1.835 +#define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */
1.836 +
1.837 +/* DMA interrupt pending register */
1.838 +#define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */
1.839 +#define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */
1.840 +#define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */
1.841 +#define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
1.842 +#define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
1.843 +#define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
1.844 +
1.845 +
1.846 +/*************************************************************************
1.847 + * GPIO (General-Purpose I/O Ports)
1.848 + *************************************************************************/
1.849 +#define MAX_GPIO_NUM 128
1.850 +
1.851 +/*n = 0,1,2,3 */
1.852 +#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
1.853 +#define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
1.854 +#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
1.855 +#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
1.856 +#define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
1.857 +#define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
1.858 +#define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
1.859 +#define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
1.860 +#define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
1.861 +#define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
1.862 +#define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
1.863 +#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
1.864 +#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
1.865 +#define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
1.866 +#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
1.867 +#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
1.868 +#define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
1.869 +#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
1.870 +#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
1.871 +#define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
1.872 +#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
1.873 +#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
1.874 +#define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */
1.875 +#define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */
1.876 +
1.877 +#define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */
1.878 +#define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */
1.879 +#define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n)))
1.880 +#define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n)))
1.881 +#define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */
1.882 +#define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n)))
1.883 +#define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n)))
1.884 +#define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */
1.885 +#define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n)))
1.886 +#define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n)))
1.887 +#define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */
1.888 +#define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n)))
1.889 +#define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n)))
1.890 +#define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/
1.891 +#define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n)))
1.892 +#define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n)))
1.893 +#define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
1.894 +#define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n)))
1.895 +#define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n)))
1.896 +#define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */
1.897 +#define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n)))
1.898 +#define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n)))
1.899 +#define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */
1.900 +#define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */
1.901 +
1.902 +
1.903 +/*************************************************************************
1.904 + * UART
1.905 + *************************************************************************/
1.906 +
1.907 +#define IRDA_BASE UART0_BASE
1.908 +/*#define UART_BASE UART0_BASE */
1.909 +#define UART_OFF 0x1000
1.910 +
1.911 +/* Register Offset */
1.912 +#define OFF_RDR (0x00) /* R 8b H'xx */
1.913 +#define OFF_TDR (0x00) /* W 8b H'xx */
1.914 +#define OFF_DLLR (0x00) /* RW 8b H'00 */
1.915 +#define OFF_DLHR (0x04) /* RW 8b H'00 */
1.916 +#define OFF_IER (0x04) /* RW 8b H'00 */
1.917 +#define OFF_ISR (0x08) /* R 8b H'01 */
1.918 +#define OFF_FCR (0x08) /* W 8b H'00 */
1.919 +#define OFF_LCR (0x0C) /* RW 8b H'00 */
1.920 +#define OFF_MCR (0x10) /* RW 8b H'00 */
1.921 +#define OFF_LSR (0x14) /* R 8b H'00 */
1.922 +#define OFF_MSR (0x18) /* R 8b H'00 */
1.923 +#define OFF_SPR (0x1C) /* RW 8b H'00 */
1.924 +#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
1.925 +#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
1.926 +#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
1.927 +
1.928 +/* Register Address */
1.929 +#define UART0_RDR (UART0_BASE + OFF_RDR)
1.930 +#define UART0_TDR (UART0_BASE + OFF_TDR)
1.931 +#define UART0_DLLR (UART0_BASE + OFF_DLLR)
1.932 +#define UART0_DLHR (UART0_BASE + OFF_DLHR)
1.933 +#define UART0_IER (UART0_BASE + OFF_IER)
1.934 +#define UART0_ISR (UART0_BASE + OFF_ISR)
1.935 +#define UART0_FCR (UART0_BASE + OFF_FCR)
1.936 +#define UART0_LCR (UART0_BASE + OFF_LCR)
1.937 +#define UART0_MCR (UART0_BASE + OFF_MCR)
1.938 +#define UART0_LSR (UART0_BASE + OFF_LSR)
1.939 +#define UART0_MSR (UART0_BASE + OFF_MSR)
1.940 +#define UART0_SPR (UART0_BASE + OFF_SPR)
1.941 +#define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
1.942 +#define UART0_UMR (UART0_BASE + OFF_UMR)
1.943 +#define UART0_UACR (UART0_BASE + OFF_UACR)
1.944 +
1.945 +/*
1.946 + * Define macros for UART_IER
1.947 + * UART Interrupt Enable Register
1.948 + */
1.949 +#define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
1.950 +#define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
1.951 +#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
1.952 +#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
1.953 +#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
1.954 +
1.955 +/*
1.956 + * Define macros for UART_ISR
1.957 + * UART Interrupt Status Register
1.958 + */
1.959 +#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
1.960 +#define UART_ISR_IID (7 << 1) /* Source of Interrupt */
1.961 +#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
1.962 +#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
1.963 +#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
1.964 +#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
1.965 +#define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */
1.966 +#define UART_ISR_FFMS_NO_FIFO (0 << 6)
1.967 +#define UART_ISR_FFMS_FIFO_MODE (3 << 6)
1.968 +
1.969 +/*
1.970 + * Define macros for UART_FCR
1.971 + * UART FIFO Control Register
1.972 + */
1.973 +#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
1.974 +#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
1.975 +#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
1.976 +#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
1.977 +#define UART_FCR_UUE (1 << 4) /* 0: disable UART */
1.978 +#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
1.979 +#define UART_FCR_RTRG_1 (0 << 6)
1.980 +#define UART_FCR_RTRG_4 (1 << 6)
1.981 +#define UART_FCR_RTRG_8 (2 << 6)
1.982 +#define UART_FCR_RTRG_15 (3 << 6)
1.983 +
1.984 +/*
1.985 + * Define macros for UART_LCR
1.986 + * UART Line Control Register
1.987 + */
1.988 +#define UART_LCR_WLEN (3 << 0) /* word length */
1.989 +#define UART_LCR_WLEN_5 (0 << 0)
1.990 +#define UART_LCR_WLEN_6 (1 << 0)
1.991 +#define UART_LCR_WLEN_7 (2 << 0)
1.992 +#define UART_LCR_WLEN_8 (3 << 0)
1.993 +#define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1.994 + 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1.995 +#define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1.996 + 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1.997 +#define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1.998 + 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1.999 +
1.1000 +#define UART_LCR_PE (1 << 3) /* 0: parity disable */
1.1001 +#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
1.1002 +#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */
1.1003 +#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
1.1004 +#define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */
1.1005 +
1.1006 +/*
1.1007 + * Define macros for UART_LSR
1.1008 + * UART Line Status Register
1.1009 + */
1.1010 +#define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
1.1011 +#define UART_LSR_ORER (1 << 1) /* 0: no overrun error */
1.1012 +#define UART_LSR_PER (1 << 2) /* 0: no parity error */
1.1013 +#define UART_LSR_FER (1 << 3) /* 0; no framing error */
1.1014 +#define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
1.1015 +#define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
1.1016 +#define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
1.1017 +#define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
1.1018 +
1.1019 +/*
1.1020 + * Define macros for UART_MCR
1.1021 + * UART Modem Control Register
1.1022 + */
1.1023 +#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */
1.1024 +#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */
1.1025 +#define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */
1.1026 +#define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
1.1027 +#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
1.1028 +#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */
1.1029 +
1.1030 +/*
1.1031 + * Define macros for UART_MSR
1.1032 + * UART Modem Status Register
1.1033 + */
1.1034 +#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */
1.1035 +#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */
1.1036 +#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */
1.1037 +#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */
1.1038 +#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */
1.1039 +#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */
1.1040 +#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */
1.1041 +#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */
1.1042 +
1.1043 +/*
1.1044 + * Define macros for SIRCR
1.1045 + * Slow IrDA Control Register
1.1046 + */
1.1047 +#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */
1.1048 +#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */
1.1049 +#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
1.1050 + 1: 0 pulse width is 1.6us for 115.2Kbps */
1.1051 +#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
1.1052 +#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
1.1053 +
1.1054 +
1.1055 +/*************************************************************************
1.1056 + * AIC (AC97/I2S Controller)
1.1057 + *************************************************************************/
1.1058 +#define AIC_FR (AIC_BASE + 0x000)
1.1059 +#define AIC_CR (AIC_BASE + 0x004)
1.1060 +#define AIC_ACCR1 (AIC_BASE + 0x008)
1.1061 +#define AIC_ACCR2 (AIC_BASE + 0x00C)
1.1062 +#define AIC_I2SCR (AIC_BASE + 0x010)
1.1063 +#define AIC_SR (AIC_BASE + 0x014)
1.1064 +#define AIC_ACSR (AIC_BASE + 0x018)
1.1065 +#define AIC_I2SSR (AIC_BASE + 0x01C)
1.1066 +#define AIC_ACCAR (AIC_BASE + 0x020)
1.1067 +#define AIC_ACCDR (AIC_BASE + 0x024)
1.1068 +#define AIC_ACSAR (AIC_BASE + 0x028)
1.1069 +#define AIC_ACSDR (AIC_BASE + 0x02C)
1.1070 +#define AIC_I2SDIV (AIC_BASE + 0x030)
1.1071 +#define AIC_DR (AIC_BASE + 0x034)
1.1072 +
1.1073 +#define REG_AIC_FR REG32(AIC_FR)
1.1074 +#define REG_AIC_CR REG32(AIC_CR)
1.1075 +#define REG_AIC_ACCR1 REG32(AIC_ACCR1)
1.1076 +#define REG_AIC_ACCR2 REG32(AIC_ACCR2)
1.1077 +#define REG_AIC_I2SCR REG32(AIC_I2SCR)
1.1078 +#define REG_AIC_SR REG32(AIC_SR)
1.1079 +#define REG_AIC_ACSR REG32(AIC_ACSR)
1.1080 +#define REG_AIC_I2SSR REG32(AIC_I2SSR)
1.1081 +#define REG_AIC_ACCAR REG32(AIC_ACCAR)
1.1082 +#define REG_AIC_ACCDR REG32(AIC_ACCDR)
1.1083 +#define REG_AIC_ACSAR REG32(AIC_ACSAR)
1.1084 +#define REG_AIC_ACSDR REG32(AIC_ACSDR)
1.1085 +#define REG_AIC_I2SDIV REG32(AIC_I2SDIV)
1.1086 +#define REG_AIC_DR REG32(AIC_DR)
1.1087 +
1.1088 +/* AIC Controller Configuration Register (AIC_FR) */
1.1089 +
1.1090 +#define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */
1.1091 +#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT)
1.1092 +#define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */
1.1093 +#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT)
1.1094 +#define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */
1.1095 +#define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */
1.1096 +#define AIC_FR_RST (1 << 3) /* AIC registers reset */
1.1097 +#define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */
1.1098 +#define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */
1.1099 +#define AIC_FR_ENB (1 << 0) /* AIC enable bit */
1.1100 +
1.1101 +/* AIC Controller Common Control Register (AIC_CR) */
1.1102 +
1.1103 +#define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */
1.1104 +#define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT)
1.1105 + #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT)
1.1106 + #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT)
1.1107 + #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT)
1.1108 + #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT)
1.1109 + #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT)
1.1110 +#define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */
1.1111 +#define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT)
1.1112 + #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT)
1.1113 + #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT)
1.1114 + #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT)
1.1115 + #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT)
1.1116 + #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT)
1.1117 +#define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */
1.1118 +#define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */
1.1119 +#define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */
1.1120 +#define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */
1.1121 +#define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */
1.1122 +#define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */
1.1123 +#define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */
1.1124 +#define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */
1.1125 +#define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */
1.1126 +#define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */
1.1127 +#define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */
1.1128 +#define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */
1.1129 +#define AIC_CR_EREC (1 << 0) /* Enable Record Function */
1.1130 +
1.1131 +/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */
1.1132 +
1.1133 +#define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */
1.1134 +#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT)
1.1135 + #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */
1.1136 + #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */
1.1137 + #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */
1.1138 + #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */
1.1139 + #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */
1.1140 + #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */
1.1141 + #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */
1.1142 + #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */
1.1143 + #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */
1.1144 + #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */
1.1145 +#define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */
1.1146 +#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT)
1.1147 + #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */
1.1148 + #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */
1.1149 + #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */
1.1150 + #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */
1.1151 + #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */
1.1152 + #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */
1.1153 + #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */
1.1154 + #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */
1.1155 + #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */
1.1156 + #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */
1.1157 +
1.1158 +/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */
1.1159 +
1.1160 +#define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */
1.1161 +#define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */
1.1162 +#define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */
1.1163 +#define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */
1.1164 +#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT)
1.1165 + #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */
1.1166 + #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */
1.1167 + #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */
1.1168 + #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */
1.1169 +#define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */
1.1170 +#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT)
1.1171 + #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */
1.1172 + #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */
1.1173 + #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */
1.1174 + #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */
1.1175 +#define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */
1.1176 +#define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */
1.1177 +#define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */
1.1178 +#define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */
1.1179 +
1.1180 +/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */
1.1181 +
1.1182 +#define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */
1.1183 +#define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */
1.1184 +#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT)
1.1185 + #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */
1.1186 + #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */
1.1187 + #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */
1.1188 + #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */
1.1189 + #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */
1.1190 +#define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */
1.1191 +
1.1192 +/* AIC Controller FIFO Status Register (AIC_SR) */
1.1193 +
1.1194 +#define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */
1.1195 +#define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT)
1.1196 +#define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */
1.1197 +#define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT)
1.1198 +#define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */
1.1199 +#define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */
1.1200 +#define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */
1.1201 +#define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */
1.1202 +
1.1203 +/* AIC Controller AC-link Status Register (AIC_ACSR) */
1.1204 +
1.1205 +#define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */
1.1206 +#define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */
1.1207 +#define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */
1.1208 +#define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */
1.1209 +#define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */
1.1210 +#define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */
1.1211 +
1.1212 +/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */
1.1213 +
1.1214 +#define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */
1.1215 +
1.1216 +/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */
1.1217 +
1.1218 +#define AIC_ACCAR_CAR_BIT 0
1.1219 +#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT)
1.1220 +
1.1221 +/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */
1.1222 +
1.1223 +#define AIC_ACCDR_CDR_BIT 0
1.1224 +#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT)
1.1225 +
1.1226 +/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */
1.1227 +
1.1228 +#define AIC_ACSAR_SAR_BIT 0
1.1229 +#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT)
1.1230 +
1.1231 +/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */
1.1232 +
1.1233 +#define AIC_ACSDR_SDR_BIT 0
1.1234 +#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT)
1.1235 +
1.1236 +/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */
1.1237 +
1.1238 +#define AIC_I2SDIV_DIV_BIT 0
1.1239 +#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT)
1.1240 + #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */
1.1241 + #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */
1.1242 + #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */
1.1243 + #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */
1.1244 + #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */
1.1245 + #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */
1.1246 +
1.1247 +
1.1248 +/*************************************************************************
1.1249 + * ICDC (Internal CODEC)
1.1250 + *************************************************************************/
1.1251 +#define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */
1.1252 +#define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */
1.1253 +#define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1.1254 +#define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */
1.1255 +#define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */
1.1256 +#define ICDC_CDCCR1 (ICDC_BASE + 0x0080)
1.1257 +#define ICDC_CDCCR2 (ICDC_BASE + 0x0084)
1.1258 +
1.1259 +#define REG_ICDC_CR REG32(ICDC_CR)
1.1260 +#define REG_ICDC_APWAIT REG32(ICDC_APWAIT)
1.1261 +#define REG_ICDC_APPRE REG32(ICDC_APPRE)
1.1262 +#define REG_ICDC_APHPEN REG32(ICDC_APHPEN)
1.1263 +#define REG_ICDC_APSR REG32(ICDC_APSR)
1.1264 +#define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1)
1.1265 +#define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2)
1.1266 +
1.1267 +/* ICDC Control Register */
1.1268 +#define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */
1.1269 +#define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT)
1.1270 +#define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */
1.1271 +#define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT)
1.1272 + #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT)
1.1273 + #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT)
1.1274 + #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT)
1.1275 + #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT)
1.1276 + #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT)
1.1277 + #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT)
1.1278 + #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT)
1.1279 + #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT)
1.1280 + #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT)
1.1281 +#define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */
1.1282 +#define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT)
1.1283 + #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT)
1.1284 + #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT)
1.1285 + #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT)
1.1286 + #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT)
1.1287 +#define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */
1.1288 +#define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT)
1.1289 + #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT)
1.1290 + #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT)
1.1291 + #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT)
1.1292 + #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT)
1.1293 +#define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */
1.1294 +#define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */
1.1295 +#define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */
1.1296 +#define ICDC_CR_EADC (1 << 10) /* Enable ADC */
1.1297 +#define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */
1.1298 +#define ICDC_CR_EDAC (1 << 8) /* Enable DAC */
1.1299 +#define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */
1.1300 +#define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */
1.1301 +#define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */
1.1302 +#define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */
1.1303 +#define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */
1.1304 +#define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */
1.1305 +
1.1306 +/* Anti-Pop WAIT Stage Timing Control Register */
1.1307 +#define ICDC_APWAIT_WAITSN_BIT 0
1.1308 +#define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT)
1.1309 +
1.1310 +/* Anti-Pop HPEN-PRE Stage Timing Control Register */
1.1311 +#define ICDC_APPRE_PRESN_BIT 0
1.1312 +#define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT)
1.1313 +
1.1314 +/* Anti-Pop HPEN Stage Timing Control Register */
1.1315 +#define ICDC_APHPEN_HPENSN_BIT 0
1.1316 +#define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT)
1.1317 +
1.1318 +/* Anti-Pop Status Register */
1.1319 +#define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */
1.1320 +#define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT)
1.1321 +#define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */
1.1322 +#define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */
1.1323 + #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */
1.1324 +#define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */
1.1325 + #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */
1.1326 + #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */
1.1327 + #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */
1.1328 + #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */
1.1329 +#define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */
1.1330 +#define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT)
1.1331 +
1.1332 +
1.1333 +/*************************************************************************
1.1334 + * I2C
1.1335 + *************************************************************************/
1.1336 +#define I2C_DR (I2C_BASE + 0x000)
1.1337 +#define I2C_CR (I2C_BASE + 0x004)
1.1338 +#define I2C_SR (I2C_BASE + 0x008)
1.1339 +#define I2C_GR (I2C_BASE + 0x00C)
1.1340 +
1.1341 +#define REG_I2C_DR REG8(I2C_DR)
1.1342 +#define REG_I2C_CR REG8(I2C_CR)
1.1343 +#define REG_I2C_SR REG8(I2C_SR)
1.1344 +#define REG_I2C_GR REG16(I2C_GR)
1.1345 +
1.1346 +/* I2C Control Register (I2C_CR) */
1.1347 +
1.1348 +#define I2C_CR_IEN (1 << 4)
1.1349 +#define I2C_CR_STA (1 << 3)
1.1350 +#define I2C_CR_STO (1 << 2)
1.1351 +#define I2C_CR_AC (1 << 1)
1.1352 +#define I2C_CR_I2CE (1 << 0)
1.1353 +
1.1354 +/* I2C Status Register (I2C_SR) */
1.1355 +
1.1356 +#define I2C_SR_STX (1 << 4)
1.1357 +#define I2C_SR_BUSY (1 << 3)
1.1358 +#define I2C_SR_TEND (1 << 2)
1.1359 +#define I2C_SR_DRF (1 << 1)
1.1360 +#define I2C_SR_ACKF (1 << 0)
1.1361 +
1.1362 +
1.1363 +/*************************************************************************
1.1364 + * SSI
1.1365 + *************************************************************************/
1.1366 +#define SSI_DR (SSI_BASE + 0x000)
1.1367 +#define SSI_CR0 (SSI_BASE + 0x004)
1.1368 +#define SSI_CR1 (SSI_BASE + 0x008)
1.1369 +#define SSI_SR (SSI_BASE + 0x00C)
1.1370 +#define SSI_ITR (SSI_BASE + 0x010)
1.1371 +#define SSI_ICR (SSI_BASE + 0x014)
1.1372 +#define SSI_GR (SSI_BASE + 0x018)
1.1373 +
1.1374 +#define REG_SSI_DR REG32(SSI_DR)
1.1375 +#define REG_SSI_CR0 REG16(SSI_CR0)
1.1376 +#define REG_SSI_CR1 REG32(SSI_CR1)
1.1377 +#define REG_SSI_SR REG32(SSI_SR)
1.1378 +#define REG_SSI_ITR REG16(SSI_ITR)
1.1379 +#define REG_SSI_ICR REG8(SSI_ICR)
1.1380 +#define REG_SSI_GR REG16(SSI_GR)
1.1381 +
1.1382 +/* SSI Data Register (SSI_DR) */
1.1383 +
1.1384 +#define SSI_DR_GPC_BIT 0
1.1385 +#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
1.1386 +
1.1387 +/* SSI Control Register 0 (SSI_CR0) */
1.1388 +
1.1389 +#define SSI_CR0_SSIE (1 << 15)
1.1390 +#define SSI_CR0_TIE (1 << 14)
1.1391 +#define SSI_CR0_RIE (1 << 13)
1.1392 +#define SSI_CR0_TEIE (1 << 12)
1.1393 +#define SSI_CR0_REIE (1 << 11)
1.1394 +#define SSI_CR0_LOOP (1 << 10)
1.1395 +#define SSI_CR0_RFINE (1 << 9)
1.1396 +#define SSI_CR0_RFINC (1 << 8)
1.1397 +#define SSI_CR0_FSEL (1 << 6)
1.1398 +#define SSI_CR0_TFLUSH (1 << 2)
1.1399 +#define SSI_CR0_RFLUSH (1 << 1)
1.1400 +#define SSI_CR0_DISREV (1 << 0)
1.1401 +
1.1402 +/* SSI Control Register 1 (SSI_CR1) */
1.1403 +
1.1404 +#define SSI_CR1_FRMHL_BIT 30
1.1405 +#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT)
1.1406 + #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
1.1407 + #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
1.1408 + #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
1.1409 + #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
1.1410 +#define SSI_CR1_TFVCK_BIT 28
1.1411 +#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT)
1.1412 + #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT)
1.1413 + #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT)
1.1414 + #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT)
1.1415 + #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT)
1.1416 +#define SSI_CR1_TCKFI_BIT 26
1.1417 +#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT)
1.1418 + #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT)
1.1419 + #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT)
1.1420 + #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT)
1.1421 + #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT)
1.1422 +#define SSI_CR1_LFST (1 << 25)
1.1423 +#define SSI_CR1_ITFRM (1 << 24)
1.1424 +#define SSI_CR1_UNFIN (1 << 23)
1.1425 +#define SSI_CR1_MULTS (1 << 22)
1.1426 +#define SSI_CR1_FMAT_BIT 20
1.1427 +#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
1.1428 + #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
1.1429 + #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
1.1430 + #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
1.1431 + #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
1.1432 +#define SSI_CR1_TTRG_BIT 16
1.1433 +#define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT)
1.1434 + #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)
1.1435 + #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT)
1.1436 + #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT)
1.1437 + #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT)
1.1438 + #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT)
1.1439 + #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT)
1.1440 + #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT)
1.1441 + #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT)
1.1442 + #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT)
1.1443 + #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT)
1.1444 + #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT)
1.1445 + #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT)
1.1446 + #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT)
1.1447 + #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT)
1.1448 + #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT)
1.1449 + #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT)
1.1450 +#define SSI_CR1_MCOM_BIT 12
1.1451 +#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT)
1.1452 + #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
1.1453 + #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
1.1454 + #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
1.1455 + #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
1.1456 + #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
1.1457 + #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
1.1458 + #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
1.1459 + #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
1.1460 + #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
1.1461 + #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
1.1462 + #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
1.1463 + #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
1.1464 + #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
1.1465 + #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
1.1466 + #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
1.1467 + #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
1.1468 +#define SSI_CR1_RTRG_BIT 8
1.1469 +#define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT)
1.1470 + #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT)
1.1471 + #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT)
1.1472 + #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT)
1.1473 + #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT)
1.1474 + #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT)
1.1475 + #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT)
1.1476 + #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT)
1.1477 + #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT)
1.1478 + #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT)
1.1479 + #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT)
1.1480 + #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT)
1.1481 + #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT)
1.1482 + #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT)
1.1483 + #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT)
1.1484 + #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT)
1.1485 + #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT)
1.1486 +#define SSI_CR1_FLEN_BIT 4
1.1487 +#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
1.1488 + #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
1.1489 + #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
1.1490 + #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
1.1491 + #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
1.1492 + #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
1.1493 + #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
1.1494 + #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
1.1495 + #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
1.1496 + #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
1.1497 + #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
1.1498 + #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
1.1499 + #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT)
1.1500 + #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT)
1.1501 + #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT)
1.1502 + #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT)
1.1503 + #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT)
1.1504 +#define SSI_CR1_PHA (1 << 1)
1.1505 +#define SSI_CR1_POL (1 << 0)
1.1506 +
1.1507 +/* SSI Status Register (SSI_SR) */
1.1508 +
1.1509 +#define SSI_SR_TFIFONUM_BIT 16
1.1510 +#define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT)
1.1511 +#define SSI_SR_RFIFONUM_BIT 8
1.1512 +#define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT)
1.1513 +#define SSI_SR_END (1 << 7)
1.1514 +#define SSI_SR_BUSY (1 << 6)
1.1515 +#define SSI_SR_TFF (1 << 5)
1.1516 +#define SSI_SR_RFE (1 << 4)
1.1517 +#define SSI_SR_TFHE (1 << 3)
1.1518 +#define SSI_SR_RFHF (1 << 2)
1.1519 +#define SSI_SR_UNDR (1 << 1)
1.1520 +#define SSI_SR_OVER (1 << 0)
1.1521 +
1.1522 +/* SSI Interval Time Control Register (SSI_ITR) */
1.1523 +
1.1524 +#define SSI_ITR_CNTCLK (1 << 15)
1.1525 +#define SSI_ITR_IVLTM_BIT 0
1.1526 +#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT)
1.1527 +
1.1528 +
1.1529 +/*************************************************************************
1.1530 + * MSC
1.1531 + *************************************************************************/
1.1532 +#define MSC_STRPCL (MSC_BASE + 0x000)
1.1533 +#define MSC_STAT (MSC_BASE + 0x004)
1.1534 +#define MSC_CLKRT (MSC_BASE + 0x008)
1.1535 +#define MSC_CMDAT (MSC_BASE + 0x00C)
1.1536 +#define MSC_RESTO (MSC_BASE + 0x010)
1.1537 +#define MSC_RDTO (MSC_BASE + 0x014)
1.1538 +#define MSC_BLKLEN (MSC_BASE + 0x018)
1.1539 +#define MSC_NOB (MSC_BASE + 0x01C)
1.1540 +#define MSC_SNOB (MSC_BASE + 0x020)
1.1541 +#define MSC_IMASK (MSC_BASE + 0x024)
1.1542 +#define MSC_IREG (MSC_BASE + 0x028)
1.1543 +#define MSC_CMD (MSC_BASE + 0x02C)
1.1544 +#define MSC_ARG (MSC_BASE + 0x030)
1.1545 +#define MSC_RES (MSC_BASE + 0x034)
1.1546 +#define MSC_RXFIFO (MSC_BASE + 0x038)
1.1547 +#define MSC_TXFIFO (MSC_BASE + 0x03C)
1.1548 +
1.1549 +#define REG_MSC_STRPCL REG16(MSC_STRPCL)
1.1550 +#define REG_MSC_STAT REG32(MSC_STAT)
1.1551 +#define REG_MSC_CLKRT REG16(MSC_CLKRT)
1.1552 +#define REG_MSC_CMDAT REG32(MSC_CMDAT)
1.1553 +#define REG_MSC_RESTO REG16(MSC_RESTO)
1.1554 +#define REG_MSC_RDTO REG16(MSC_RDTO)
1.1555 +#define REG_MSC_BLKLEN REG16(MSC_BLKLEN)
1.1556 +#define REG_MSC_NOB REG16(MSC_NOB)
1.1557 +#define REG_MSC_SNOB REG16(MSC_SNOB)
1.1558 +#define REG_MSC_IMASK REG16(MSC_IMASK)
1.1559 +#define REG_MSC_IREG REG16(MSC_IREG)
1.1560 +#define REG_MSC_CMD REG8(MSC_CMD)
1.1561 +#define REG_MSC_ARG REG32(MSC_ARG)
1.1562 +#define REG_MSC_RES REG16(MSC_RES)
1.1563 +#define REG_MSC_RXFIFO REG32(MSC_RXFIFO)
1.1564 +#define REG_MSC_TXFIFO REG32(MSC_TXFIFO)
1.1565 +
1.1566 +/* MSC Clock and Control Register (MSC_STRPCL) */
1.1567 +
1.1568 +#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
1.1569 +#define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
1.1570 +#define MSC_STRPCL_START_READWAIT (1 << 5)
1.1571 +#define MSC_STRPCL_STOP_READWAIT (1 << 4)
1.1572 +#define MSC_STRPCL_RESET (1 << 3)
1.1573 +#define MSC_STRPCL_START_OP (1 << 2)
1.1574 +#define MSC_STRPCL_CLOCK_CONTROL_BIT 0
1.1575 +#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
1.1576 + #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
1.1577 + #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
1.1578 +
1.1579 +/* MSC Status Register (MSC_STAT) */
1.1580 +
1.1581 +#define MSC_STAT_IS_RESETTING (1 << 15)
1.1582 +#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
1.1583 +#define MSC_STAT_PRG_DONE (1 << 13)
1.1584 +#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
1.1585 +#define MSC_STAT_END_CMD_RES (1 << 11)
1.1586 +#define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
1.1587 +#define MSC_STAT_IS_READWAIT (1 << 9)
1.1588 +#define MSC_STAT_CLK_EN (1 << 8)
1.1589 +#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
1.1590 +#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
1.1591 +#define MSC_STAT_CRC_RES_ERR (1 << 5)
1.1592 +#define MSC_STAT_CRC_READ_ERROR (1 << 4)
1.1593 +#define MSC_STAT_CRC_WRITE_ERROR_BIT 2
1.1594 +#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
1.1595 + #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
1.1596 + #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
1.1597 + #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
1.1598 +#define MSC_STAT_TIME_OUT_RES (1 << 1)
1.1599 +#define MSC_STAT_TIME_OUT_READ (1 << 0)
1.1600 +
1.1601 +/* MSC Bus Clock Control Register (MSC_CLKRT) */
1.1602 +
1.1603 +#define MSC_CLKRT_CLK_RATE_BIT 0
1.1604 +#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
1.1605 + #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
1.1606 + #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
1.1607 + #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
1.1608 + #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
1.1609 + #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
1.1610 + #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
1.1611 + #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
1.1612 + #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
1.1613 +
1.1614 +/* MSC Command Sequence Control Register (MSC_CMDAT) */
1.1615 +
1.1616 +#define MSC_CMDAT_IO_ABORT (1 << 11)
1.1617 +#define MSC_CMDAT_BUS_WIDTH_BIT 9
1.1618 +#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
1.1619 + #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
1.1620 + #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
1.1621 + #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
1.1622 + #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
1.1623 +#define MSC_CMDAT_DMA_EN (1 << 8)
1.1624 +#define MSC_CMDAT_INIT (1 << 7)
1.1625 +#define MSC_CMDAT_BUSY (1 << 6)
1.1626 +#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
1.1627 +#define MSC_CMDAT_WRITE (1 << 4)
1.1628 +#define MSC_CMDAT_READ (0 << 4)
1.1629 +#define MSC_CMDAT_DATA_EN (1 << 3)
1.1630 +#define MSC_CMDAT_RESPONSE_BIT 0
1.1631 +#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
1.1632 + #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
1.1633 + #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
1.1634 + #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
1.1635 + #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
1.1636 + #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
1.1637 + #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
1.1638 + #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
1.1639 +
1.1640 +#define CMDAT_DMA_EN (1 << 8)
1.1641 +#define CMDAT_INIT (1 << 7)
1.1642 +#define CMDAT_BUSY (1 << 6)
1.1643 +#define CMDAT_STREAM (1 << 5)
1.1644 +#define CMDAT_WRITE (1 << 4)
1.1645 +#define CMDAT_DATA_EN (1 << 3)
1.1646 +
1.1647 +/* MSC Interrupts Mask Register (MSC_IMASK) */
1.1648 +
1.1649 +#define MSC_IMASK_SDIO (1 << 7)
1.1650 +#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
1.1651 +#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
1.1652 +#define MSC_IMASK_END_CMD_RES (1 << 2)
1.1653 +#define MSC_IMASK_PRG_DONE (1 << 1)
1.1654 +#define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
1.1655 +
1.1656 +
1.1657 +/* MSC Interrupts Status Register (MSC_IREG) */
1.1658 +
1.1659 +#define MSC_IREG_SDIO (1 << 7)
1.1660 +#define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
1.1661 +#define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
1.1662 +#define MSC_IREG_END_CMD_RES (1 << 2)
1.1663 +#define MSC_IREG_PRG_DONE (1 << 1)
1.1664 +#define MSC_IREG_DATA_TRAN_DONE (1 << 0)
1.1665 +
1.1666 +
1.1667 +/*************************************************************************
1.1668 + * EMC (External Memory Controller)
1.1669 + *************************************************************************/
1.1670 +#define EMC_BCR (EMC_BASE + 0x0) /* BCR */
1.1671 +
1.1672 +#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */
1.1673 +#define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */
1.1674 +#define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */
1.1675 +#define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */
1.1676 +#define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */
1.1677 +#define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */
1.1678 +#define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */
1.1679 +#define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */
1.1680 +#define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */
1.1681 +#define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */
1.1682 +
1.1683 +#define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */
1.1684 +#define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */
1.1685 +#define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */
1.1686 +#define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */
1.1687 +#define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */
1.1688 +#define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */
1.1689 +#define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */
1.1690 +#define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */
1.1691 +#define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */
1.1692 +#define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */
1.1693 +#define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */
1.1694 +#define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */
1.1695 +
1.1696 +#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
1.1697 +#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
1.1698 +#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
1.1699 +#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
1.1700 +#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */
1.1701 +#define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */
1.1702 +
1.1703 +#define REG_EMC_BCR REG32(EMC_BCR)
1.1704 +
1.1705 +#define REG_EMC_SMCR0 REG32(EMC_SMCR0)
1.1706 +#define REG_EMC_SMCR1 REG32(EMC_SMCR1)
1.1707 +#define REG_EMC_SMCR2 REG32(EMC_SMCR2)
1.1708 +#define REG_EMC_SMCR3 REG32(EMC_SMCR3)
1.1709 +#define REG_EMC_SMCR4 REG32(EMC_SMCR4)
1.1710 +#define REG_EMC_SACR0 REG32(EMC_SACR0)
1.1711 +#define REG_EMC_SACR1 REG32(EMC_SACR1)
1.1712 +#define REG_EMC_SACR2 REG32(EMC_SACR2)
1.1713 +#define REG_EMC_SACR3 REG32(EMC_SACR3)
1.1714 +#define REG_EMC_SACR4 REG32(EMC_SACR4)
1.1715 +
1.1716 +#define REG_EMC_NFCSR REG32(EMC_NFCSR)
1.1717 +#define REG_EMC_NFECR REG32(EMC_NFECR)
1.1718 +#define REG_EMC_NFECC REG32(EMC_NFECC)
1.1719 +#define REG_EMC_NFPAR0 REG32(EMC_NFPAR0)
1.1720 +#define REG_EMC_NFPAR1 REG32(EMC_NFPAR1)
1.1721 +#define REG_EMC_NFPAR2 REG32(EMC_NFPAR2)
1.1722 +#define REG_EMC_NFINTS REG32(EMC_NFINTS)
1.1723 +#define REG_EMC_NFINTE REG32(EMC_NFINTE)
1.1724 +#define REG_EMC_NFERR0 REG32(EMC_NFERR0)
1.1725 +#define REG_EMC_NFERR1 REG32(EMC_NFERR1)
1.1726 +#define REG_EMC_NFERR2 REG32(EMC_NFERR2)
1.1727 +#define REG_EMC_NFERR3 REG32(EMC_NFERR3)
1.1728 +
1.1729 +#define REG_EMC_DMCR REG32(EMC_DMCR)
1.1730 +#define REG_EMC_RTCSR REG16(EMC_RTCSR)
1.1731 +#define REG_EMC_RTCNT REG16(EMC_RTCNT)
1.1732 +#define REG_EMC_RTCOR REG16(EMC_RTCOR)
1.1733 +#define REG_EMC_DMAR0 REG32(EMC_DMAR0)
1.1734 +
1.1735 +/* Static Memory Control Register */
1.1736 +#define EMC_SMCR_STRV_BIT 24
1.1737 +#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
1.1738 +#define EMC_SMCR_TAW_BIT 20
1.1739 +#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
1.1740 +#define EMC_SMCR_TBP_BIT 16
1.1741 +#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
1.1742 +#define EMC_SMCR_TAH_BIT 12
1.1743 +#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
1.1744 +#define EMC_SMCR_TAS_BIT 8
1.1745 +#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
1.1746 +#define EMC_SMCR_BW_BIT 6
1.1747 +#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
1.1748 + #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
1.1749 + #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
1.1750 + #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
1.1751 +#define EMC_SMCR_BCM (1 << 3)
1.1752 +#define EMC_SMCR_BL_BIT 1
1.1753 +#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
1.1754 + #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
1.1755 + #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
1.1756 + #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
1.1757 + #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
1.1758 +#define EMC_SMCR_SMT (1 << 0)
1.1759 +
1.1760 +/* Static Memory Bank Addr Config Reg */
1.1761 +#define EMC_SACR_BASE_BIT 8
1.1762 +#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
1.1763 +#define EMC_SACR_MASK_BIT 0
1.1764 +#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
1.1765 +
1.1766 +/* NAND Flash Control/Status Register */
1.1767 +#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
1.1768 +#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
1.1769 +#define EMC_NFCSR_NFCE3 (1 << 5)
1.1770 +#define EMC_NFCSR_NFE3 (1 << 4)
1.1771 +#define EMC_NFCSR_NFCE2 (1 << 3)
1.1772 +#define EMC_NFCSR_NFE2 (1 << 2)
1.1773 +#define EMC_NFCSR_NFCE1 (1 << 1)
1.1774 +#define EMC_NFCSR_NFE1 (1 << 0)
1.1775 +
1.1776 +/* NAND Flash ECC Control Register */
1.1777 +#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */
1.1778 +#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */
1.1779 +#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */
1.1780 +#define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */
1.1781 +#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */
1.1782 +#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */
1.1783 +#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */
1.1784 +
1.1785 +/* NAND Flash ECC Data Register */
1.1786 +#define EMC_NFECC_ECC2_BIT 16
1.1787 +#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
1.1788 +#define EMC_NFECC_ECC1_BIT 8
1.1789 +#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
1.1790 +#define EMC_NFECC_ECC0_BIT 0
1.1791 +#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
1.1792 +
1.1793 +/* NAND Flash Interrupt Status Register */
1.1794 +#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */
1.1795 +#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
1.1796 +#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */
1.1797 +#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */
1.1798 +#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */
1.1799 +#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */
1.1800 +#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */
1.1801 +
1.1802 +/* NAND Flash Interrupt Enable Register */
1.1803 +#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */
1.1804 +#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */
1.1805 +#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */
1.1806 +#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */
1.1807 +#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */
1.1808 +
1.1809 +/* NAND Flash RS Error Report Register */
1.1810 +#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */
1.1811 +#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT)
1.1812 +#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */
1.1813 +#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT)
1.1814 +
1.1815 +
1.1816 +/* DRAM Control Register */
1.1817 +#define EMC_DMCR_BW_BIT 31
1.1818 +#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
1.1819 +#define EMC_DMCR_CA_BIT 26
1.1820 +#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
1.1821 + #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
1.1822 + #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
1.1823 + #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
1.1824 + #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
1.1825 + #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
1.1826 +#define EMC_DMCR_RMODE (1 << 25)
1.1827 +#define EMC_DMCR_RFSH (1 << 24)
1.1828 +#define EMC_DMCR_MRSET (1 << 23)
1.1829 +#define EMC_DMCR_RA_BIT 20
1.1830 +#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
1.1831 + #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
1.1832 + #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
1.1833 + #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
1.1834 +#define EMC_DMCR_BA_BIT 19
1.1835 +#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
1.1836 +#define EMC_DMCR_PDM (1 << 18)
1.1837 +#define EMC_DMCR_EPIN (1 << 17)
1.1838 +#define EMC_DMCR_TRAS_BIT 13
1.1839 +#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
1.1840 +#define EMC_DMCR_RCD_BIT 11
1.1841 +#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
1.1842 +#define EMC_DMCR_TPC_BIT 8
1.1843 +#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
1.1844 +#define EMC_DMCR_TRWL_BIT 5
1.1845 +#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
1.1846 +#define EMC_DMCR_TRC_BIT 2
1.1847 +#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
1.1848 +#define EMC_DMCR_TCL_BIT 0
1.1849 +#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
1.1850 +
1.1851 +/* Refresh Time Control/Status Register */
1.1852 +#define EMC_RTCSR_CMF (1 << 7)
1.1853 +#define EMC_RTCSR_CKS_BIT 0
1.1854 +#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
1.1855 + #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
1.1856 + #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
1.1857 + #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
1.1858 + #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
1.1859 + #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
1.1860 + #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
1.1861 + #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
1.1862 + #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
1.1863 +
1.1864 +/* SDRAM Bank Address Configuration Register */
1.1865 +#define EMC_DMAR_BASE_BIT 8
1.1866 +#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
1.1867 +#define EMC_DMAR_MASK_BIT 0
1.1868 +#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
1.1869 +
1.1870 +/* Mode Register of SDRAM bank 0 */
1.1871 +#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
1.1872 +#define EMC_SDMR_OM_BIT 7 /* Operating Mode */
1.1873 +#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
1.1874 + #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
1.1875 +#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
1.1876 +#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
1.1877 + #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
1.1878 + #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
1.1879 + #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
1.1880 +#define EMC_SDMR_BT_BIT 3 /* Burst Type */
1.1881 +#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
1.1882 + #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
1.1883 + #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
1.1884 +#define EMC_SDMR_BL_BIT 0 /* Burst Length */
1.1885 +#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
1.1886 + #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
1.1887 + #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
1.1888 + #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
1.1889 + #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
1.1890 +
1.1891 +#define EMC_SDMR_CAS2_16BIT \
1.1892 + (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1.1893 +#define EMC_SDMR_CAS2_32BIT \
1.1894 + (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1.1895 +#define EMC_SDMR_CAS3_16BIT \
1.1896 + (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1.1897 +#define EMC_SDMR_CAS3_32BIT \
1.1898 + (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1.1899 +
1.1900 +
1.1901 +/*************************************************************************
1.1902 + * CIM
1.1903 + *************************************************************************/
1.1904 +#define CIM_CFG (CIM_BASE + 0x0000)
1.1905 +#define CIM_CTRL (CIM_BASE + 0x0004)
1.1906 +#define CIM_STATE (CIM_BASE + 0x0008)
1.1907 +#define CIM_IID (CIM_BASE + 0x000C)
1.1908 +#define CIM_RXFIFO (CIM_BASE + 0x0010)
1.1909 +#define CIM_DA (CIM_BASE + 0x0020)
1.1910 +#define CIM_FA (CIM_BASE + 0x0024)
1.1911 +#define CIM_FID (CIM_BASE + 0x0028)
1.1912 +#define CIM_CMD (CIM_BASE + 0x002C)
1.1913 +
1.1914 +#define REG_CIM_CFG REG32(CIM_CFG)
1.1915 +#define REG_CIM_CTRL REG32(CIM_CTRL)
1.1916 +#define REG_CIM_STATE REG32(CIM_STATE)
1.1917 +#define REG_CIM_IID REG32(CIM_IID)
1.1918 +#define REG_CIM_RXFIFO REG32(CIM_RXFIFO)
1.1919 +#define REG_CIM_DA REG32(CIM_DA)
1.1920 +#define REG_CIM_FA REG32(CIM_FA)
1.1921 +#define REG_CIM_FID REG32(CIM_FID)
1.1922 +#define REG_CIM_CMD REG32(CIM_CMD)
1.1923 +
1.1924 +/* CIM Configuration Register (CIM_CFG) */
1.1925 +
1.1926 +#define CIM_CFG_INV_DAT (1 << 15)
1.1927 +#define CIM_CFG_VSP (1 << 14)
1.1928 +#define CIM_CFG_HSP (1 << 13)
1.1929 +#define CIM_CFG_PCP (1 << 12)
1.1930 +#define CIM_CFG_DUMMY_ZERO (1 << 9)
1.1931 +#define CIM_CFG_EXT_VSYNC (1 << 8)
1.1932 +#define CIM_CFG_PACK_BIT 4
1.1933 +#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT)
1.1934 + #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT)
1.1935 + #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT)
1.1936 + #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT)
1.1937 + #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT)
1.1938 + #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT)
1.1939 + #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT)
1.1940 + #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT)
1.1941 + #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT)
1.1942 +#define CIM_CFG_DSM_BIT 0
1.1943 +#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT)
1.1944 + #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
1.1945 + #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
1.1946 + #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
1.1947 + #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */
1.1948 +
1.1949 +/* CIM Control Register (CIM_CTRL) */
1.1950 +
1.1951 +#define CIM_CTRL_MCLKDIV_BIT 24
1.1952 +#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT)
1.1953 +#define CIM_CTRL_FRC_BIT 16
1.1954 +#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT)
1.1955 + #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
1.1956 + #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
1.1957 + #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
1.1958 + #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
1.1959 + #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
1.1960 + #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
1.1961 + #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
1.1962 + #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
1.1963 + #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
1.1964 + #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
1.1965 + #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
1.1966 + #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
1.1967 + #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
1.1968 + #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
1.1969 + #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
1.1970 + #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
1.1971 +#define CIM_CTRL_VDDM (1 << 13)
1.1972 +#define CIM_CTRL_DMA_SOFM (1 << 12)
1.1973 +#define CIM_CTRL_DMA_EOFM (1 << 11)
1.1974 +#define CIM_CTRL_DMA_STOPM (1 << 10)
1.1975 +#define CIM_CTRL_RXF_TRIGM (1 << 9)
1.1976 +#define CIM_CTRL_RXF_OFM (1 << 8)
1.1977 +#define CIM_CTRL_RXF_TRIG_BIT 4
1.1978 +#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT)
1.1979 + #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */
1.1980 + #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */
1.1981 + #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */
1.1982 + #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */
1.1983 + #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */
1.1984 + #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */
1.1985 + #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */
1.1986 + #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */
1.1987 +#define CIM_CTRL_DMA_EN (1 << 2)
1.1988 +#define CIM_CTRL_RXF_RST (1 << 1)
1.1989 +#define CIM_CTRL_ENA (1 << 0)
1.1990 +
1.1991 +/* CIM State Register (CIM_STATE) */
1.1992 +
1.1993 +#define CIM_STATE_DMA_SOF (1 << 6)
1.1994 +#define CIM_STATE_DMA_EOF (1 << 5)
1.1995 +#define CIM_STATE_DMA_STOP (1 << 4)
1.1996 +#define CIM_STATE_RXF_OF (1 << 3)
1.1997 +#define CIM_STATE_RXF_TRIG (1 << 2)
1.1998 +#define CIM_STATE_RXF_EMPTY (1 << 1)
1.1999 +#define CIM_STATE_VDD (1 << 0)
1.2000 +
1.2001 +/* CIM DMA Command Register (CIM_CMD) */
1.2002 +
1.2003 +#define CIM_CMD_SOFINT (1 << 31)
1.2004 +#define CIM_CMD_EOFINT (1 << 30)
1.2005 +#define CIM_CMD_STOP (1 << 28)
1.2006 +#define CIM_CMD_LEN_BIT 0
1.2007 +#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT)
1.2008 +
1.2009 +
1.2010 +/*************************************************************************
1.2011 + * SADC (Smart A/D Controller)
1.2012 + *************************************************************************/
1.2013 +
1.2014 +#define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */
1.2015 +#define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */
1.2016 +#define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */
1.2017 +#define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/
1.2018 +#define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */
1.2019 +#define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */
1.2020 +#define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */
1.2021 +#define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */
1.2022 +#define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */
1.2023 +
1.2024 +#define REG_SADC_ENA REG8(SADC_ENA)
1.2025 +#define REG_SADC_CFG REG32(SADC_CFG)
1.2026 +#define REG_SADC_CTRL REG8(SADC_CTRL)
1.2027 +#define REG_SADC_STATE REG8(SADC_STATE)
1.2028 +#define REG_SADC_SAMETIME REG16(SADC_SAMETIME)
1.2029 +#define REG_SADC_WAITTIME REG16(SADC_WAITTIME)
1.2030 +#define REG_SADC_TSDAT REG32(SADC_TSDAT)
1.2031 +#define REG_SADC_BATDAT REG16(SADC_BATDAT)
1.2032 +#define REG_SADC_SADDAT REG16(SADC_SADDAT)
1.2033 +
1.2034 +/* ADC Enable Register */
1.2035 +#define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */
1.2036 +#define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */
1.2037 +#define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */
1.2038 +#define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */
1.2039 +
1.2040 +/* ADC Configure Register */
1.2041 +#define SADC_CFG_CLKOUT_NUM_BIT 16
1.2042 +#define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT)
1.2043 +#define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */
1.2044 +#define SADC_CFG_XYZ_BIT 13 /* XYZ selection */
1.2045 +#define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT)
1.2046 + #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT)
1.2047 + #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT)
1.2048 + #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
1.2049 +#define SADC_CFG_SNUM_BIT 10 /* Sample Number */
1.2050 +#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT)
1.2051 + #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
1.2052 + #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
1.2053 + #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT)
1.2054 + #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT)
1.2055 + #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT)
1.2056 + #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
1.2057 + #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
1.2058 + #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
1.2059 +#define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */
1.2060 +#define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT)
1.2061 +#define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */
1.2062 +#define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */
1.2063 +#define SADC_CFG_CMD_BIT 0 /* ADC Command */
1.2064 +#define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT)
1.2065 + #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */
1.2066 + #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */
1.2067 + #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */
1.2068 + #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */
1.2069 + #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */
1.2070 + #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */
1.2071 + #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */
1.2072 + #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */
1.2073 + #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */
1.2074 + #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */
1.2075 + #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */
1.2076 + #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */
1.2077 + #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */
1.2078 +
1.2079 +/* ADC Control Register */
1.2080 +#define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */
1.2081 +#define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */
1.2082 +#define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */
1.2083 +#define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */
1.2084 +#define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */
1.2085 +
1.2086 +/* ADC Status Register */
1.2087 +#define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */
1.2088 +#define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */
1.2089 +#define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */
1.2090 +#define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */
1.2091 +#define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */
1.2092 +#define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */
1.2093 +#define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */
1.2094 +#define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */
1.2095 +
1.2096 +/* ADC Touch Screen Data Register */
1.2097 +#define SADC_TSDAT_DATA0_BIT 0
1.2098 +#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT)
1.2099 +#define SADC_TSDAT_TYPE0 (1 << 15)
1.2100 +#define SADC_TSDAT_DATA1_BIT 16
1.2101 +#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT)
1.2102 +#define SADC_TSDAT_TYPE1 (1 << 31)
1.2103 +
1.2104 +
1.2105 +/*************************************************************************
1.2106 + * SLCD (Smart LCD Controller)
1.2107 + *************************************************************************/
1.2108 +
1.2109 +#define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */
1.2110 +#define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */
1.2111 +#define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */
1.2112 +#define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */
1.2113 +#define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */
1.2114 +
1.2115 +#define REG_SLCD_CFG REG32(SLCD_CFG)
1.2116 +#define REG_SLCD_CTRL REG8(SLCD_CTRL)
1.2117 +#define REG_SLCD_STATE REG8(SLCD_STATE)
1.2118 +#define REG_SLCD_DATA REG32(SLCD_DATA)
1.2119 +#define REG_SLCD_FIFO REG32(SLCD_FIFO)
1.2120 +
1.2121 +/* SLCD Configure Register */
1.2122 +#define SLCD_CFG_BURST_BIT 14
1.2123 +#define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT)
1.2124 + #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT)
1.2125 + #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT)
1.2126 +#define SLCD_CFG_DWIDTH_BIT 10
1.2127 +#define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT)
1.2128 + #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT)
1.2129 + #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT)
1.2130 + #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT)
1.2131 + #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT)
1.2132 + #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT)
1.2133 +#define SLCD_CFG_CWIDTH_16BIT (0 << 8)
1.2134 +#define SLCD_CFG_CWIDTH_8BIT (1 << 8)
1.2135 +#define SLCD_CFG_CS_ACTIVE_LOW (0 << 4)
1.2136 +#define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
1.2137 +#define SLCD_CFG_RS_CMD_LOW (0 << 3)
1.2138 +#define SLCD_CFG_RS_CMD_HIGH (1 << 3)
1.2139 +#define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1)
1.2140 +#define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1)
1.2141 +#define SLCD_CFG_TYPE_PARALLEL (0 << 0)
1.2142 +#define SLCD_CFG_TYPE_SERIAL (1 << 0)
1.2143 +
1.2144 +/* SLCD Control Register */
1.2145 +#define SLCD_CTRL_DMA_EN (1 << 0)
1.2146 +
1.2147 +/* SLCD Status Register */
1.2148 +#define SLCD_STATE_BUSY (1 << 0)
1.2149 +
1.2150 +/* SLCD Data Register */
1.2151 +#define SLCD_DATA_RS_DATA (0 << 31)
1.2152 +#define SLCD_DATA_RS_COMMAND (1 << 31)
1.2153 +
1.2154 +/* SLCD FIFO Register */
1.2155 +#define SLCD_FIFO_RS_DATA (0 << 31)
1.2156 +#define SLCD_FIFO_RS_COMMAND (1 << 31)
1.2157 +
1.2158 +
1.2159 +/*************************************************************************
1.2160 + * LCD (LCD Controller)
1.2161 + *************************************************************************/
1.2162 +#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
1.2163 +#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
1.2164 +#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
1.2165 +#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
1.2166 +#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
1.2167 +#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
1.2168 +#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
1.2169 +#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
1.2170 +#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
1.2171 +#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
1.2172 +#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
1.2173 +#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
1.2174 +#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
1.2175 +#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
1.2176 +#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
1.2177 +#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
1.2178 +#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
1.2179 +#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
1.2180 +#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
1.2181 +#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
1.2182 +#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
1.2183 +
1.2184 +#define REG_LCD_CFG REG32(LCD_CFG)
1.2185 +#define REG_LCD_VSYNC REG32(LCD_VSYNC)
1.2186 +#define REG_LCD_HSYNC REG32(LCD_HSYNC)
1.2187 +#define REG_LCD_VAT REG32(LCD_VAT)
1.2188 +#define REG_LCD_DAH REG32(LCD_DAH)
1.2189 +#define REG_LCD_DAV REG32(LCD_DAV)
1.2190 +#define REG_LCD_PS REG32(LCD_PS)
1.2191 +#define REG_LCD_CLS REG32(LCD_CLS)
1.2192 +#define REG_LCD_SPL REG32(LCD_SPL)
1.2193 +#define REG_LCD_REV REG32(LCD_REV)
1.2194 +#define REG_LCD_CTRL REG32(LCD_CTRL)
1.2195 +#define REG_LCD_STATE REG32(LCD_STATE)
1.2196 +#define REG_LCD_IID REG32(LCD_IID)
1.2197 +#define REG_LCD_DA0 REG32(LCD_DA0)
1.2198 +#define REG_LCD_SA0 REG32(LCD_SA0)
1.2199 +#define REG_LCD_FID0 REG32(LCD_FID0)
1.2200 +#define REG_LCD_CMD0 REG32(LCD_CMD0)
1.2201 +#define REG_LCD_DA1 REG32(LCD_DA1)
1.2202 +#define REG_LCD_SA1 REG32(LCD_SA1)
1.2203 +#define REG_LCD_FID1 REG32(LCD_FID1)
1.2204 +#define REG_LCD_CMD1 REG32(LCD_CMD1)
1.2205 +
1.2206 +/* LCD Configure Register */
1.2207 +#define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */
1.2208 +#define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT)
1.2209 + #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT)
1.2210 + #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT)
1.2211 +#define LCD_CFG_PSM (1 << 23) /* PS signal mode */
1.2212 +#define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */
1.2213 +#define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */
1.2214 +#define LCD_CFG_REVM (1 << 20) /* REV signal mode */
1.2215 +#define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */
1.2216 +#define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */
1.2217 +#define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */
1.2218 +#define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */
1.2219 +#define LCD_CFG_PSP (1 << 15) /* PS pin reset state */
1.2220 +#define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */
1.2221 +#define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */
1.2222 +#define LCD_CFG_REVP (1 << 12) /* REV pin reset state */
1.2223 +#define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */
1.2224 +#define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */
1.2225 +#define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */
1.2226 +#define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */
1.2227 +#define LCD_CFG_PDW_BIT 4 /* STN pins utilization */
1.2228 +#define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT)
1.2229 +#define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */
1.2230 + #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */
1.2231 + #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */
1.2232 + #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */
1.2233 +#define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */
1.2234 +#define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT)
1.2235 + #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
1.2236 + #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT)
1.2237 + #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT)
1.2238 + #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT)
1.2239 + #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT)
1.2240 + #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT)
1.2241 + #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT)
1.2242 + #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT)
1.2243 + #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT)
1.2244 + #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT)
1.2245 + #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT)
1.2246 + #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT)
1.2247 + /* JZ47XX defines */
1.2248 + #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT)
1.2249 + #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT)
1.2250 + #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT)
1.2251 +
1.2252 +
1.2253 +
1.2254 +/* Vertical Synchronize Register */
1.2255 +#define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */
1.2256 +#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT)
1.2257 +#define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */
1.2258 +#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT)
1.2259 +
1.2260 +/* Horizontal Synchronize Register */
1.2261 +#define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */
1.2262 +#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT)
1.2263 +#define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */
1.2264 +#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT)
1.2265 +
1.2266 +/* Virtual Area Setting Register */
1.2267 +#define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */
1.2268 +#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT)
1.2269 +#define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */
1.2270 +#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT)
1.2271 +
1.2272 +/* Display Area Horizontal Start/End Point Register */
1.2273 +#define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */
1.2274 +#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT)
1.2275 +#define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */
1.2276 +#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT)
1.2277 +
1.2278 +/* Display Area Vertical Start/End Point Register */
1.2279 +#define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */
1.2280 +#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT)
1.2281 +#define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */
1.2282 +#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT)
1.2283 +
1.2284 +/* PS Signal Setting */
1.2285 +#define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */
1.2286 +#define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT)
1.2287 +#define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */
1.2288 +#define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT)
1.2289 +
1.2290 +/* CLS Signal Setting */
1.2291 +#define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */
1.2292 +#define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT)
1.2293 +#define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */
1.2294 +#define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT)
1.2295 +
1.2296 +/* SPL Signal Setting */
1.2297 +#define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */
1.2298 +#define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT)
1.2299 +#define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */
1.2300 +#define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT)
1.2301 +
1.2302 +/* REV Signal Setting */
1.2303 +#define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */
1.2304 +#define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT)
1.2305 +
1.2306 +/* LCD Control Register */
1.2307 +#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
1.2308 +#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
1.2309 + #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
1.2310 + #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
1.2311 + #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
1.2312 +#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */
1.2313 +#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */
1.2314 +#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
1.2315 +#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
1.2316 +#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
1.2317 + #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
1.2318 + #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
1.2319 + #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
1.2320 +#define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */
1.2321 +#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT)
1.2322 +#define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */
1.2323 +#define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */
1.2324 +#define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */
1.2325 +#define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */
1.2326 +#define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */
1.2327 +#define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */
1.2328 +#define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */
1.2329 +#define LCD_CTRL_BEDN (1 << 6) /* Endian selection */
1.2330 +#define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */
1.2331 +#define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */
1.2332 +#define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */
1.2333 +#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
1.2334 +#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
1.2335 + #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
1.2336 + #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
1.2337 + #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
1.2338 + #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
1.2339 + #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
1.2340 + #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
1.2341 +
1.2342 +/* LCD Status Register */
1.2343 +#define LCD_STATE_QD (1 << 7) /* Quick Disable Done */
1.2344 +#define LCD_STATE_EOF (1 << 5) /* EOF Flag */
1.2345 +#define LCD_STATE_SOF (1 << 4) /* SOF Flag */
1.2346 +#define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */
1.2347 +#define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */
1.2348 +#define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */
1.2349 +#define LCD_STATE_LDD (1 << 0) /* LCD Disabled */
1.2350 +
1.2351 +/* DMA Command Register */
1.2352 +#define LCD_CMD_SOFINT (1 << 31)
1.2353 +#define LCD_CMD_EOFINT (1 << 30)
1.2354 +#define LCD_CMD_PAL (1 << 28)
1.2355 +#define LCD_CMD_LEN_BIT 0
1.2356 +#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT)
1.2357 +
1.2358 +
1.2359 +/*************************************************************************
1.2360 + * USB Device
1.2361 + *************************************************************************/
1.2362 +#define USB_BASE UDC_BASE
1.2363 +
1.2364 +#define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */
1.2365 +#define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */
1.2366 +#define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */
1.2367 +#define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */
1.2368 +#define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */
1.2369 +#define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */
1.2370 +#define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */
1.2371 +#define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */
1.2372 +#define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */
1.2373 +#define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */
1.2374 +#define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */
1.2375 +
1.2376 +#define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */
1.2377 +#define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */
1.2378 +#define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */
1.2379 +#define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */
1.2380 +#define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */
1.2381 +#define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */
1.2382 +#define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */
1.2383 +#define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */
1.2384 +
1.2385 +#define USB_FIFO_EP0 (USB_BASE + 0x20)
1.2386 +#define USB_FIFO_EP1 (USB_BASE + 0x24)
1.2387 +#define USB_FIFO_EP2 (USB_BASE + 0x28)
1.2388 +
1.2389 +#define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */
1.2390 +#define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */
1.2391 +
1.2392 +#define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */
1.2393 +#define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */
1.2394 +#define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */
1.2395 +#define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */
1.2396 +#define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */
1.2397 +#define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */
1.2398 +#define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */
1.2399 +
1.2400 +
1.2401 +/* Power register bit masks */
1.2402 +#define USB_POWER_SUSPENDM 0x01
1.2403 +#define USB_POWER_RESUME 0x04
1.2404 +#define USB_POWER_HSMODE 0x10
1.2405 +#define USB_POWER_HSENAB 0x20
1.2406 +#define USB_POWER_SOFTCONN 0x40
1.2407 +
1.2408 +/* Interrupt register bit masks */
1.2409 +#define USB_INTR_SUSPEND 0x01
1.2410 +#define USB_INTR_RESUME 0x02
1.2411 +#define USB_INTR_RESET 0x04
1.2412 +
1.2413 +#define USB_INTR_EP0 0x0001
1.2414 +#define USB_INTR_INEP1 0x0002
1.2415 +#define USB_INTR_INEP2 0x0004
1.2416 +#define USB_INTR_OUTEP1 0x0002
1.2417 +
1.2418 +/* CSR0 bit masks */
1.2419 +#define USB_CSR0_OUTPKTRDY 0x01
1.2420 +#define USB_CSR0_INPKTRDY 0x02
1.2421 +#define USB_CSR0_SENTSTALL 0x04
1.2422 +#define USB_CSR0_DATAEND 0x08
1.2423 +#define USB_CSR0_SETUPEND 0x10
1.2424 +#define USB_CSR0_SENDSTALL 0x20
1.2425 +#define USB_CSR0_SVDOUTPKTRDY 0x40
1.2426 +#define USB_CSR0_SVDSETUPEND 0x80
1.2427 +
1.2428 +/* Endpoint CSR register bits */
1.2429 +#define USB_INCSRH_AUTOSET 0x80
1.2430 +#define USB_INCSRH_ISO 0x40
1.2431 +#define USB_INCSRH_MODE 0x20
1.2432 +#define USB_INCSRH_DMAREQENAB 0x10
1.2433 +#define USB_INCSRH_DMAREQMODE 0x04
1.2434 +#define USB_INCSR_CDT 0x40
1.2435 +#define USB_INCSR_SENTSTALL 0x20
1.2436 +#define USB_INCSR_SENDSTALL 0x10
1.2437 +#define USB_INCSR_FF 0x08
1.2438 +#define USB_INCSR_UNDERRUN 0x04
1.2439 +#define USB_INCSR_FFNOTEMPT 0x02
1.2440 +#define USB_INCSR_INPKTRDY 0x01
1.2441 +#define USB_OUTCSRH_AUTOCLR 0x80
1.2442 +#define USB_OUTCSRH_ISO 0x40
1.2443 +#define USB_OUTCSRH_DMAREQENAB 0x20
1.2444 +#define USB_OUTCSRH_DNYT 0x10
1.2445 +#define USB_OUTCSRH_DMAREQMODE 0x08
1.2446 +#define USB_OUTCSR_CDT 0x80
1.2447 +#define USB_OUTCSR_SENTSTALL 0x40
1.2448 +#define USB_OUTCSR_SENDSTALL 0x20
1.2449 +#define USB_OUTCSR_FF 0x10
1.2450 +#define USB_OUTCSR_DATAERR 0x08
1.2451 +#define USB_OUTCSR_OVERRUN 0x04
1.2452 +#define USB_OUTCSR_FFFULL 0x02
1.2453 +#define USB_OUTCSR_OUTPKTRDY 0x01
1.2454 +
1.2455 +/* Testmode register bits */
1.2456 +#define USB_TEST_SE0NAK 0x01
1.2457 +#define USB_TEST_J 0x02
1.2458 +#define USB_TEST_K 0x04
1.2459 +#define USB_TEST_PACKET 0x08
1.2460 +
1.2461 +/* DMA control bits */
1.2462 +#define USB_CNTL_ENA 0x01
1.2463 +#define USB_CNTL_DIR_IN 0x02
1.2464 +#define USB_CNTL_MODE_1 0x04
1.2465 +#define USB_CNTL_INTR_EN 0x08
1.2466 +#define USB_CNTL_EP(n) ((n) << 4)
1.2467 +#define USB_CNTL_BURST_0 (0 << 9)
1.2468 +#define USB_CNTL_BURST_4 (1 << 9)
1.2469 +#define USB_CNTL_BURST_8 (2 << 9)
1.2470 +#define USB_CNTL_BURST_16 (3 << 9)
1.2471 +
1.2472 +
1.2473 +/* Module Operation Definitions */
1.2474 +#ifndef __ASSEMBLY__
1.2475 +
1.2476 +/***************************************************************************
1.2477 + * GPIO
1.2478 + ***************************************************************************/
1.2479 +
1.2480 +//------------------------------------------------------
1.2481 +// GPIO Pins Description
1.2482 +//
1.2483 +// PORT 0:
1.2484 +//
1.2485 +// PIN/BIT N FUNC0 FUNC1
1.2486 +// 0 D0 -
1.2487 +// 1 D1 -
1.2488 +// 2 D2 -
1.2489 +// 3 D3 -
1.2490 +// 4 D4 -
1.2491 +// 5 D5 -
1.2492 +// 6 D6 -
1.2493 +// 7 D7 -
1.2494 +// 8 D8 -
1.2495 +// 9 D9 -
1.2496 +// 10 D10 -
1.2497 +// 11 D11 -
1.2498 +// 12 D12 -
1.2499 +// 13 D13 -
1.2500 +// 14 D14 -
1.2501 +// 15 D15 -
1.2502 +// 16 D16 -
1.2503 +// 17 D17 -
1.2504 +// 18 D18 -
1.2505 +// 19 D19 -
1.2506 +// 20 D20 -
1.2507 +// 21 D21 -
1.2508 +// 22 D22 -
1.2509 +// 23 D23 -
1.2510 +// 24 D24 -
1.2511 +// 25 D25 -
1.2512 +// 26 D26 -
1.2513 +// 27 D27 -
1.2514 +// 28 D28 -
1.2515 +// 29 D29 -
1.2516 +// 30 D30 -
1.2517 +// 31 D31 -
1.2518 +//
1.2519 +//------------------------------------------------------
1.2520 +// PORT 1:
1.2521 +//
1.2522 +// PIN/BIT N FUNC0 FUNC1
1.2523 +// 0 A0 -
1.2524 +// 1 A1 -
1.2525 +// 2 A2 -
1.2526 +// 3 A3 -
1.2527 +// 4 A4 -
1.2528 +// 5 A5 -
1.2529 +// 6 A6 -
1.2530 +// 7 A7 -
1.2531 +// 8 A8 -
1.2532 +// 9 A9 -
1.2533 +// 10 A10 -
1.2534 +// 11 A11 -
1.2535 +// 12 A12 -
1.2536 +// 13 A13 -
1.2537 +// 14 A14 -
1.2538 +// 15 A15/CL -
1.2539 +// 16 A16/AL -
1.2540 +// 17 LCD_CLS A21
1.2541 +// 18 LCD_SPL A22
1.2542 +// 19 DCS# -
1.2543 +// 20 RAS# -
1.2544 +// 21 CAS# -
1.2545 +// 22 RDWE#/BUFD# -
1.2546 +// 23 CKE -
1.2547 +// 24 CKO -
1.2548 +// 25 CS1# -
1.2549 +// 26 CS2# -
1.2550 +// 27 CS3# -
1.2551 +// 28 CS4# -
1.2552 +// 29 RD# -
1.2553 +// 30 WR# -
1.2554 +// 31 WE0# -
1.2555 +//
1.2556 +// Note: PIN15&16 are CL&AL when connecting to NAND flash.
1.2557 +//------------------------------------------------------
1.2558 +// PORT 2:
1.2559 +//
1.2560 +// PIN/BIT N FUNC0 FUNC1
1.2561 +// 0 LCD_D0 -
1.2562 +// 1 LCD_D1 -
1.2563 +// 2 LCD_D2 -
1.2564 +// 3 LCD_D3 -
1.2565 +// 4 LCD_D4 -
1.2566 +// 5 LCD_D5 -
1.2567 +// 6 LCD_D6 -
1.2568 +// 7 LCD_D7 -
1.2569 +// 8 LCD_D8 -
1.2570 +// 9 LCD_D9 -
1.2571 +// 10 LCD_D10 -
1.2572 +// 11 LCD_D11 -
1.2573 +// 12 LCD_D12 -
1.2574 +// 13 LCD_D13 -
1.2575 +// 14 LCD_D14 -
1.2576 +// 15 LCD_D15 -
1.2577 +// 16 LCD_D16 -
1.2578 +// 17 LCD_D17 -
1.2579 +// 18 LCD_PCLK -
1.2580 +// 19 LCD_HSYNC -
1.2581 +// 20 LCD_VSYNC -
1.2582 +// 21 LCD_DE -
1.2583 +// 22 LCD_PS A19
1.2584 +// 23 LCD_REV A20
1.2585 +// 24 WE1# -
1.2586 +// 25 WE2# -
1.2587 +// 26 WE3# -
1.2588 +// 27 WAIT# -
1.2589 +// 28 FRE# -
1.2590 +// 29 FWE# -
1.2591 +// 30(NOTE:FRB#) - -
1.2592 +// 31 - -
1.2593 +//
1.2594 +// NOTE(1): PIN30 is used for FRB# when connecting to NAND flash.
1.2595 +//------------------------------------------------------
1.2596 +// PORT 3:
1.2597 +//
1.2598 +// PIN/BIT N FUNC0 FUNC1
1.2599 +// 0 CIM_D0 -
1.2600 +// 1 CIM_D1 -
1.2601 +// 2 CIM_D2 -
1.2602 +// 3 CIM_D3 -
1.2603 +// 4 CIM_D4 -
1.2604 +// 5 CIM_D5 -
1.2605 +// 6 CIM_D6 -
1.2606 +// 7 CIM_D7 -
1.2607 +// 8 MSC_CMD -
1.2608 +// 9 MSC_CLK -
1.2609 +// 10 MSC_D0 -
1.2610 +// 11 MSC_D1 -
1.2611 +// 12 MSC_D2 -
1.2612 +// 13 MSC_D3 -
1.2613 +// 14 CIM_MCLK -
1.2614 +// 15 CIM_PCLK -
1.2615 +// 16 CIM_VSYNC -
1.2616 +// 17 CIM_HSYNC -
1.2617 +// 18 SSI_CLK SCLK_RSTN
1.2618 +// 19 SSI_CE0# BIT_CLK(AIC)
1.2619 +// 20 SSI_DT SDATA_OUT(AIC)
1.2620 +// 21 SSI_DR SDATA_IN(AIC)
1.2621 +// 22 SSI_CE1#&GPC SYNC(AIC)
1.2622 +// 23 PWM0 I2C_SDA
1.2623 +// 24 PWM1 I2C_SCK
1.2624 +// 25 PWM2 UART0_TxD
1.2625 +// 26 PWM3 UART0_RxD
1.2626 +// 27 PWM4 A17
1.2627 +// 28 PWM5 A18
1.2628 +// 29 - -
1.2629 +// 30 PWM6 UART0_CTS/UART1_RxD
1.2630 +// 31 PWM7 UART0_RTS/UART1_TxD
1.2631 +//
1.2632 +//////////////////////////////////////////////////////////
1.2633 +
1.2634 +/*
1.2635 + * p is the port number (0,1,2,3)
1.2636 + * o is the pin offset (0-31) inside the port
1.2637 + * n is the absolute number of a pin (0-127), regardless of the port
1.2638 + */
1.2639 +
1.2640 +//-------------------------------------------
1.2641 +// Function Pins Mode
1.2642 +
1.2643 +#define __gpio_as_func0(n) \
1.2644 +do { \
1.2645 + unsigned int p, o; \
1.2646 + p = (n) / 32; \
1.2647 + o = (n) % 32; \
1.2648 + REG_GPIO_PXFUNS(p) = (1 << o); \
1.2649 + REG_GPIO_PXSELC(p) = (1 << o); \
1.2650 +} while (0)
1.2651 +
1.2652 +#define __gpio_as_func1(n) \
1.2653 +do { \
1.2654 + unsigned int p, o; \
1.2655 + p = (n) / 32; \
1.2656 + o = (n) % 32; \
1.2657 + REG_GPIO_PXFUNS(p) = (1 << o); \
1.2658 + REG_GPIO_PXSELS(p) = (1 << o); \
1.2659 +} while (0)
1.2660 +
1.2661 +/*
1.2662 + * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
1.2663 + * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
1.2664 + */
1.2665 +#define __gpio_as_sdram_32bit() \
1.2666 +do { \
1.2667 + REG_GPIO_PXFUNS(0) = 0xffffffff; \
1.2668 + REG_GPIO_PXSELC(0) = 0xffffffff; \
1.2669 + REG_GPIO_PXPES(0) = 0xffffffff; \
1.2670 + REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
1.2671 + REG_GPIO_PXSELC(1) = 0x81f9ffff; \
1.2672 + REG_GPIO_PXPES(1) = 0x81f9ffff; \
1.2673 + REG_GPIO_PXFUNS(2) = 0x07000000; \
1.2674 + REG_GPIO_PXSELC(2) = 0x07000000; \
1.2675 + REG_GPIO_PXPES(2) = 0x07000000; \
1.2676 +} while (0)
1.2677 +
1.2678 +/*
1.2679 + * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
1.2680 + * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
1.2681 + */
1.2682 +#define __gpio_as_sdram_16bit() \
1.2683 +do { \
1.2684 + REG_GPIO_PXFUNS(0) = 0x5442bfaa; \
1.2685 + REG_GPIO_PXSELC(0) = 0x5442bfaa; \
1.2686 + REG_GPIO_PXPES(0) = 0x5442bfaa; \
1.2687 + REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
1.2688 + REG_GPIO_PXSELC(1) = 0x81f9ffff; \
1.2689 + REG_GPIO_PXPES(1) = 0x81f9ffff; \
1.2690 + REG_GPIO_PXFUNS(2) = 0x01000000; \
1.2691 + REG_GPIO_PXSELC(2) = 0x01000000; \
1.2692 + REG_GPIO_PXPES(2) = 0x01000000; \
1.2693 +} while (0)
1.2694 +
1.2695 +/*
1.2696 + * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD#
1.2697 + */
1.2698 +#define __gpio_as_nand() \
1.2699 +do { \
1.2700 + REG_GPIO_PXFUNS(1) = 0x02018000; \
1.2701 + REG_GPIO_PXSELC(1) = 0x02018000; \
1.2702 + REG_GPIO_PXPES(1) = 0x02018000; \
1.2703 + REG_GPIO_PXFUNS(2) = 0x30000000; \
1.2704 + REG_GPIO_PXSELC(2) = 0x30000000; \
1.2705 + REG_GPIO_PXPES(2) = 0x30000000; \
1.2706 + REG_GPIO_PXFUNC(2) = 0x40000000; \
1.2707 + REG_GPIO_PXSELC(2) = 0x40000000; \
1.2708 + REG_GPIO_PXDIRC(2) = 0x40000000; \
1.2709 + REG_GPIO_PXPES(2) = 0x40000000; \
1.2710 + REG_GPIO_PXFUNS(1) = 0x00400000; \
1.2711 + REG_GPIO_PXSELC(1) = 0x00400000; \
1.2712 +} while (0)
1.2713 +
1.2714 +/*
1.2715 + * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7
1.2716 + */
1.2717 +#define __gpio_as_nor_8bit() \
1.2718 +do { \
1.2719 + REG_GPIO_PXFUNS(0) = 0x000000ff; \
1.2720 + REG_GPIO_PXSELC(0) = 0x000000ff; \
1.2721 + REG_GPIO_PXPES(0) = 0x000000ff; \
1.2722 + REG_GPIO_PXFUNS(1) = 0x7041ffff; \
1.2723 + REG_GPIO_PXSELC(1) = 0x7041ffff; \
1.2724 + REG_GPIO_PXPES(1) = 0x7041ffff; \
1.2725 + REG_GPIO_PXFUNS(1) = 0x00060000; \
1.2726 + REG_GPIO_PXSELS(1) = 0x00060000; \
1.2727 + REG_GPIO_PXPES(1) = 0x00060000; \
1.2728 + REG_GPIO_PXFUNS(2) = 0x08000000; \
1.2729 + REG_GPIO_PXSELC(2) = 0x08000000; \
1.2730 + REG_GPIO_PXPES(2) = 0x08000000; \
1.2731 + REG_GPIO_PXFUNS(2) = 0x00c00000; \
1.2732 + REG_GPIO_PXSELS(2) = 0x00c00000; \
1.2733 + REG_GPIO_PXPES(2) = 0x00c00000; \
1.2734 + REG_GPIO_PXFUNS(3) = 0x18000000; \
1.2735 + REG_GPIO_PXSELS(3) = 0x18000000; \
1.2736 + REG_GPIO_PXPES(3) = 0x18000000; \
1.2737 +} while (0)
1.2738 +
1.2739 +/*
1.2740 + * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15
1.2741 + */
1.2742 +#define __gpio_as_nor_16bit() \
1.2743 +do { \
1.2744 + REG_GPIO_PXFUNS(0) = 0x0000ffff; \
1.2745 + REG_GPIO_PXSELC(0) = 0x0000ffff; \
1.2746 + REG_GPIO_PXPES(0) = 0x0000ffff; \
1.2747 + REG_GPIO_PXFUNS(1) = 0x7041ffff; \
1.2748 + REG_GPIO_PXSELC(1) = 0x7041ffff; \
1.2749 + REG_GPIO_PXPES(1) = 0x7041ffff; \
1.2750 + REG_GPIO_PXFUNS(1) = 0x00060000; \
1.2751 + REG_GPIO_PXSELS(1) = 0x00060000; \
1.2752 + REG_GPIO_PXPES(1) = 0x00060000; \
1.2753 + REG_GPIO_PXFUNS(2) = 0x08000000; \
1.2754 + REG_GPIO_PXSELC(2) = 0x08000000; \
1.2755 + REG_GPIO_PXPES(2) = 0x08000000; \
1.2756 + REG_GPIO_PXFUNS(2) = 0x00c00000; \
1.2757 + REG_GPIO_PXSELS(2) = 0x00c00000; \
1.2758 + REG_GPIO_PXPES(2) = 0x00c00000; \
1.2759 + REG_GPIO_PXFUNS(3) = 0x18000000; \
1.2760 + REG_GPIO_PXSELS(3) = 0x18000000; \
1.2761 + REG_GPIO_PXPES(3) = 0x18000000; \
1.2762 +} while (0)
1.2763 +
1.2764 +/*
1.2765 + * UART0_TxD, UART_RxD0
1.2766 + */
1.2767 +#define __gpio_as_uart0() \
1.2768 +do { \
1.2769 + REG_GPIO_PXFUNS(3) = 0x06000000; \
1.2770 + REG_GPIO_PXSELS(3) = 0x06000000; \
1.2771 + REG_GPIO_PXPES(3) = 0x06000000; \
1.2772 +} while (0)
1.2773 +
1.2774 +/*
1.2775 + * UART0_CTS, UART0_RTS
1.2776 + */
1.2777 +#define __gpio_as_ctsrts() \
1.2778 +do { \
1.2779 + REG_GPIO_PXFUNS(3) = 0xc0000000; \
1.2780 + REG_GPIO_PXSELS(3) = 0xc0000000; \
1.2781 + REG_GPIO_PXTRGC(3) = 0xc0000000; \
1.2782 + REG_GPIO_PXPES(3) = 0xc0000000; \
1.2783 +} while (0)
1.2784 +
1.2785 +/*
1.2786 + * UART1_TxD, UART1_RxD1
1.2787 + */
1.2788 +#define __gpio_as_uart1() \
1.2789 +do { \
1.2790 + REG_GPIO_PXFUNS(3) = 0xc0000000; \
1.2791 + REG_GPIO_PXSELC(3) = 0xc0000000; \
1.2792 + REG_GPIO_PXTRGS(3) = 0xc0000000; \
1.2793 + REG_GPIO_PXPES(3) = 0xc0000000; \
1.2794 +} while (0)
1.2795 +
1.2796 +/*
1.2797 + * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
1.2798 + */
1.2799 +#define __gpio_as_lcd_16bit() \
1.2800 +do { \
1.2801 + REG_GPIO_PXFUNS(2) = 0x003cffff; \
1.2802 + REG_GPIO_PXSELC(2) = 0x003cffff; \
1.2803 + REG_GPIO_PXPES(2) = 0x003cffff; \
1.2804 +} while (0)
1.2805 +
1.2806 +/*
1.2807 + * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
1.2808 + */
1.2809 +#define __gpio_as_lcd_18bit() \
1.2810 +do { \
1.2811 + REG_GPIO_PXFUNS(2) = 0x003fffff; \
1.2812 + REG_GPIO_PXSELC(2) = 0x003fffff; \
1.2813 + REG_GPIO_PXPES(2) = 0x003fffff; \
1.2814 +} while (0)
1.2815 +
1.2816 +/*
1.2817 + * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC
1.2818 + */
1.2819 +#define __gpio_as_cim() \
1.2820 +do { \
1.2821 + REG_GPIO_PXFUNS(3) = 0x0003c0ff; \
1.2822 + REG_GPIO_PXSELC(3) = 0x0003c0ff; \
1.2823 + REG_GPIO_PXPES(3) = 0x0003c0ff; \
1.2824 +} while (0)
1.2825 +
1.2826 +/*
1.2827 + * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET
1.2828 + */
1.2829 +#define __gpio_as_aic() \
1.2830 +do { \
1.2831 + REG_GPIO_PXFUNS(3) = 0x007c0000; \
1.2832 + REG_GPIO_PXSELS(3) = 0x007c0000; \
1.2833 + REG_GPIO_PXPES(3) = 0x007c0000; \
1.2834 +} while (0)
1.2835 +
1.2836 +/*
1.2837 + * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3
1.2838 + */
1.2839 +#define __gpio_as_msc() \
1.2840 +do { \
1.2841 + REG_GPIO_PXFUNS(3) = 0x00003f00; \
1.2842 + REG_GPIO_PXSELC(3) = 0x00003f00; \
1.2843 + REG_GPIO_PXPES(3) = 0x00003f00; \
1.2844 +} while (0)
1.2845 +
1.2846 +/*
1.2847 + * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR
1.2848 + */
1.2849 +#define __gpio_as_ssi() \
1.2850 +do { \
1.2851 + REG_GPIO_PXFUNS(3) = 0x003c0000; \
1.2852 + REG_GPIO_PXSELC(3) = 0x003c0000; \
1.2853 + REG_GPIO_PXPES(3) = 0x003c0000; \
1.2854 +} while (0)
1.2855 +
1.2856 +/*
1.2857 + * I2C_SCK, I2C_SDA
1.2858 + */
1.2859 +#define __gpio_as_i2c() \
1.2860 +do { \
1.2861 + REG_GPIO_PXFUNS(3) = 0x01800000; \
1.2862 + REG_GPIO_PXSELS(3) = 0x01800000; \
1.2863 + REG_GPIO_PXPES(3) = 0x01800000; \
1.2864 +} while (0)
1.2865 +
1.2866 +/*
1.2867 + * PWM0
1.2868 + */
1.2869 +#define __gpio_as_pwm0() \
1.2870 +do { \
1.2871 + REG_GPIO_PXFUNS(3) = 0x00800000; \
1.2872 + REG_GPIO_PXSELC(3) = 0x00800000; \
1.2873 + REG_GPIO_PXPES(3) = 0x00800000; \
1.2874 +} while (0)
1.2875 +
1.2876 +/*
1.2877 + * PWM1
1.2878 + */
1.2879 +#define __gpio_as_pwm1() \
1.2880 +do { \
1.2881 + REG_GPIO_PXFUNS(3) = 0x01000000; \
1.2882 + REG_GPIO_PXSELC(3) = 0x01000000; \
1.2883 + REG_GPIO_PXPES(3) = 0x01000000; \
1.2884 +} while (0)
1.2885 +
1.2886 +/*
1.2887 + * PWM2
1.2888 + */
1.2889 +#define __gpio_as_pwm2() \
1.2890 +do { \
1.2891 + REG_GPIO_PXFUNS(3) = 0x02000000; \
1.2892 + REG_GPIO_PXSELC(3) = 0x02000000; \
1.2893 + REG_GPIO_PXPES(3) = 0x02000000; \
1.2894 +} while (0)
1.2895 +
1.2896 +/*
1.2897 + * PWM3
1.2898 + */
1.2899 +#define __gpio_as_pwm3() \
1.2900 +do { \
1.2901 + REG_GPIO_PXFUNS(3) = 0x04000000; \
1.2902 + REG_GPIO_PXSELC(3) = 0x04000000; \
1.2903 + REG_GPIO_PXPES(3) = 0x04000000; \
1.2904 +} while (0)
1.2905 +
1.2906 +/*
1.2907 + * PWM4
1.2908 + */
1.2909 +#define __gpio_as_pwm4() \
1.2910 +do { \
1.2911 + REG_GPIO_PXFUNS(3) = 0x08000000; \
1.2912 + REG_GPIO_PXSELC(3) = 0x08000000; \
1.2913 + REG_GPIO_PXPES(3) = 0x08000000; \
1.2914 +} while (0)
1.2915 +
1.2916 +/*
1.2917 + * PWM5
1.2918 + */
1.2919 +#define __gpio_as_pwm5() \
1.2920 +do { \
1.2921 + REG_GPIO_PXFUNS(3) = 0x10000000; \
1.2922 + REG_GPIO_PXSELC(3) = 0x10000000; \
1.2923 + REG_GPIO_PXPES(3) = 0x10000000; \
1.2924 +} while (0)
1.2925 +
1.2926 +/*
1.2927 + * PWM6
1.2928 + */
1.2929 +#define __gpio_as_pwm6() \
1.2930 +do { \
1.2931 + REG_GPIO_PXFUNS(3) = 0x40000000; \
1.2932 + REG_GPIO_PXSELC(3) = 0x40000000; \
1.2933 + REG_GPIO_PXPES(3) = 0x40000000; \
1.2934 +} while (0)
1.2935 +
1.2936 +/*
1.2937 + * PWM7
1.2938 + */
1.2939 +#define __gpio_as_pwm7() \
1.2940 +do { \
1.2941 + REG_GPIO_PXFUNS(3) = 0x80000000; \
1.2942 + REG_GPIO_PXSELC(3) = 0x80000000; \
1.2943 + REG_GPIO_PXPES(3) = 0x80000000; \
1.2944 +} while (0)
1.2945 +
1.2946 +/*
1.2947 + * n = 0 ~ 7
1.2948 + */
1.2949 +#define __gpio_as_pwm(n) __gpio_as_pwm##n()
1.2950 +
1.2951 +//-------------------------------------------
1.2952 +// GPIO or Interrupt Mode
1.2953 +
1.2954 +#define __gpio_get_port(p) (REG_GPIO_PXPIN(p))
1.2955 +
1.2956 +#define __gpio_port_as_output(p, o) \
1.2957 +do { \
1.2958 + REG_GPIO_PXFUNC(p) = (1 << (o)); \
1.2959 + REG_GPIO_PXSELC(p) = (1 << (o)); \
1.2960 + REG_GPIO_PXDIRS(p) = (1 << (o)); \
1.2961 +} while (0)
1.2962 +
1.2963 +#define __gpio_port_as_input(p, o) \
1.2964 +do { \
1.2965 + REG_GPIO_PXFUNC(p) = (1 << (o)); \
1.2966 + REG_GPIO_PXSELC(p) = (1 << (o)); \
1.2967 + REG_GPIO_PXDIRC(p) = (1 << (o)); \
1.2968 +} while (0)
1.2969 +
1.2970 +#define __gpio_as_output(n) \
1.2971 +do { \
1.2972 + unsigned int p, o; \
1.2973 + p = (n) / 32; \
1.2974 + o = (n) % 32; \
1.2975 + __gpio_port_as_output(p, o); \
1.2976 +} while (0)
1.2977 +
1.2978 +#define __gpio_as_input(n) \
1.2979 +do { \
1.2980 + unsigned int p, o; \
1.2981 + p = (n) / 32; \
1.2982 + o = (n) % 32; \
1.2983 + __gpio_port_as_input(p, o); \
1.2984 +} while (0)
1.2985 +
1.2986 +#define __gpio_set_pin(n) \
1.2987 +do { \
1.2988 + unsigned int p, o; \
1.2989 + p = (n) / 32; \
1.2990 + o = (n) % 32; \
1.2991 + REG_GPIO_PXDATS(p) = (1 << o); \
1.2992 +} while (0)
1.2993 +
1.2994 +#define __gpio_clear_pin(n) \
1.2995 +do { \
1.2996 + unsigned int p, o; \
1.2997 + p = (n) / 32; \
1.2998 + o = (n) % 32; \
1.2999 + REG_GPIO_PXDATC(p) = (1 << o); \
1.3000 +} while (0)
1.3001 +
1.3002 +#define __gpio_get_pin(n) \
1.3003 +({ \
1.3004 + unsigned int p, o, v; \
1.3005 + p = (n) / 32; \
1.3006 + o = (n) % 32; \
1.3007 + if (__gpio_get_port(p) & (1 << o)) \
1.3008 + v = 1; \
1.3009 + else \
1.3010 + v = 0; \
1.3011 + v; \
1.3012 +})
1.3013 +
1.3014 +#define __gpio_as_irq_high_level(n) \
1.3015 +do { \
1.3016 + unsigned int p, o; \
1.3017 + p = (n) / 32; \
1.3018 + o = (n) % 32; \
1.3019 + REG_GPIO_PXIMS(p) = (1 << o); \
1.3020 + REG_GPIO_PXTRGC(p) = (1 << o); \
1.3021 + REG_GPIO_PXFUNC(p) = (1 << o); \
1.3022 + REG_GPIO_PXSELS(p) = (1 << o); \
1.3023 + REG_GPIO_PXDIRS(p) = (1 << o); \
1.3024 + REG_GPIO_PXFLGC(p) = (1 << o); \
1.3025 + REG_GPIO_PXIMC(p) = (1 << o); \
1.3026 +} while (0)
1.3027 +
1.3028 +#define __gpio_as_irq_low_level(n) \
1.3029 +do { \
1.3030 + unsigned int p, o; \
1.3031 + p = (n) / 32; \
1.3032 + o = (n) % 32; \
1.3033 + REG_GPIO_PXIMS(p) = (1 << o); \
1.3034 + REG_GPIO_PXTRGC(p) = (1 << o); \
1.3035 + REG_GPIO_PXFUNC(p) = (1 << o); \
1.3036 + REG_GPIO_PXSELS(p) = (1 << o); \
1.3037 + REG_GPIO_PXDIRC(p) = (1 << o); \
1.3038 + REG_GPIO_PXFLGC(p) = (1 << o); \
1.3039 + REG_GPIO_PXIMC(p) = (1 << o); \
1.3040 +} while (0)
1.3041 +
1.3042 +#define __gpio_as_irq_rise_edge(n) \
1.3043 +do { \
1.3044 + unsigned int p, o; \
1.3045 + p = (n) / 32; \
1.3046 + o = (n) % 32; \
1.3047 + REG_GPIO_PXIMS(p) = (1 << o); \
1.3048 + REG_GPIO_PXTRGS(p) = (1 << o); \
1.3049 + REG_GPIO_PXFUNC(p) = (1 << o); \
1.3050 + REG_GPIO_PXSELS(p) = (1 << o); \
1.3051 + REG_GPIO_PXDIRS(p) = (1 << o); \
1.3052 + REG_GPIO_PXFLGC(p) = (1 << o); \
1.3053 + REG_GPIO_PXIMC(p) = (1 << o); \
1.3054 +} while (0)
1.3055 +
1.3056 +#define __gpio_as_irq_fall_edge(n) \
1.3057 +do { \
1.3058 + unsigned int p, o; \
1.3059 + p = (n) / 32; \
1.3060 + o = (n) % 32; \
1.3061 + REG_GPIO_PXIMS(p) = (1 << o); \
1.3062 + REG_GPIO_PXTRGS(p) = (1 << o); \
1.3063 + REG_GPIO_PXFUNC(p) = (1 << o); \
1.3064 + REG_GPIO_PXSELS(p) = (1 << o); \
1.3065 + REG_GPIO_PXDIRC(p) = (1 << o); \
1.3066 + REG_GPIO_PXFLGC(p) = (1 << o); \
1.3067 + REG_GPIO_PXIMC(p) = (1 << o); \
1.3068 +} while (0)
1.3069 +
1.3070 +#define __gpio_mask_irq(n) \
1.3071 +do { \
1.3072 + unsigned int p, o; \
1.3073 + p = (n) / 32; \
1.3074 + o = (n) % 32; \
1.3075 + REG_GPIO_PXIMS(p) = (1 << o); \
1.3076 +} while (0)
1.3077 +
1.3078 +#define __gpio_unmask_irq(n) \
1.3079 +do { \
1.3080 + unsigned int p, o; \
1.3081 + p = (n) / 32; \
1.3082 + o = (n) % 32; \
1.3083 + REG_GPIO_PXIMC(p) = (1 << o); \
1.3084 +} while (0)
1.3085 +
1.3086 +#define __gpio_ack_irq(n) \
1.3087 +do { \
1.3088 + unsigned int p, o; \
1.3089 + p = (n) / 32; \
1.3090 + o = (n) % 32; \
1.3091 + REG_GPIO_PXFLGC(p) = (1 << o); \
1.3092 +} while (0)
1.3093 +
1.3094 +#define __gpio_get_irq() \
1.3095 +({ \
1.3096 + unsigned int p, i, tmp, v = 0; \
1.3097 + for (p = 3; p >= 0; p--) { \
1.3098 + tmp = REG_GPIO_PXFLG(p); \
1.3099 + for (i = 0; i < 32; i++) \
1.3100 + if (tmp & (1 << i)) \
1.3101 + v = (32*p + i); \
1.3102 + } \
1.3103 + v; \
1.3104 +})
1.3105 +
1.3106 +#define __gpio_group_irq(n) \
1.3107 +({ \
1.3108 + register int tmp, i; \
1.3109 + tmp = REG_GPIO_PXFLG((n)); \
1.3110 + for (i=31;i>=0;i--) \
1.3111 + if (tmp & (1 << i)) \
1.3112 + break; \
1.3113 + i; \
1.3114 +})
1.3115 +
1.3116 +#define __gpio_enable_pull(n) \
1.3117 +do { \
1.3118 + unsigned int p, o; \
1.3119 + p = (n) / 32; \
1.3120 + o = (n) % 32; \
1.3121 + REG_GPIO_PXPEC(p) = (1 << o); \
1.3122 +} while (0)
1.3123 +
1.3124 +#define __gpio_disable_pull(n) \
1.3125 +do { \
1.3126 + unsigned int p, o; \
1.3127 + p = (n) / 32; \
1.3128 + o = (n) % 32; \
1.3129 + REG_GPIO_PXPES(p) = (1 << o); \
1.3130 +} while (0)
1.3131 +
1.3132 +
1.3133 +/***************************************************************************
1.3134 + * CPM
1.3135 + ***************************************************************************/
1.3136 +#define __cpm_get_pllm() \
1.3137 + ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
1.3138 +#define __cpm_get_plln() \
1.3139 + ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
1.3140 +#define __cpm_get_pllod() \
1.3141 + ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
1.3142 +
1.3143 +#define __cpm_get_cdiv() \
1.3144 + ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
1.3145 +#define __cpm_get_hdiv() \
1.3146 + ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
1.3147 +#define __cpm_get_pdiv() \
1.3148 + ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
1.3149 +#define __cpm_get_mdiv() \
1.3150 + ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
1.3151 +#define __cpm_get_ldiv() \
1.3152 + ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT)
1.3153 +#define __cpm_get_udiv() \
1.3154 + ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT)
1.3155 +#define __cpm_get_i2sdiv() \
1.3156 + ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
1.3157 +#define __cpm_get_pixdiv() \
1.3158 + ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
1.3159 +#define __cpm_get_mscdiv() \
1.3160 + ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
1.3161 +
1.3162 +#define __cpm_set_cdiv(v) \
1.3163 + (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
1.3164 +#define __cpm_set_hdiv(v) \
1.3165 + (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
1.3166 +#define __cpm_set_pdiv(v) \
1.3167 + (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
1.3168 +#define __cpm_set_mdiv(v) \
1.3169 + (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
1.3170 +#define __cpm_set_ldiv(v) \
1.3171 + (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
1.3172 +#define __cpm_set_udiv(v) \
1.3173 + (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
1.3174 +#define __cpm_set_i2sdiv(v) \
1.3175 + (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
1.3176 +#define __cpm_set_pixdiv(v) \
1.3177 + (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
1.3178 +#define __cpm_set_mscdiv(v) \
1.3179 + (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
1.3180 +
1.3181 +#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS)
1.3182 +#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS)
1.3183 +#define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN)
1.3184 +#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
1.3185 +#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
1.3186 +#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE)
1.3187 +#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS)
1.3188 +#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
1.3189 +
1.3190 +#define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS)
1.3191 +#define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP)
1.3192 +#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
1.3193 +
1.3194 +#define __cpm_get_cclk_doze_duty() \
1.3195 + ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
1.3196 +#define __cpm_set_cclk_doze_duty(v) \
1.3197 + (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
1.3198 +
1.3199 +#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
1.3200 +#define __cpm_idle_mode() \
1.3201 + (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
1.3202 +#define __cpm_sleep_mode() \
1.3203 + (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
1.3204 +
1.3205 +#define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff)
1.3206 +#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1)
1.3207 +#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC)
1.3208 +#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU)
1.3209 +#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC)
1.3210 +#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC)
1.3211 +#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
1.3212 +#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM)
1.3213 +#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC)
1.3214 +#define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC)
1.3215 +#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1)
1.3216 +#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2)
1.3217 +#define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI)
1.3218 +#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C)
1.3219 +#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC)
1.3220 +#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU)
1.3221 +#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0)
1.3222 +
1.3223 +#define __cpm_start_all() (REG_CPM_CLKGR = 0x0)
1.3224 +#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1)
1.3225 +#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC)
1.3226 +#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU)
1.3227 +#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC)
1.3228 +#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC)
1.3229 +#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
1.3230 +#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM)
1.3231 +#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC)
1.3232 +#define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC)
1.3233 +#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1)
1.3234 +#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2)
1.3235 +#define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI)
1.3236 +#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C)
1.3237 +#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC)
1.3238 +#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
1.3239 +#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0)
1.3240 +
1.3241 +#define __cpm_get_o1st() \
1.3242 + ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT)
1.3243 +#define __cpm_set_o1st(v) \
1.3244 + (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT)))
1.3245 +#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND)
1.3246 +#define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE)
1.3247 +
1.3248 +
1.3249 +#ifdef CFG_EXTAL
1.3250 +#define JZ_EXTAL CFG_EXTAL
1.3251 +#else
1.3252 +#define JZ_EXTAL 3686400
1.3253 +#endif
1.3254 +#define JZ_EXTAL2 32768 /* RTC clock */
1.3255 +
1.3256 +/* PLL output frequency */
1.3257 +static __inline__ unsigned int __cpm_get_pllout(void)
1.3258 +{
1.3259 + unsigned long m, n, no, pllout;
1.3260 + unsigned long cppcr = REG_CPM_CPPCR;
1.3261 + unsigned long od[4] = {1, 2, 2, 4};
1.3262 + if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
1.3263 + m = __cpm_get_pllm() + 2;
1.3264 + n = __cpm_get_plln() + 2;
1.3265 + no = od[__cpm_get_pllod()];
1.3266 + pllout = ((JZ_EXTAL) / (n * no)) * m;
1.3267 + } else
1.3268 + pllout = JZ_EXTAL;
1.3269 + return pllout;
1.3270 +}
1.3271 +
1.3272 +/* PLL output frequency for MSC/I2S/LCD/USB */
1.3273 +static __inline__ unsigned int __cpm_get_pllout2(void)
1.3274 +{
1.3275 + if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
1.3276 + return __cpm_get_pllout();
1.3277 + else
1.3278 + return __cpm_get_pllout()/2;
1.3279 +}
1.3280 +
1.3281 +/* CPU core clock */
1.3282 +static __inline__ unsigned int __cpm_get_cclk(void)
1.3283 +{
1.3284 + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.3285 +
1.3286 + return __cpm_get_pllout() / div[__cpm_get_cdiv()];
1.3287 +}
1.3288 +
1.3289 +/* AHB system bus clock */
1.3290 +static __inline__ unsigned int __cpm_get_hclk(void)
1.3291 +{
1.3292 + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.3293 +
1.3294 + return __cpm_get_pllout() / div[__cpm_get_hdiv()];
1.3295 +}
1.3296 +
1.3297 +/* Memory bus clock */
1.3298 +static __inline__ unsigned int __cpm_get_mclk(void)
1.3299 +{
1.3300 + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.3301 +
1.3302 + return __cpm_get_pllout() / div[__cpm_get_mdiv()];
1.3303 +}
1.3304 +
1.3305 +/* APB peripheral bus clock */
1.3306 +static __inline__ unsigned int __cpm_get_pclk(void)
1.3307 +{
1.3308 + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.3309 +
1.3310 + return __cpm_get_pllout() / div[__cpm_get_pdiv()];
1.3311 +}
1.3312 +
1.3313 +/* LCDC module clock */
1.3314 +static __inline__ unsigned int __cpm_get_lcdclk(void)
1.3315 +{
1.3316 + return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1);
1.3317 +}
1.3318 +
1.3319 +/* LCD pixel clock */
1.3320 +static __inline__ unsigned int __cpm_get_pixclk(void)
1.3321 +{
1.3322 + return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
1.3323 +}
1.3324 +
1.3325 +/* I2S clock */
1.3326 +static __inline__ unsigned int __cpm_get_i2sclk(void)
1.3327 +{
1.3328 + if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) {
1.3329 + return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
1.3330 + }
1.3331 + else {
1.3332 + return JZ_EXTAL;
1.3333 + }
1.3334 +}
1.3335 +
1.3336 +/* USB clock */
1.3337 +static __inline__ unsigned int __cpm_get_usbclk(void)
1.3338 +{
1.3339 + if (REG_CPM_CPCCR & CPM_CPCCR_UCS) {
1.3340 + return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
1.3341 + }
1.3342 + else {
1.3343 + return JZ_EXTAL;
1.3344 + }
1.3345 +}
1.3346 +
1.3347 +/* MSC clock */
1.3348 +static __inline__ unsigned int __cpm_get_mscclk(void)
1.3349 +{
1.3350 + return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1);
1.3351 +}
1.3352 +
1.3353 +/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
1.3354 +static __inline__ unsigned int __cpm_get_extalclk(void)
1.3355 +{
1.3356 + return JZ_EXTAL;
1.3357 +}
1.3358 +
1.3359 +/* RTC clock for CPM,INTC,RTC,TCU,WDT */
1.3360 +static __inline__ unsigned int __cpm_get_rtcclk(void)
1.3361 +{
1.3362 + return JZ_EXTAL2;
1.3363 +}
1.3364 +
1.3365 +/*
1.3366 + * Output 24MHz for SD and 16MHz for MMC.
1.3367 + */
1.3368 +static inline void __cpm_select_msc_clk(int sd)
1.3369 +{
1.3370 + unsigned int pllout2 = __cpm_get_pllout2();
1.3371 + unsigned int div = 0;
1.3372 +
1.3373 + if (sd) {
1.3374 + div = pllout2 / 24000000;
1.3375 + }
1.3376 + else {
1.3377 + div = pllout2 / 16000000;
1.3378 + }
1.3379 +
1.3380 + REG_CPM_MSCCDR = div - 1;
1.3381 +}
1.3382 +
1.3383 +/***************************************************************************
1.3384 + * TCU
1.3385 + ***************************************************************************/
1.3386 +// where 'n' is the TCU channel
1.3387 +#define __tcu_select_extalclk(n) \
1.3388 + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN)
1.3389 +#define __tcu_select_rtcclk(n) \
1.3390 + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN)
1.3391 +#define __tcu_select_pclk(n) \
1.3392 + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN)
1.3393 +
1.3394 +#define __tcu_select_clk_div1(n) \
1.3395 + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1)
1.3396 +#define __tcu_select_clk_div4(n) \
1.3397 + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4)
1.3398 +#define __tcu_select_clk_div16(n) \
1.3399 + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16)
1.3400 +#define __tcu_select_clk_div64(n) \
1.3401 + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64)
1.3402 +#define __tcu_select_clk_div256(n) \
1.3403 + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256)
1.3404 +#define __tcu_select_clk_div1024(n) \
1.3405 + (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024)
1.3406 +
1.3407 +#define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN )
1.3408 +#define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN )
1.3409 +
1.3410 +#define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH )
1.3411 +#define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH )
1.3412 +
1.3413 +#define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD )
1.3414 +#define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD )
1.3415 +
1.3416 +#define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) )
1.3417 +#define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) )
1.3418 +
1.3419 +#define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) )
1.3420 +#define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) )
1.3421 +#define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) )
1.3422 +#define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) )
1.3423 +#define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) )
1.3424 +#define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) )
1.3425 +#define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) )
1.3426 +#define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) )
1.3427 +#define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) )
1.3428 +#define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) )
1.3429 +
1.3430 +#define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC )
1.3431 +#define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) )
1.3432 +
1.3433 +#define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC )
1.3434 +#define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) )
1.3435 +
1.3436 +#define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC )
1.3437 +#define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) )
1.3438 +
1.3439 +#define __tcu_get_count(n) ( REG_TCU_TCNT((n)) )
1.3440 +#define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) )
1.3441 +#define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) )
1.3442 +#define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) )
1.3443 +
1.3444 +
1.3445 +/***************************************************************************
1.3446 + * WDT
1.3447 + ***************************************************************************/
1.3448 +#define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN )
1.3449 +#define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN )
1.3450 +#define __wdt_set_count(v) ( REG_WDT_TCNT = (v) )
1.3451 +#define __wdt_set_data(v) ( REG_WDT_TDR = (v) )
1.3452 +
1.3453 +#define __wdt_select_extalclk() \
1.3454 + (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN)
1.3455 +#define __wdt_select_rtcclk() \
1.3456 + (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN)
1.3457 +#define __wdt_select_pclk() \
1.3458 + (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN)
1.3459 +
1.3460 +#define __wdt_select_clk_div1() \
1.3461 + (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1)
1.3462 +#define __wdt_select_clk_div4() \
1.3463 + (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4)
1.3464 +#define __wdt_select_clk_div16() \
1.3465 + (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16)
1.3466 +#define __wdt_select_clk_div64() \
1.3467 + (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64)
1.3468 +#define __wdt_select_clk_div256() \
1.3469 + (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256)
1.3470 +#define __wdt_select_clk_div1024() \
1.3471 + (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024)
1.3472 +
1.3473 +
1.3474 +/***************************************************************************
1.3475 + * UART
1.3476 + ***************************************************************************/
1.3477 +
1.3478 +#define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE )
1.3479 +#define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE )
1.3480 +
1.3481 +#define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE )
1.3482 +#define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE )
1.3483 +
1.3484 +#define __uart_enable_receive_irq() \
1.3485 + ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )
1.3486 +#define __uart_disable_receive_irq() \
1.3487 + ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )
1.3488 +
1.3489 +#define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP )
1.3490 +#define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP )
1.3491 +
1.3492 +#define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 )
1.3493 +
1.3494 +#define __uart_set_baud(devclk, baud) \
1.3495 + do { \
1.3496 + REG8(UART0_LCR) |= UARTLCR_DLAB; \
1.3497 + REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \
1.3498 + REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \
1.3499 + REG8(UART0_LCR) &= ~UARTLCR_DLAB; \
1.3500 + } while (0)
1.3501 +
1.3502 +#define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 )
1.3503 +#define __uart_clear_errors() \
1.3504 + ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) )
1.3505 +
1.3506 +#define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 )
1.3507 +#define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 )
1.3508 +#define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) )
1.3509 +#define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
1.3510 +#define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
1.3511 +#define __uart_receive_char() REG8(UART0_RDR)
1.3512 +#define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )
1.3513 +#define __uart_enable_irda() \
1.3514 + /* Tx high pulse as 0, Rx low pulse as 0 */ \
1.3515 + ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )
1.3516 +
1.3517 +
1.3518 +/***************************************************************************
1.3519 + * DMAC
1.3520 + ***************************************************************************/
1.3521 +
1.3522 +/* n is the DMA channel (0 - 5) */
1.3523 +
1.3524 +#define __dmac_enable_module() \
1.3525 + ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR )
1.3526 +#define __dmac_disable_module() \
1.3527 + ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE )
1.3528 +
1.3529 +/* p=0,1,2,3 */
1.3530 +#define __dmac_set_priority(p) \
1.3531 +do { \
1.3532 + REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \
1.3533 + REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \
1.3534 +} while (0)
1.3535 +
1.3536 +#define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT )
1.3537 +#define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR )
1.3538 +
1.3539 +#define __dmac_enable_descriptor(n) \
1.3540 + ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
1.3541 +#define __dmac_disable_descriptor(n) \
1.3542 + ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
1.3543 +
1.3544 +#define __dmac_enable_channel(n) \
1.3545 + ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN )
1.3546 +#define __dmac_disable_channel(n) \
1.3547 + ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN )
1.3548 +#define __dmac_channel_enabled(n) \
1.3549 + ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )
1.3550 +
1.3551 +#define __dmac_channel_enable_irq(n) \
1.3552 + ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )
1.3553 +#define __dmac_channel_disable_irq(n) \
1.3554 + ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
1.3555 +
1.3556 +#define __dmac_channel_transmit_halt_detected(n) \
1.3557 + ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
1.3558 +#define __dmac_channel_transmit_end_detected(n) \
1.3559 + ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
1.3560 +#define __dmac_channel_address_error_detected(n) \
1.3561 + ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
1.3562 +#define __dmac_channel_count_terminated_detected(n) \
1.3563 + ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )
1.3564 +#define __dmac_channel_descriptor_invalid_detected(n) \
1.3565 + ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )
1.3566 +
1.3567 +#define __dmac_channel_clear_transmit_halt(n) \
1.3568 + ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT )
1.3569 +#define __dmac_channel_clear_transmit_end(n) \
1.3570 + ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
1.3571 +#define __dmac_channel_clear_address_error(n) \
1.3572 + ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR )
1.3573 +#define __dmac_channel_clear_count_terminated(n) \
1.3574 + ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
1.3575 +#define __dmac_channel_clear_descriptor_invalid(n) \
1.3576 + ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
1.3577 +
1.3578 +#define __dmac_channel_set_single_mode(n) \
1.3579 + ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM )
1.3580 +#define __dmac_channel_set_block_mode(n) \
1.3581 + ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM )
1.3582 +
1.3583 +#define __dmac_channel_set_transfer_unit_32bit(n) \
1.3584 +do { \
1.3585 + REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1.3586 + REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \
1.3587 +} while (0)
1.3588 +
1.3589 +#define __dmac_channel_set_transfer_unit_16bit(n) \
1.3590 +do { \
1.3591 + REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1.3592 + REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \
1.3593 +} while (0)
1.3594 +
1.3595 +#define __dmac_channel_set_transfer_unit_8bit(n) \
1.3596 +do { \
1.3597 + REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1.3598 + REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \
1.3599 +} while (0)
1.3600 +
1.3601 +#define __dmac_channel_set_transfer_unit_16byte(n) \
1.3602 +do { \
1.3603 + REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1.3604 + REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \
1.3605 +} while (0)
1.3606 +
1.3607 +#define __dmac_channel_set_transfer_unit_32byte(n) \
1.3608 +do { \
1.3609 + REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
1.3610 + REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \
1.3611 +} while (0)
1.3612 +
1.3613 +/* w=8,16,32 */
1.3614 +#define __dmac_channel_set_dest_port_width(n,w) \
1.3615 +do { \
1.3616 + REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \
1.3617 + REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \
1.3618 +} while (0)
1.3619 +
1.3620 +/* w=8,16,32 */
1.3621 +#define __dmac_channel_set_src_port_width(n,w) \
1.3622 +do { \
1.3623 + REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \
1.3624 + REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \
1.3625 +} while (0)
1.3626 +
1.3627 +/* v=0-15 */
1.3628 +#define __dmac_channel_set_rdil(n,v) \
1.3629 +do { \
1.3630 + REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \
1.3631 + REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \
1.3632 +} while (0)
1.3633 +
1.3634 +#define __dmac_channel_dest_addr_fixed(n) \
1.3635 + ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )
1.3636 +#define __dmac_channel_dest_addr_increment(n) \
1.3637 + ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )
1.3638 +
1.3639 +#define __dmac_channel_src_addr_fixed(n) \
1.3640 + ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )
1.3641 +#define __dmac_channel_src_addr_increment(n) \
1.3642 + ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )
1.3643 +
1.3644 +#define __dmac_channel_set_doorbell(n) \
1.3645 + ( REG_DMAC_DMADBSR = (1 << (n)) )
1.3646 +
1.3647 +#define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) )
1.3648 +#define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) )
1.3649 +
1.3650 +static __inline__ int __dmac_get_irq(void)
1.3651 +{
1.3652 + int i;
1.3653 + for (i = 0; i < MAX_DMA_NUM; i++)
1.3654 + if (__dmac_channel_irq_detected(i))
1.3655 + return i;
1.3656 + return -1;
1.3657 +}
1.3658 +
1.3659 +
1.3660 +/***************************************************************************
1.3661 + * AIC (AC'97 & I2S Controller)
1.3662 + ***************************************************************************/
1.3663 +
1.3664 +#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB )
1.3665 +#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB )
1.3666 +
1.3667 +#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL )
1.3668 +#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL )
1.3669 +
1.3670 +#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
1.3671 +#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
1.3672 +#define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST )
1.3673 +
1.3674 +#define __aic_reset() \
1.3675 +do { \
1.3676 + REG_AIC_FR |= AIC_FR_RST; \
1.3677 +} while(0)
1.3678 +
1.3679 +
1.3680 +#define __aic_set_transmit_trigger(n) \
1.3681 +do { \
1.3682 + REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \
1.3683 + REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \
1.3684 +} while(0)
1.3685 +
1.3686 +#define __aic_set_receive_trigger(n) \
1.3687 +do { \
1.3688 + REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \
1.3689 + REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \
1.3690 +} while(0)
1.3691 +
1.3692 +#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC )
1.3693 +#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC )
1.3694 +#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL )
1.3695 +#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL )
1.3696 +#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
1.3697 +#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
1.3698 +
1.3699 +#define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH )
1.3700 +#define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH )
1.3701 +
1.3702 +#define __aic_enable_transmit_intr() \
1.3703 + ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
1.3704 +#define __aic_disable_transmit_intr() \
1.3705 + ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
1.3706 +#define __aic_enable_receive_intr() \
1.3707 + ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
1.3708 +#define __aic_disable_receive_intr() \
1.3709 + ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
1.3710 +
1.3711 +#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS )
1.3712 +#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
1.3713 +#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS )
1.3714 +#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS )
1.3715 +
1.3716 +#define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S )
1.3717 +#define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S )
1.3718 +#define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW )
1.3719 +#define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW )
1.3720 +#define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU )
1.3721 +#define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU )
1.3722 +
1.3723 +#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3
1.3724 +#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4
1.3725 +#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6
1.3726 +#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7
1.3727 +#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8
1.3728 +#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9
1.3729 +
1.3730 +#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3
1.3731 +#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4
1.3732 +#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6
1.3733 +#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7
1.3734 +#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8
1.3735 +#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9
1.3736 +
1.3737 +#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
1.3738 +#define __ac97_set_xs_mono() \
1.3739 +do { \
1.3740 + REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
1.3741 + REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \
1.3742 +} while(0)
1.3743 +#define __ac97_set_xs_stereo() \
1.3744 +do { \
1.3745 + REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
1.3746 + REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \
1.3747 +} while(0)
1.3748 +
1.3749 +/* In fact, only stereo is support now. */
1.3750 +#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
1.3751 +#define __ac97_set_rs_mono() \
1.3752 +do { \
1.3753 + REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
1.3754 + REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \
1.3755 +} while(0)
1.3756 +#define __ac97_set_rs_stereo() \
1.3757 +do { \
1.3758 + REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
1.3759 + REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \
1.3760 +} while(0)
1.3761 +
1.3762 +#define __ac97_warm_reset_codec() \
1.3763 + do { \
1.3764 + REG_AIC_ACCR2 |= AIC_ACCR2_SA; \
1.3765 + REG_AIC_ACCR2 |= AIC_ACCR2_SS; \
1.3766 + udelay(2); \
1.3767 + REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \
1.3768 + REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \
1.3769 + } while (0)
1.3770 +
1.3771 +#define __ac97_cold_reset_codec() \
1.3772 + do { \
1.3773 + REG_AIC_ACCR2 |= AIC_ACCR2_SR; \
1.3774 + udelay(2); \
1.3775 + REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \
1.3776 + } while (0)
1.3777 +
1.3778 +/* n=8,16,18,20 */
1.3779 +#define __ac97_set_iass(n) \
1.3780 + ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
1.3781 +#define __ac97_set_oass(n) \
1.3782 + ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
1.3783 +
1.3784 +#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
1.3785 +#define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
1.3786 +
1.3787 +/* n=8,16,18,20,24 */
1.3788 +/*#define __i2s_set_sample_size(n) \
1.3789 + ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/
1.3790 +
1.3791 +#define __i2s_set_oss_sample_size(n) \
1.3792 + ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT )
1.3793 +#define __i2s_set_iss_sample_size(n) \
1.3794 + ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT )
1.3795 +
1.3796 +#define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
1.3797 +#define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
1.3798 +
1.3799 +#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS )
1.3800 +#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS )
1.3801 +#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
1.3802 +#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR )
1.3803 +
1.3804 +#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
1.3805 +
1.3806 +#define __aic_get_transmit_resident() \
1.3807 + ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT )
1.3808 +#define __aic_get_receive_count() \
1.3809 + ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT )
1.3810 +
1.3811 +#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT )
1.3812 +#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR )
1.3813 +#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO )
1.3814 +#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
1.3815 +#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY )
1.3816 +#define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR )
1.3817 +#define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )
1.3818 +
1.3819 +#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
1.3820 +
1.3821 +#define CODEC_READ_CMD (1 << 19)
1.3822 +#define CODEC_WRITE_CMD (0 << 19)
1.3823 +#define CODEC_REG_INDEX_BIT 12
1.3824 +#define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */
1.3825 +#define CODEC_REG_DATA_BIT 4
1.3826 +#define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */
1.3827 +
1.3828 +#define __ac97_out_rcmd_addr(reg) \
1.3829 +do { \
1.3830 + REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
1.3831 +} while (0)
1.3832 +
1.3833 +#define __ac97_out_wcmd_addr(reg) \
1.3834 +do { \
1.3835 + REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
1.3836 +} while (0)
1.3837 +
1.3838 +#define __ac97_out_data(value) \
1.3839 +do { \
1.3840 + REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \
1.3841 +} while (0)
1.3842 +
1.3843 +#define __ac97_in_data() \
1.3844 + ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT )
1.3845 +
1.3846 +#define __ac97_in_status_addr() \
1.3847 + ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT )
1.3848 +
1.3849 +#define __i2s_set_sample_rate(i2sclk, sync) \
1.3850 + ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
1.3851 +
1.3852 +#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) )
1.3853 +#define __aic_read_rfifo() ( REG_AIC_DR )
1.3854 +
1.3855 +#define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC )
1.3856 +#define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC )
1.3857 +
1.3858 +//
1.3859 +// Define next ops for AC97 compatible
1.3860 +//
1.3861 +
1.3862 +#define AC97_ACSR AIC_ACSR
1.3863 +
1.3864 +#define __ac97_enable() __aic_enable(); __aic_select_ac97()
1.3865 +#define __ac97_disable() __aic_disable()
1.3866 +#define __ac97_reset() __aic_reset()
1.3867 +
1.3868 +#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
1.3869 +#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n)
1.3870 +
1.3871 +#define __ac97_enable_record() __aic_enable_record()
1.3872 +#define __ac97_disable_record() __aic_disable_record()
1.3873 +#define __ac97_enable_replay() __aic_enable_replay()
1.3874 +#define __ac97_disable_replay() __aic_disable_replay()
1.3875 +#define __ac97_enable_loopback() __aic_enable_loopback()
1.3876 +#define __ac97_disable_loopback() __aic_disable_loopback()
1.3877 +
1.3878 +#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma()
1.3879 +#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma()
1.3880 +#define __ac97_enable_receive_dma() __aic_enable_receive_dma()
1.3881 +#define __ac97_disable_receive_dma() __aic_disable_receive_dma()
1.3882 +
1.3883 +#define __ac97_transmit_request() __aic_transmit_request()
1.3884 +#define __ac97_receive_request() __aic_receive_request()
1.3885 +#define __ac97_transmit_underrun() __aic_transmit_underrun()
1.3886 +#define __ac97_receive_overrun() __aic_receive_overrun()
1.3887 +
1.3888 +#define __ac97_clear_errors() __aic_clear_errors()
1.3889 +
1.3890 +#define __ac97_get_transmit_resident() __aic_get_transmit_resident()
1.3891 +#define __ac97_get_receive_count() __aic_get_receive_count()
1.3892 +
1.3893 +#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr()
1.3894 +#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr()
1.3895 +#define __ac97_enable_receive_intr() __aic_enable_receive_intr()
1.3896 +#define __ac97_disable_receive_intr() __aic_disable_receive_intr()
1.3897 +
1.3898 +#define __ac97_write_tfifo(v) __aic_write_tfifo(v)
1.3899 +#define __ac97_read_rfifo() __aic_read_rfifo()
1.3900 +
1.3901 +//
1.3902 +// Define next ops for I2S compatible
1.3903 +//
1.3904 +
1.3905 +#define I2S_ACSR AIC_I2SSR
1.3906 +
1.3907 +#define __i2s_enable() __aic_enable(); __aic_select_i2s()
1.3908 +#define __i2s_disable() __aic_disable()
1.3909 +#define __i2s_reset() __aic_reset()
1.3910 +
1.3911 +#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
1.3912 +#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n)
1.3913 +
1.3914 +#define __i2s_enable_record() __aic_enable_record()
1.3915 +#define __i2s_disable_record() __aic_disable_record()
1.3916 +#define __i2s_enable_replay() __aic_enable_replay()
1.3917 +#define __i2s_disable_replay() __aic_disable_replay()
1.3918 +#define __i2s_enable_loopback() __aic_enable_loopback()
1.3919 +#define __i2s_disable_loopback() __aic_disable_loopback()
1.3920 +
1.3921 +#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma()
1.3922 +#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma()
1.3923 +#define __i2s_enable_receive_dma() __aic_enable_receive_dma()
1.3924 +#define __i2s_disable_receive_dma() __aic_disable_receive_dma()
1.3925 +
1.3926 +#define __i2s_transmit_request() __aic_transmit_request()
1.3927 +#define __i2s_receive_request() __aic_receive_request()
1.3928 +#define __i2s_transmit_underrun() __aic_transmit_underrun()
1.3929 +#define __i2s_receive_overrun() __aic_receive_overrun()
1.3930 +
1.3931 +#define __i2s_clear_errors() __aic_clear_errors()
1.3932 +
1.3933 +#define __i2s_get_transmit_resident() __aic_get_transmit_resident()
1.3934 +#define __i2s_get_receive_count() __aic_get_receive_count()
1.3935 +
1.3936 +#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr()
1.3937 +#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr()
1.3938 +#define __i2s_enable_receive_intr() __aic_enable_receive_intr()
1.3939 +#define __i2s_disable_receive_intr() __aic_disable_receive_intr()
1.3940 +
1.3941 +#define __i2s_write_tfifo(v) __aic_write_tfifo(v)
1.3942 +#define __i2s_read_rfifo() __aic_read_rfifo()
1.3943 +
1.3944 +#define __i2s_reset_codec() \
1.3945 + do { \
1.3946 + } while (0)
1.3947 +
1.3948 +
1.3949 +/***************************************************************************
1.3950 + * ICDC
1.3951 + ***************************************************************************/
1.3952 +#define __i2s_internal_codec() __aic_internal_codec()
1.3953 +#define __i2s_external_codec() __aic_external_codec()
1.3954 +
1.3955 +/***************************************************************************
1.3956 + * INTC
1.3957 + ***************************************************************************/
1.3958 +#define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) )
1.3959 +#define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) )
1.3960 +#define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) )
1.3961 +
1.3962 +
1.3963 +/***************************************************************************
1.3964 + * I2C
1.3965 + ***************************************************************************/
1.3966 +
1.3967 +#define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE )
1.3968 +#define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE )
1.3969 +
1.3970 +#define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA )
1.3971 +#define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO )
1.3972 +#define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC )
1.3973 +#define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC )
1.3974 +
1.3975 +#define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF )
1.3976 +#define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF )
1.3977 +#define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF )
1.3978 +
1.3979 +#define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) )
1.3980 +#define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY )
1.3981 +#define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND )
1.3982 +
1.3983 +#define __i2c_set_clk(dev_clk, i2c_clk) \
1.3984 + ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )
1.3985 +
1.3986 +#define __i2c_read() ( REG_I2C_DR )
1.3987 +#define __i2c_write(val) ( REG_I2C_DR = (val) )
1.3988 +
1.3989 +
1.3990 +/***************************************************************************
1.3991 + * MSC
1.3992 + ***************************************************************************/
1.3993 +
1.3994 +#define __msc_start_op() \
1.3995 + ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )
1.3996 +
1.3997 +#define __msc_set_resto(to) ( REG_MSC_RESTO = to )
1.3998 +#define __msc_set_rdto(to) ( REG_MSC_RDTO = to )
1.3999 +#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd )
1.4000 +#define __msc_set_arg(arg) ( REG_MSC_ARG = arg )
1.4001 +#define __msc_set_nob(nob) ( REG_MSC_NOB = nob )
1.4002 +#define __msc_get_nob() ( REG_MSC_NOB )
1.4003 +#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len )
1.4004 +#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat )
1.4005 +#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT )
1.4006 +#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT )
1.4007 +
1.4008 +#define __msc_set_cmdat_bus_width1() \
1.4009 +do { \
1.4010 + REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
1.4011 + REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \
1.4012 +} while(0)
1.4013 +
1.4014 +#define __msc_set_cmdat_bus_width4() \
1.4015 +do { \
1.4016 + REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
1.4017 + REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \
1.4018 +} while(0)
1.4019 +
1.4020 +#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN )
1.4021 +#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT )
1.4022 +#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY )
1.4023 +#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK )
1.4024 +#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK )
1.4025 +#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ )
1.4026 +#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ )
1.4027 +#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN )
1.4028 +
1.4029 +/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */
1.4030 +#define __msc_set_cmdat_res_format(r) \
1.4031 +do { \
1.4032 + REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \
1.4033 + REG_MSC_CMDAT |= (r); \
1.4034 +} while(0)
1.4035 +
1.4036 +#define __msc_clear_cmdat() \
1.4037 + REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \
1.4038 + MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \
1.4039 + MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )
1.4040 +
1.4041 +#define __msc_get_imask() ( REG_MSC_IMASK )
1.4042 +#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff )
1.4043 +#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 )
1.4044 +#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ )
1.4045 +#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ )
1.4046 +#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ )
1.4047 +#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ )
1.4048 +#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES )
1.4049 +#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES )
1.4050 +#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE )
1.4051 +#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE )
1.4052 +#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE )
1.4053 +#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE )
1.4054 +
1.4055 +/* n=0,1,2,3,4,5,6,7 */
1.4056 +#define __msc_set_clkrt(n) \
1.4057 +do { \
1.4058 + REG_MSC_CLKRT = n; \
1.4059 +} while(0)
1.4060 +
1.4061 +#define __msc_get_ireg() ( REG_MSC_IREG )
1.4062 +#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ )
1.4063 +#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ )
1.4064 +#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES )
1.4065 +#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE )
1.4066 +#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE )
1.4067 +#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES )
1.4068 +#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE )
1.4069 +#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE )
1.4070 +
1.4071 +#define __msc_get_stat() ( REG_MSC_STAT )
1.4072 +#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0)
1.4073 +#define __msc_stat_crc_err() \
1.4074 + ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )
1.4075 +#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR )
1.4076 +#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR )
1.4077 +#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES )
1.4078 +#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES )
1.4079 +#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ )
1.4080 +
1.4081 +#define __msc_rd_resfifo() ( REG_MSC_RES )
1.4082 +#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO )
1.4083 +#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v )
1.4084 +
1.4085 +#define __msc_reset() \
1.4086 +do { \
1.4087 + REG_MSC_STRPCL = MSC_STRPCL_RESET; \
1.4088 + while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \
1.4089 +} while (0)
1.4090 +
1.4091 +#define __msc_start_clk() \
1.4092 +do { \
1.4093 + REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \
1.4094 +} while (0)
1.4095 +
1.4096 +#define __msc_stop_clk() \
1.4097 +do { \
1.4098 + REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \
1.4099 +} while (0)
1.4100 +
1.4101 +#define MMC_CLK 19169200
1.4102 +#define SD_CLK 24576000
1.4103 +
1.4104 +/* msc_clk should little than pclk and little than clk retrieve from card */
1.4105 +#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \
1.4106 +do { \
1.4107 + unsigned int rate, pclk, i; \
1.4108 + pclk = dev_clk; \
1.4109 + rate = type?SD_CLK:MMC_CLK; \
1.4110 + if (msc_clk && msc_clk < pclk) \
1.4111 + pclk = msc_clk; \
1.4112 + i = 0; \
1.4113 + while (pclk < rate) \
1.4114 + { \
1.4115 + i ++; \
1.4116 + rate >>= 1; \
1.4117 + } \
1.4118 + lv = i; \
1.4119 +} while(0)
1.4120 +
1.4121 +/* divide rate to little than or equal to 400kHz */
1.4122 +#define __msc_calc_slow_clk_divisor(type, lv) \
1.4123 +do { \
1.4124 + unsigned int rate, i; \
1.4125 + rate = (type?SD_CLK:MMC_CLK)/1000/400; \
1.4126 + i = 0; \
1.4127 + while (rate > 0) \
1.4128 + { \
1.4129 + rate >>= 1; \
1.4130 + i ++; \
1.4131 + } \
1.4132 + lv = i; \
1.4133 +} while(0)
1.4134 +
1.4135 +
1.4136 +/***************************************************************************
1.4137 + * SSI
1.4138 + ***************************************************************************/
1.4139 +
1.4140 +#define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE )
1.4141 +#define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE )
1.4142 +#define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL )
1.4143 +
1.4144 +#define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK )
1.4145 +
1.4146 +#define __ssi_select_ce2() \
1.4147 +do { \
1.4148 + REG_SSI_CR0 |= SSI_CR0_FSEL; \
1.4149 + REG_SSI_CR1 &= ~SSI_CR1_MULTS; \
1.4150 +} while (0)
1.4151 +
1.4152 +#define __ssi_select_gpc() \
1.4153 +do { \
1.4154 + REG_SSI_CR0 &= ~SSI_CR0_FSEL; \
1.4155 + REG_SSI_CR1 |= SSI_CR1_MULTS; \
1.4156 +} while (0)
1.4157 +
1.4158 +#define __ssi_enable_tx_intr() \
1.4159 + ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE )
1.4160 +
1.4161 +#define __ssi_disable_tx_intr() \
1.4162 + ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )
1.4163 +
1.4164 +#define __ssi_enable_rx_intr() \
1.4165 + ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE )
1.4166 +
1.4167 +#define __ssi_disable_rx_intr() \
1.4168 + ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) )
1.4169 +
1.4170 +#define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP )
1.4171 +#define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP )
1.4172 +
1.4173 +#define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV )
1.4174 +#define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV )
1.4175 +
1.4176 +#define __ssi_finish_receive() \
1.4177 + ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) )
1.4178 +
1.4179 +#define __ssi_disable_recvfinish() \
1.4180 + ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) )
1.4181 +
1.4182 +#define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH )
1.4183 +#define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH )
1.4184 +
1.4185 +#define __ssi_flush_fifo() \
1.4186 + ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH )
1.4187 +
1.4188 +#define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN )
1.4189 +
1.4190 +#define __ssi_spi_format() \
1.4191 +do { \
1.4192 + REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
1.4193 + REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \
1.4194 + REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
1.4195 + REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \
1.4196 +} while (0)
1.4197 +
1.4198 +/* TI's SSP format, must clear SSI_CR1.UNFIN */
1.4199 +#define __ssi_ssp_format() \
1.4200 +do { \
1.4201 + REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \
1.4202 + REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \
1.4203 +} while (0)
1.4204 +
1.4205 +/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */
1.4206 +#define __ssi_microwire_format() \
1.4207 +do { \
1.4208 + REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
1.4209 + REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \
1.4210 + REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
1.4211 + REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \
1.4212 + REG_SSI_CR0 &= ~SSI_CR0_RFINE; \
1.4213 +} while (0)
1.4214 +
1.4215 +/* CE# level (FRMHL), CE# in interval time (ITFRM),
1.4216 + clock phase and polarity (PHA POL),
1.4217 + interval time (SSIITR), interval characters/frame (SSIICR) */
1.4218 +
1.4219 + /* frmhl,endian,mcom,flen,pha,pol MASK */
1.4220 +#define SSICR1_MISC_MASK \
1.4221 + ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \
1.4222 + | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \
1.4223 +
1.4224 +#define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \
1.4225 +do { \
1.4226 + REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \
1.4227 + REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \
1.4228 + (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \
1.4229 + ((pha) << 1) | (pol); \
1.4230 +} while(0)
1.4231 +
1.4232 +/* Transfer with MSB or LSB first */
1.4233 +#define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST )
1.4234 +#define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST )
1.4235 +
1.4236 +#define __ssi_set_frame_length(n) \
1.4237 + REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4)
1.4238 +
1.4239 +/* n = 1 - 16 */
1.4240 +#define __ssi_set_microwire_command_length(n) \
1.4241 + ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) )
1.4242 +
1.4243 +/* Set the clock phase for SPI */
1.4244 +#define __ssi_set_spi_clock_phase(n) \
1.4245 + ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) )
1.4246 +
1.4247 +/* Set the clock polarity for SPI */
1.4248 +#define __ssi_set_spi_clock_polarity(n) \
1.4249 + ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) )
1.4250 +
1.4251 +/* n = ix8 */
1.4252 +#define __ssi_set_tx_trigger(n) \
1.4253 +do { \
1.4254 + REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \
1.4255 + REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \
1.4256 +} while (0)
1.4257 +
1.4258 +/* n = ix8 */
1.4259 +#define __ssi_set_rx_trigger(n) \
1.4260 +do { \
1.4261 + REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \
1.4262 + REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \
1.4263 +} while (0)
1.4264 +
1.4265 +#define __ssi_get_txfifo_count() \
1.4266 + ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT )
1.4267 +
1.4268 +#define __ssi_get_rxfifo_count() \
1.4269 + ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT )
1.4270 +
1.4271 +#define __ssi_clear_errors() \
1.4272 + ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) )
1.4273 +
1.4274 +#define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END )
1.4275 +#define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY )
1.4276 +
1.4277 +#define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF )
1.4278 +#define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE )
1.4279 +#define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF )
1.4280 +
1.4281 +#define __ssi_set_clk(dev_clk, ssi_clk) \
1.4282 + ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 )
1.4283 +
1.4284 +#define __ssi_receive_data() REG_SSI_DR
1.4285 +#define __ssi_transmit_data(v) ( REG_SSI_DR = (v) )
1.4286 +
1.4287 +
1.4288 +/***************************************************************************
1.4289 + * CIM
1.4290 + ***************************************************************************/
1.4291 +
1.4292 +#define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA )
1.4293 +#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA )
1.4294 +
1.4295 +#define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT )
1.4296 +#define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT )
1.4297 +
1.4298 +#define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP )
1.4299 +#define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP )
1.4300 +
1.4301 +#define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP )
1.4302 +#define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP )
1.4303 +
1.4304 +#define __cim_sample_data_at_pclk_falling_edge() \
1.4305 + ( REG_CIM_CFG |= CIM_CFG_PCP )
1.4306 +#define __cim_sample_data_at_pclk_rising_edge() \
1.4307 + ( REG_CIM_CFG &= ~CIM_CFG_PCP )
1.4308 +
1.4309 +#define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO )
1.4310 +#define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO )
1.4311 +
1.4312 +#define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC )
1.4313 +#define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC )
1.4314 +
1.4315 +/* n=0-7 */
1.4316 +#define __cim_set_data_packing_mode(n) \
1.4317 +do { \
1.4318 + REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \
1.4319 + REG_CIM_CFG |= (CIM_CFG_PACK_##n); \
1.4320 +} while (0)
1.4321 +
1.4322 +#define __cim_enable_ccir656_progressive_mode() \
1.4323 +do { \
1.4324 + REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
1.4325 + REG_CIM_CFG |= CIM_CFG_DSM_CPM; \
1.4326 +} while (0)
1.4327 +
1.4328 +#define __cim_enable_ccir656_interlace_mode() \
1.4329 +do { \
1.4330 + REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
1.4331 + REG_CIM_CFG |= CIM_CFG_DSM_CIM; \
1.4332 +} while (0)
1.4333 +
1.4334 +#define __cim_enable_gated_clock_mode() \
1.4335 +do { \
1.4336 + REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
1.4337 + REG_CIM_CFG |= CIM_CFG_DSM_GCM; \
1.4338 +} while (0)
1.4339 +
1.4340 +#define __cim_enable_nongated_clock_mode() \
1.4341 +do { \
1.4342 + REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
1.4343 + REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \
1.4344 +} while (0)
1.4345 +
1.4346 +/* sclk:system bus clock
1.4347 + * mclk: CIM master clock
1.4348 + */
1.4349 +#define __cim_set_master_clk(sclk, mclk) \
1.4350 +do { \
1.4351 + REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \
1.4352 + REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \
1.4353 +} while (0)
1.4354 +
1.4355 +#define __cim_enable_sof_intr() \
1.4356 + ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM )
1.4357 +#define __cim_disable_sof_intr() \
1.4358 + ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM )
1.4359 +
1.4360 +#define __cim_enable_eof_intr() \
1.4361 + ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM )
1.4362 +#define __cim_disable_eof_intr() \
1.4363 + ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM )
1.4364 +
1.4365 +#define __cim_enable_stop_intr() \
1.4366 + ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM )
1.4367 +#define __cim_disable_stop_intr() \
1.4368 + ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM )
1.4369 +
1.4370 +#define __cim_enable_trig_intr() \
1.4371 + ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM )
1.4372 +#define __cim_disable_trig_intr() \
1.4373 + ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM )
1.4374 +
1.4375 +#define __cim_enable_rxfifo_overflow_intr() \
1.4376 + ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM )
1.4377 +#define __cim_disable_rxfifo_overflow_intr() \
1.4378 + ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )
1.4379 +
1.4380 +/* n=1-16 */
1.4381 +#define __cim_set_frame_rate(n) \
1.4382 +do { \
1.4383 + REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \
1.4384 + REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \
1.4385 +} while (0)
1.4386 +
1.4387 +#define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN )
1.4388 +#define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN )
1.4389 +
1.4390 +#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )
1.4391 +#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )
1.4392 +
1.4393 +/* n=4,8,12,16,20,24,28,32 */
1.4394 +#define __cim_set_rxfifo_trigger(n) \
1.4395 +do { \
1.4396 + REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \
1.4397 + REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \
1.4398 +} while (0)
1.4399 +
1.4400 +#define __cim_clear_state() ( REG_CIM_STATE = 0 )
1.4401 +
1.4402 +#define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD )
1.4403 +#define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY )
1.4404 +#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG )
1.4405 +#define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF )
1.4406 +#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF )
1.4407 +#define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP )
1.4408 +#define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF )
1.4409 +#define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF )
1.4410 +
1.4411 +#define __cim_get_iid() ( REG_CIM_IID )
1.4412 +#define __cim_get_image_data() ( REG_CIM_RXFIFO )
1.4413 +#define __cim_get_dam_cmd() ( REG_CIM_CMD )
1.4414 +
1.4415 +#define __cim_set_da(a) ( REG_CIM_DA = (a) )
1.4416 +
1.4417 +/***************************************************************************
1.4418 + * LCD
1.4419 + ***************************************************************************/
1.4420 +#define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) )
1.4421 +#define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) )
1.4422 +
1.4423 +#define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS )
1.4424 +#define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
1.4425 +
1.4426 +#define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA )
1.4427 +#define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
1.4428 +
1.4429 +/* n=1,2,4,8,16 */
1.4430 +#define __lcd_set_bpp(n) \
1.4431 + ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
1.4432 +
1.4433 +/* n=4,8,16 */
1.4434 +#define __lcd_set_burst_length(n) \
1.4435 +do { \
1.4436 + REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \
1.4437 + REG_LCD_CTRL |= LCD_CTRL_BST_n##; \
1.4438 +} while (0)
1.4439 +
1.4440 +#define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
1.4441 +#define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
1.4442 +
1.4443 +#define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP )
1.4444 +#define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
1.4445 +
1.4446 +/* n=2,4,16 */
1.4447 +#define __lcd_set_stn_frc(n) \
1.4448 +do { \
1.4449 + REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \
1.4450 + REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \
1.4451 +} while (0)
1.4452 +
1.4453 +
1.4454 +#define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN )
1.4455 +#define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
1.4456 +
1.4457 +#define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN )
1.4458 +#define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
1.4459 +
1.4460 +#define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM )
1.4461 +#define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
1.4462 +
1.4463 +#define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM )
1.4464 +#define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
1.4465 +
1.4466 +#define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM )
1.4467 +#define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
1.4468 +
1.4469 +#define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
1.4470 +#define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
1.4471 +
1.4472 +#define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
1.4473 +#define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
1.4474 +
1.4475 +#define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM )
1.4476 +#define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
1.4477 +
1.4478 +#define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM )
1.4479 +#define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
1.4480 +
1.4481 +
1.4482 +/* LCD status register indication */
1.4483 +
1.4484 +#define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD )
1.4485 +#define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD )
1.4486 +#define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 )
1.4487 +#define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 )
1.4488 +#define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU )
1.4489 +#define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF )
1.4490 +#define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF )
1.4491 +
1.4492 +#define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU )
1.4493 +#define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF )
1.4494 +#define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF )
1.4495 +
1.4496 +#define __lcd_panel_white() ( REG_LCD_CFG |= LCD_CFG_WHITE )
1.4497 +#define __lcd_panel_black() ( REG_LCD_CFG &= ~LCD_CFG_WHITE )
1.4498 +
1.4499 +/* n=1,2,4,8 for single mono-STN
1.4500 + * n=4,8 for dual mono-STN
1.4501 + */
1.4502 +#define __lcd_set_panel_datawidth(n) \
1.4503 +do { \
1.4504 + REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \
1.4505 + REG_LCD_CFG |= LCD_CFG_PDW_n##; \
1.4506 +} while (0)
1.4507 +
1.4508 +/* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */
1.4509 +#define __lcd_set_panel_mode(m) \
1.4510 +do { \
1.4511 + REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \
1.4512 + REG_LCD_CFG |= (m); \
1.4513 +} while(0)
1.4514 +
1.4515 +/* n = 0-255 */
1.4516 +#define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff )
1.4517 +#define __lcd_set_ac_bias(n) \
1.4518 +do { \
1.4519 + REG_LCD_IO &= ~LCD_IO_ACB_MASK; \
1.4520 + REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \
1.4521 +} while(0)
1.4522 +
1.4523 +#define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR )
1.4524 +#define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR )
1.4525 +
1.4526 +#define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP )
1.4527 +#define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP )
1.4528 +
1.4529 +#define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP )
1.4530 +#define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP )
1.4531 +
1.4532 +#define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP )
1.4533 +#define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP )
1.4534 +
1.4535 +#define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP )
1.4536 +#define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP )
1.4537 +
1.4538 +#define __lcd_vsync_get_vps() \
1.4539 + ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
1.4540 +
1.4541 +#define __lcd_vsync_get_vpe() \
1.4542 + ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
1.4543 +#define __lcd_vsync_set_vpe(n) \
1.4544 +do { \
1.4545 + REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \
1.4546 + REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \
1.4547 +} while (0)
1.4548 +
1.4549 +#define __lcd_hsync_get_hps() \
1.4550 + ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
1.4551 +#define __lcd_hsync_set_hps(n) \
1.4552 +do { \
1.4553 + REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \
1.4554 + REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \
1.4555 +} while (0)
1.4556 +
1.4557 +#define __lcd_hsync_get_hpe() \
1.4558 + ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
1.4559 +#define __lcd_hsync_set_hpe(n) \
1.4560 +do { \
1.4561 + REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \
1.4562 + REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \
1.4563 +} while (0)
1.4564 +
1.4565 +#define __lcd_vat_get_ht() \
1.4566 + ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
1.4567 +#define __lcd_vat_set_ht(n) \
1.4568 +do { \
1.4569 + REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \
1.4570 + REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \
1.4571 +} while (0)
1.4572 +
1.4573 +#define __lcd_vat_get_vt() \
1.4574 + ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
1.4575 +#define __lcd_vat_set_vt(n) \
1.4576 +do { \
1.4577 + REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \
1.4578 + REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \
1.4579 +} while (0)
1.4580 +
1.4581 +#define __lcd_dah_get_hds() \
1.4582 + ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
1.4583 +#define __lcd_dah_set_hds(n) \
1.4584 +do { \
1.4585 + REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \
1.4586 + REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \
1.4587 +} while (0)
1.4588 +
1.4589 +#define __lcd_dah_get_hde() \
1.4590 + ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
1.4591 +#define __lcd_dah_set_hde(n) \
1.4592 +do { \
1.4593 + REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \
1.4594 + REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \
1.4595 +} while (0)
1.4596 +
1.4597 +#define __lcd_dav_get_vds() \
1.4598 + ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
1.4599 +#define __lcd_dav_set_vds(n) \
1.4600 +do { \
1.4601 + REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \
1.4602 + REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \
1.4603 +} while (0)
1.4604 +
1.4605 +#define __lcd_dav_get_vde() \
1.4606 + ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
1.4607 +#define __lcd_dav_set_vde(n) \
1.4608 +do { \
1.4609 + REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \
1.4610 + REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \
1.4611 +} while (0)
1.4612 +
1.4613 +#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
1.4614 +#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
1.4615 +#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
1.4616 +#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
1.4617 +
1.4618 +#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
1.4619 +#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
1.4620 +#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
1.4621 +#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
1.4622 +
1.4623 +#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL )
1.4624 +#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
1.4625 +
1.4626 +#define __lcd_cmd0_get_len() \
1.4627 + ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
1.4628 +#define __lcd_cmd1_get_len() \
1.4629 + ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
1.4630 +
1.4631 +/***************************************************************************
1.4632 + * RTC ops
1.4633 + ***************************************************************************/
1.4634 +
1.4635 +#define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY )
1.4636 +#define __rtc_enabled() \
1.4637 +do{ \
1.4638 + while(!__rtc_write_ready()); \
1.4639 + REG_RTC_RCR |= RTC_RCR_RTCE ; \
1.4640 +}while(0) \
1.4641 +
1.4642 +#define __rtc_disabled() \
1.4643 +do{ \
1.4644 + while(!__rtc_write_ready()); \
1.4645 + REG_RTC_RCR &= ~RTC_RCR_RTCE; \
1.4646 +}while(0)
1.4647 +#define __rtc_enable_alarm() \
1.4648 +do{ \
1.4649 + while(!__rtc_write_ready()); \
1.4650 + REG_RTC_RCR |= RTC_RCR_AE; \
1.4651 +}while(0)
1.4652 +
1.4653 +#define __rtc_disable_alarm() \
1.4654 +do{ \
1.4655 + while(!__rtc_write_ready()); \
1.4656 + REG_RTC_RCR &= ~RTC_RCR_AE; \
1.4657 +}while(0)
1.4658 +
1.4659 +#define __rtc_enable_alarm_irq() \
1.4660 +do{ \
1.4661 + while(!__rtc_write_ready()); \
1.4662 + REG_RTC_RCR |= RTC_RCR_AIE; \
1.4663 +}while(0)
1.4664 +
1.4665 +#define __rtc_disable_alarm_irq() \
1.4666 +do{ \
1.4667 + while(!__rtc_write_ready()); \
1.4668 + REG_RTC_RCR &= ~RTC_RCR_AIE; \
1.4669 +}while(0)
1.4670 +#define __rtc_enable_Hz_irq() \
1.4671 +do{ \
1.4672 + while(!__rtc_write_ready()); \
1.4673 + REG_RTC_RCR |= RTC_RCR_HZIE; \
1.4674 +}while(0)
1.4675 +
1.4676 +#define __rtc_disable_Hz_irq() \
1.4677 +do{ \
1.4678 + while(!__rtc_write_ready()); \
1.4679 + REG_RTC_RCR &= ~RTC_RCR_HZIE; \
1.4680 +}while(0)
1.4681 +#define __rtc_get_1Hz_flag() \
1.4682 +do{ \
1.4683 + while(!__rtc_write_ready()); \
1.4684 + ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \
1.4685 +}while(0)
1.4686 +#define __rtc_clear_1Hz_flag() \
1.4687 +do{ \
1.4688 + while(!__rtc_write_ready()); \
1.4689 + REG_RTC_RCR &= ~RTC_RCR_HZ; \
1.4690 +}while(0)
1.4691 +#define __rtc_get_alarm_flag() \
1.4692 +do{ \
1.4693 + while(!__rtc_write_ready()); \
1.4694 + ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1) \
1.4695 +while(0)
1.4696 +#define __rtc_clear_alarm_flag() \
1.4697 +do{ \
1.4698 + while(!__rtc_write_ready()); \
1.4699 + REG_RTC_RCR &= ~RTC_RCR_AF; \
1.4700 +}while(0)
1.4701 +#define __rtc_get_second() \
1.4702 +do{ \
1.4703 + while(!__rtc_write_ready());\
1.4704 + REG_RTC_RSR; \
1.4705 +}while(0)
1.4706 +
1.4707 +#define __rtc_set_second(v) \
1.4708 +do{ \
1.4709 + while(!__rtc_write_ready()); \
1.4710 + REG_RTC_RSR = v; \
1.4711 +}while(0)
1.4712 +
1.4713 +#define __rtc_get_alarm_second() \
1.4714 +do{ \
1.4715 + while(!__rtc_write_ready()); \
1.4716 + REG_RTC_RSAR; \
1.4717 +}while(0)
1.4718 +
1.4719 +
1.4720 +#define __rtc_set_alarm_second(v) \
1.4721 +do{ \
1.4722 + while(!__rtc_write_ready()); \
1.4723 + REG_RTC_RSAR = v; \
1.4724 +}while(0)
1.4725 +
1.4726 +#define __rtc_RGR_is_locked() \
1.4727 +do{ \
1.4728 + while(!__rtc_write_ready()); \
1.4729 + REG_RTC_RGR >> RTC_RGR_LOCK; \
1.4730 +}while(0)
1.4731 +#define __rtc_lock_RGR() \
1.4732 +do{ \
1.4733 + while(!__rtc_write_ready()); \
1.4734 + REG_RTC_RGR |= RTC_RGR_LOCK; \
1.4735 +}while(0)
1.4736 +
1.4737 +#define __rtc_unlock_RGR() \
1.4738 +do{ \
1.4739 + while(!__rtc_write_ready()); \
1.4740 + REG_RTC_RGR &= ~RTC_RGR_LOCK; \
1.4741 +}while(0)
1.4742 +
1.4743 +#define __rtc_get_adjc_val() \
1.4744 +do{ \
1.4745 + while(!__rtc_write_ready()); \
1.4746 + ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \
1.4747 +}while(0)
1.4748 +#define __rtc_set_adjc_val(v) \
1.4749 +do{ \
1.4750 + while(!__rtc_write_ready()); \
1.4751 + ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) )) \
1.4752 +}while(0)
1.4753 +
1.4754 +#define __rtc_get_nc1Hz_val() \
1.4755 + while(!__rtc_write_ready()); \
1.4756 + ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT )
1.4757 +
1.4758 +#define __rtc_set_nc1Hz_val(v) \
1.4759 +do{ \
1.4760 + while(!__rtc_write_ready()); \
1.4761 + ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) )) \
1.4762 +}while(0)
1.4763 +#define __rtc_power_down() \
1.4764 +do{ \
1.4765 + while(!__rtc_write_ready()); \
1.4766 + REG_RTC_HCR |= RTC_HCR_PD; \
1.4767 +}while(0)
1.4768 +
1.4769 +#define __rtc_get_hwfcr_val() \
1.4770 +do{ \
1.4771 + while(!__rtc_write_ready()); \
1.4772 + REG_RTC_HWFCR & RTC_HWFCR_MASK; \
1.4773 +}while(0)
1.4774 +#define __rtc_set_hwfcr_val(v) \
1.4775 +do{ \
1.4776 + while(!__rtc_write_ready()); \
1.4777 + REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \
1.4778 +}while(0)
1.4779 +
1.4780 +#define __rtc_get_hrcr_val() \
1.4781 +do{ \
1.4782 + while(!__rtc_write_ready()); \
1.4783 + ( REG_RTC_HRCR & RTC_HRCR_MASK ); \
1.4784 +}while(0)
1.4785 +#define __rtc_set_hrcr_val(v) \
1.4786 +do{ \
1.4787 + while(!__rtc_write_ready()); \
1.4788 + ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \
1.4789 +}while(0)
1.4790 +
1.4791 +#define __rtc_enable_alarm_wakeup() \
1.4792 +do{ \
1.4793 + while(!__rtc_write_ready()); \
1.4794 + ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \
1.4795 +}while(0)
1.4796 +
1.4797 +#define __rtc_disable_alarm_wakeup() \
1.4798 +do{ \
1.4799 + while(!__rtc_write_ready()); \
1.4800 + ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \
1.4801 +}while(0)
1.4802 +
1.4803 +#define __rtc_status_hib_reset_occur() \
1.4804 +do{ \
1.4805 + while(!__rtc_write_ready()); \
1.4806 + ( (REG_RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 ); \
1.4807 +}while(0)
1.4808 +#define __rtc_status_ppr_reset_occur() \
1.4809 +do{ \
1.4810 + while(!__rtc_write_ready()); \
1.4811 + ( (REG_RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 ); \
1.4812 +}while(0)
1.4813 +#define __rtc_status_wakeup_pin_waken_up() \
1.4814 +do{ \
1.4815 + while(!__rtc_write_ready()); \
1.4816 + ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \
1.4817 +}while(0)
1.4818 +#define __rtc_status_alarm_waken_up() \
1.4819 +do{ \
1.4820 + while(!__rtc_write_ready()); \
1.4821 + ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \
1.4822 +}while(0)
1.4823 +#define __rtc_clear_hib_stat_all() \
1.4824 +do{ \
1.4825 + while(!__rtc_write_ready()); \
1.4826 + ( REG_RTC_HWRSR = 0 ); \
1.4827 +}while(0)
1.4828 +
1.4829 +#define __rtc_get_scratch_pattern() \
1.4830 + while(!__rtc_write_ready()); \
1.4831 + (REG_RTC_HSPR)
1.4832 +#define __rtc_set_scratch_pattern(n) \
1.4833 +do{ \
1.4834 + while(!__rtc_write_ready()); \
1.4835 + (REG_RTC_HSPR = n ); \
1.4836 +}while(0)
1.4837 +
1.4838 +#endif /* !__ASSEMBLY__ */
1.4839 +
1.4840 +#endif /* __JZ4740_H__ */