1.1 --- a/board-nanonote.c Sun Jun 07 02:20:54 2015 +0200
1.2 +++ b/board-nanonote.c Sun Jun 07 18:21:24 2015 +0200
1.3 @@ -80,72 +80,6 @@
1.4 __gpio_as_sdram_32bit();
1.5 }
1.6
1.7 -void gpio_init2(void)
1.8 -{
1.9 - /*
1.10 - * Initialize LCD pins
1.11 - */
1.12 - __gpio_as_slcd_8bit();
1.13 -
1.14 - /*
1.15 - * Initialize MSC pins
1.16 - */
1.17 - __gpio_as_msc();
1.18 -
1.19 - /*
1.20 - * Initialize Other pins
1.21 - */
1.22 - unsigned int i;
1.23 - for (i = 0; i < 7; i++){
1.24 - __gpio_as_input(GPIO_KEYIN_BASE + i);
1.25 - __gpio_enable_pull(GPIO_KEYIN_BASE + i);
1.26 - }
1.27 -
1.28 - for (i = 0; i < 8; i++) {
1.29 - __gpio_as_output(GPIO_KEYOUT_BASE + i);
1.30 - __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
1.31 - }
1.32 -
1.33 - /* enable the TP4, TP5 as UART0 */
1.34 - __gpio_jtag_to_uart0();
1.35 -
1.36 - __gpio_as_input(GPIO_KEYIN_8);
1.37 - __gpio_enable_pull(GPIO_KEYIN_8);
1.38 -
1.39 - __gpio_as_output(GPIO_AUDIO_POP);
1.40 - __gpio_set_pin(GPIO_AUDIO_POP);
1.41 -
1.42 - __gpio_as_output(GPIO_LCD_CS);
1.43 - __gpio_clear_pin(GPIO_LCD_CS);
1.44 -
1.45 - __gpio_as_output(GPIO_AMP_EN);
1.46 - __gpio_clear_pin(GPIO_AMP_EN);
1.47 -
1.48 - __gpio_as_output(GPIO_SDPW_EN);
1.49 - __gpio_disable_pull(GPIO_SDPW_EN);
1.50 - __gpio_clear_pin(GPIO_SDPW_EN);
1.51 -
1.52 - __gpio_as_input(GPIO_SD_DETECT);
1.53 - __gpio_disable_pull(GPIO_SD_DETECT);
1.54 -
1.55 - __gpio_as_input(GPIO_USB_DETECT);
1.56 - __gpio_enable_pull(GPIO_USB_DETECT);
1.57 -}
1.58 -
1.59 -void cpm_init(void)
1.60 -{
1.61 - __cpm_stop_ipu();
1.62 - __cpm_stop_cim();
1.63 - __cpm_stop_i2c();
1.64 - __cpm_stop_ssi();
1.65 - __cpm_stop_uart1();
1.66 - __cpm_stop_sadc();
1.67 - __cpm_stop_uhc();
1.68 - __cpm_stop_udc();
1.69 - __cpm_stop_aic1();
1.70 -/* __cpm_stop_aic2();*/
1.71 -}
1.72 -
1.73 void pll_init(void)
1.74 {
1.75 register unsigned int cfcr, plcr1;
1.76 @@ -278,244 +212,3 @@
1.77
1.78 /* everything is ok now */
1.79 }
1.80 -
1.81 -void rtc_init(void)
1.82 -{
1.83 - while ( !__rtc_write_ready());
1.84 - __rtc_enable_alarm(); /* enable alarm */
1.85 -
1.86 - while ( !__rtc_write_ready());
1.87 - REG_RTC_RGR = 0x00007fff; /* type value */
1.88 -
1.89 - while ( !__rtc_write_ready());
1.90 - REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */
1.91 -
1.92 - while ( !__rtc_write_ready());
1.93 - REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */
1.94 -}
1.95 -
1.96 -unsigned long get_memory_size(void)
1.97 -{
1.98 - unsigned int dmcr;
1.99 - unsigned int rows, cols, dw, banks;
1.100 - unsigned long size;
1.101 -
1.102 - dmcr = REG_EMC_DMCR;
1.103 - rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
1.104 - cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
1.105 - dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
1.106 - banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
1.107 -
1.108 - size = (1 << (rows + cols)) * dw * banks;
1.109 -
1.110 - return size;
1.111 -}
1.112 -
1.113 -/* Timer routines. */
1.114 -
1.115 -#define TIMER_CHAN 0
1.116 -#define TIMER_FDATA 0xffff /* Timer full data value */
1.117 -#define TIMER_HZ CONFIG_SYS_HZ
1.118 -
1.119 -#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */
1.120 -
1.121 -static unsigned long timestamp;
1.122 -static unsigned long lastdec;
1.123 -
1.124 -void reset_timer_masked(void);
1.125 -unsigned long get_timer_masked(void);
1.126 -void udelay_masked(unsigned long usec);
1.127 -
1.128 -/*
1.129 - * timer without interrupts
1.130 - */
1.131 -
1.132 -int timer_init(void)
1.133 -{
1.134 - REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN;
1.135 - REG_TCU_TCNT(TIMER_CHAN) = 0;
1.136 - REG_TCU_TDHR(TIMER_CHAN) = 0;
1.137 - REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA;
1.138 -
1.139 - REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */
1.140 - REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */
1.141 - REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */
1.142 -
1.143 - lastdec = 0;
1.144 - timestamp = 0;
1.145 -
1.146 - return 0;
1.147 -}
1.148 -
1.149 -void reset_timer(void)
1.150 -{
1.151 - reset_timer_masked ();
1.152 -}
1.153 -
1.154 -unsigned long get_timer(unsigned long base)
1.155 -{
1.156 - return get_timer_masked () - base;
1.157 -}
1.158 -
1.159 -void set_timer(unsigned long t)
1.160 -{
1.161 - timestamp = t;
1.162 -}
1.163 -
1.164 -void udelay (unsigned long usec)
1.165 -{
1.166 - unsigned long tmo,tmp;
1.167 -
1.168 - /* normalize */
1.169 - if (usec >= 1000) {
1.170 - tmo = usec / 1000;
1.171 - tmo *= TIMER_HZ;
1.172 - tmo /= 1000;
1.173 - }
1.174 - else {
1.175 - if (usec >= 1) {
1.176 - tmo = usec * TIMER_HZ;
1.177 - tmo /= (1000*1000);
1.178 - }
1.179 - else
1.180 - tmo = 1;
1.181 - }
1.182 -
1.183 - /* check for rollover during this delay */
1.184 - tmp = get_timer (0);
1.185 - if ((tmp + tmo) < tmp )
1.186 - reset_timer_masked(); /* timer would roll over */
1.187 - else
1.188 - tmo += tmp;
1.189 -
1.190 - while (get_timer_masked () < tmo);
1.191 -}
1.192 -
1.193 -void reset_timer_masked (void)
1.194 -{
1.195 - /* reset time */
1.196 - lastdec = READ_TIMER;
1.197 - timestamp = 0;
1.198 -}
1.199 -
1.200 -unsigned long get_timer_masked (void)
1.201 -{
1.202 - unsigned long now = READ_TIMER;
1.203 -
1.204 - if (lastdec <= now) {
1.205 - /* normal mode */
1.206 - timestamp += (now - lastdec);
1.207 - } else {
1.208 - /* we have an overflow ... */
1.209 - timestamp += TIMER_FDATA + now - lastdec;
1.210 - }
1.211 - lastdec = now;
1.212 -
1.213 - return timestamp;
1.214 -}
1.215 -
1.216 -void udelay_masked (unsigned long usec)
1.217 -{
1.218 - unsigned long tmo;
1.219 - unsigned long endtime;
1.220 - signed long diff;
1.221 -
1.222 - /* normalize */
1.223 - if (usec >= 1000) {
1.224 - tmo = usec / 1000;
1.225 - tmo *= TIMER_HZ;
1.226 - tmo /= 1000;
1.227 - } else {
1.228 - if (usec > 1) {
1.229 - tmo = usec * TIMER_HZ;
1.230 - tmo /= (1000*1000);
1.231 - } else {
1.232 - tmo = 1;
1.233 - }
1.234 - }
1.235 -
1.236 - endtime = get_timer_masked () + tmo;
1.237 -
1.238 - do {
1.239 - unsigned long now = get_timer_masked ();
1.240 - diff = endtime - now;
1.241 - } while (diff >= 0);
1.242 -}
1.243 -
1.244 -/*
1.245 - * This function is derived from PowerPC code (read timebase as long long).
1.246 - * On MIPS it just returns the timer value.
1.247 - */
1.248 -unsigned long long get_ticks(void)
1.249 -{
1.250 - return get_timer(0);
1.251 -}
1.252 -
1.253 -/*
1.254 - * This function is derived from PowerPC code (timebase clock frequency).
1.255 - * On MIPS it returns the number of timer ticks per second.
1.256 - */
1.257 -unsigned long get_tbclk (void)
1.258 -{
1.259 - return TIMER_HZ;
1.260 -}
1.261 -
1.262 -/* CPU-specific routines from U-Boot.
1.263 - See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c
1.264 - See: u-boot/arch/mips/include/asm/cacheops.h
1.265 -*/
1.266 -
1.267 -#define Index_Store_Tag_I 0x08
1.268 -#define Index_Writeback_Inv_D 0x15
1.269 -
1.270 -void flush_icache_all(void)
1.271 -{
1.272 - u32 addr, t = 0;
1.273 -
1.274 - asm volatile ("mtc0 $0, $28"); /* Clear Taglo */
1.275 - asm volatile ("mtc0 $0, $29"); /* Clear TagHi */
1.276 -
1.277 - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE;
1.278 - addr += CONFIG_SYS_CACHELINE_SIZE) {
1.279 - asm volatile (
1.280 - ".set mips3\n\t"
1.281 - " cache %0, 0(%1)\n\t"
1.282 - ".set mips2\n\t"
1.283 - :
1.284 - : "I" (Index_Store_Tag_I), "r"(addr));
1.285 - }
1.286 -
1.287 - /* invalicate btb */
1.288 - asm volatile (
1.289 - ".set mips32\n\t"
1.290 - "mfc0 %0, $16, 7\n\t"
1.291 - "nop\n\t"
1.292 - "ori %0,2\n\t"
1.293 - "mtc0 %0, $16, 7\n\t"
1.294 - ".set mips2\n\t"
1.295 - :
1.296 - : "r" (t));
1.297 -}
1.298 -
1.299 -void flush_dcache_all(void)
1.300 -{
1.301 - u32 addr;
1.302 -
1.303 - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE;
1.304 - addr += CONFIG_SYS_CACHELINE_SIZE) {
1.305 - asm volatile (
1.306 - ".set mips3\n\t"
1.307 - " cache %0, 0(%1)\n\t"
1.308 - ".set mips2\n\t"
1.309 - :
1.310 - : "I" (Index_Writeback_Inv_D), "r"(addr));
1.311 - }
1.312 -
1.313 - asm volatile ("sync");
1.314 -}
1.315 -
1.316 -void flush_cache_all(void)
1.317 -{
1.318 - flush_dcache_all();
1.319 - flush_icache_all();
1.320 -}