1.1 --- a/stage2/jzlcd.c Tue Jun 30 16:10:40 2015 +0200
1.2 +++ b/stage2/jzlcd.c Tue Jun 30 19:38:56 2015 +0200
1.3 @@ -369,8 +369,6 @@
1.4 val--;
1.5 if ( val > 0xF )
1.6 val = 0xF;
1.7 - __cpm_set_lcdclk_div(val);
1.8 - REG_CPM_CFCR |= CPM_CFCR_UPE;
1.9 #else
1.10 pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
1.11 pll_div = pll_div ? 1 : 2 ;
1.12 @@ -390,9 +388,10 @@
1.13 if ( val > 0x1f ) {
1.14 val = 0x1f;
1.15 }
1.16 +#endif
1.17 __cpm_set_ldiv( val );
1.18 REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
1.19 -#endif
1.20 +
1.21 __cpm_start_lcd();
1.22 udelay(1000);
1.23