1.1 --- a/include/sdram.h Fri Jun 12 18:02:08 2015 +0200
1.2 +++ b/include/sdram.h Fri Jun 12 23:33:11 2015 +0200
1.3 @@ -37,16 +37,26 @@
1.4 /*
1.5 * SDRAM configuration (timings in ns)
1.6 */
1.7 -#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
1.8 -#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
1.9 -#define SDRAM_ROW 13 /* Row address: 11 to 13 */
1.10 -#define SDRAM_COL 9 /* Column address: 8 to 12 */
1.11 -#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
1.12 -#define SDRAM_TRAS 45 /* RAS# Active Time */
1.13 -#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
1.14 -#define SDRAM_TPC 20 /* RAS# Precharge Time */
1.15 -#define SDRAM_TRWL 7 /* Write Latency Time */
1.16 -#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
1.17 +#ifdef CONFIG_CPU_JZ4730_MINIPC
1.18 +#define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */
1.19 +#else
1.20 +#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
1.21 +#endif
1.22 +
1.23 +#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
1.24 +#define SDRAM_ROW 13 /* Row address: 11 to 13 */
1.25 +#define SDRAM_COL 9 /* Column address: 8 to 12 */
1.26 +#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
1.27 +#define SDRAM_TRAS 45 /* RAS# Active Time */
1.28 +#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
1.29 +#define SDRAM_TPC 20 /* RAS# Precharge Time */
1.30 +#define SDRAM_TRWL 7 /* Write Latency Time */
1.31 +
1.32 +#ifdef CONFIG_CPU_JZ4730_MINIPC
1.33 +#define SDRAM_TREF 7812 /* Refresh period: 8192 cycles/64ms */
1.34 +#else
1.35 +#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
1.36 +#endif
1.37
1.38 #define SDRAM_ROW0 11 /* Row address minimum */
1.39 #define SDRAM_COL0 8 /* Column address minimum */