1.1 --- a/include/jz4740.h Fri May 22 18:37:44 2015 +0200
1.2 +++ b/include/jz4740.h Fri Jun 05 00:07:00 2015 +0200
1.3 @@ -23,34 +23,7 @@
1.4
1.5 #include "xburst_types.h"
1.6
1.7 -#if 0
1.8 -static inline void jz_flush_dcache(void)
1.9 -{
1.10 - unsigned long start;
1.11 - unsigned long end;
1.12 -
1.13 - start = KSEG0;
1.14 - end = start + CFG_DCACHE_SIZE;
1.15 - while (start < end) {
1.16 - cache_unroll(start,Index_Writeback_Inv_D);
1.17 - start += CFG_CACHELINE_SIZE;
1.18 - }
1.19 -}
1.20 -
1.21 -static inline void jz_flush_icache(void)
1.22 -{
1.23 - unsigned long start;
1.24 - unsigned long end;
1.25 -
1.26 - start = KSEG0;
1.27 - end = start + CFG_ICACHE_SIZE;
1.28 - while(start < end) {
1.29 - cache_unroll(start,Index_Invalidate_I);
1.30 - start += CFG_CACHELINE_SIZE;
1.31 - }
1.32 -}
1.33 -
1.34 -#endif
1.35 +#ifndef __ASSEMBLY__
1.36 #define cache_unroll(base,op) \
1.37 __asm__ __volatile__(" \
1.38 .set noreorder; \
1.39 @@ -61,44 +34,14 @@
1.40 : \
1.41 : "r" (base), \
1.42 "i" (op));
1.43 -/* cpu pipeline flush */
1.44 -static inline void jz_sync(void)
1.45 -{
1.46 - __asm__ volatile ("sync");
1.47 -}
1.48 -
1.49 -static inline void jz_writeb(u32 address, u8 value)
1.50 -{
1.51 - *((volatile u8 *)address) = value;
1.52 -}
1.53 -
1.54 -static inline void jz_writew(u32 address, u16 value)
1.55 -{
1.56 - *((volatile u16 *)address) = value;
1.57 -}
1.58 -
1.59 -static inline void jz_writel(u32 address, u32 value)
1.60 -{
1.61 - *((volatile u32 *)address) = value;
1.62 -}
1.63 -
1.64 -static inline u8 jz_readb(u32 address)
1.65 -{
1.66 - return *((volatile u8 *)address);
1.67 -}
1.68 -
1.69 -static inline u16 jz_readw(u32 address)
1.70 -{
1.71 - return *((volatile u16 *)address);
1.72 -}
1.73 -
1.74 -static inline u32 jz_readl(u32 address)
1.75 -{
1.76 - return *((volatile u32 *)address);
1.77 -}
1.78 -
1.79 -/* Boot ROM Specification */
1.80 -
1.81 +
1.82 +#define REG8(addr) *((volatile u8 *)(addr))
1.83 +#define REG16(addr) *((volatile u16 *)(addr))
1.84 +#define REG32(addr) *((volatile u32 *)(addr))
1.85 +
1.86 +#endif /* !ASSEMBLY */
1.87 +
1.88 +/* Boot ROM Specification */
1.89 /* NOR Boot config */
1.90 #define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
1.91 #define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
1.92 @@ -135,9 +78,9 @@
1.93 #define ETH_BASE 0xB3100000
1.94
1.95
1.96 -/*************************************************************************
1.97 +/*
1.98 * INTC (Interrupt Controller)
1.99 - *************************************************************************/
1.100 + */
1.101 #define INTC_ISR (INTC_BASE + 0x00)
1.102 #define INTC_IMR (INTC_BASE + 0x04)
1.103 #define INTC_IMSR (INTC_BASE + 0x08)
1.104 @@ -178,9 +121,9 @@
1.105 #define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
1.106
1.107
1.108 -/*************************************************************************
1.109 +/*
1.110 * RTC
1.111 - *************************************************************************/
1.112 + */
1.113 #define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
1.114 #define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
1.115 #define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
1.116 @@ -240,7 +183,6 @@
1.117 #define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
1.118 #define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
1.119
1.120 -
1.121 /*************************************************************************
1.122 * CPM (Clock reset and Power control Management)
1.123 *************************************************************************/
1.124 @@ -359,7 +301,8 @@
1.125 /* Sleep Control Register */
1.126 #define CPM_SCR_O1ST_BIT 8
1.127 #define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
1.128 -#define CPM_SCR_USBPHY_ENABLE (1 << 6)
1.129 +#define CPM_SCR_UDCPHY_ENABLE (1 << 6)
1.130 +#define CPM_SCR_USBPHY_DISABLE (1 << 7)
1.131 #define CPM_SCR_OSC_ENABLE (1 << 4)
1.132
1.133 /* Hibernate Control Register */
1.134 @@ -479,12 +422,12 @@
1.135 #define TCU_TCSR_PWM_EN (1 << 7)
1.136 #define TCU_TCSR_PRESCALE_BIT 3
1.137 #define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
1.138 - #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
1.139 - #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
1.140 - #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
1.141 - #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
1.142 - #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
1.143 - #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
1.144 +#define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
1.145 +#define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
1.146 +#define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
1.147 +#define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
1.148 +#define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
1.149 +#define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
1.150 #define TCU_TCSR_EXT_EN (1 << 2)
1.151 #define TCU_TCSR_RTC_EN (1 << 1)
1.152 #define TCU_TCSR_PCK_EN (1 << 0)
1.153 @@ -613,9 +556,9 @@
1.154 #define TCU_TSSR_STPC0 (1 << 0)
1.155
1.156
1.157 -/*************************************************************************
1.158 +/*
1.159 * WDT (WatchDog Timer)
1.160 - *************************************************************************/
1.161 + */
1.162 #define WDT_TDR (WDT_BASE + 0x00)
1.163 #define WDT_TCER (WDT_BASE + 0x04)
1.164 #define WDT_TCNT (WDT_BASE + 0x08)
1.165 @@ -642,9 +585,9 @@
1.166 #define WDT_TCER_TCEN (1 << 0)
1.167
1.168
1.169 -/*************************************************************************
1.170 +/*
1.171 * DMAC (DMA Controller)
1.172 - *************************************************************************/
1.173 + */
1.174
1.175 #define MAX_DMA_NUM 6 /* max 6 channels */
1.176
1.177 @@ -729,18 +672,18 @@
1.178 /* DMA request source register */
1.179 #define DMAC_DRSR_RS_BIT 0
1.180 #define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
1.181 - #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
1.182 - #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
1.183 - #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
1.184 - #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT)
1.185 - #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT)
1.186 - #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
1.187 - #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
1.188 - #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT)
1.189 - #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT)
1.190 - #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
1.191 - #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
1.192 - #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT)
1.193 +#define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
1.194 +#define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
1.195 +#define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
1.196 +#define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT)
1.197 +#define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT)
1.198 +#define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
1.199 +#define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
1.200 +#define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT)
1.201 +#define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT)
1.202 +#define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
1.203 +#define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
1.204 +#define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT)
1.205
1.206 /* DMA channel control/status register */
1.207 #define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
1.208 @@ -845,7 +788,7 @@
1.209 *************************************************************************/
1.210 #define MAX_GPIO_NUM 128
1.211
1.212 -/*n = 0,1,2,3 */
1.213 +/* = 0,1,2,3 */
1.214 #define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
1.215 #define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
1.216 #define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
1.217 @@ -902,7 +845,7 @@
1.218 *************************************************************************/
1.219
1.220 #define IRDA_BASE UART0_BASE
1.221 -/*#define UART_BASE UART0_BASE */
1.222 +/* #define UART_BASE UART0_BASE */
1.223 #define UART_OFF 0x1000
1.224
1.225 /* Register Offset */
1.226 @@ -1610,39 +1553,29 @@
1.227
1.228 /* MSC Command Sequence Control Register (MSC_CMDAT) */
1.229
1.230 -#define MSC_CMDAT_IO_ABORT (1 << 11)
1.231 -#define MSC_CMDAT_BUS_WIDTH_BIT 9
1.232 -#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
1.233 - #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
1.234 - #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
1.235 - #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
1.236 - #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
1.237 -#define MSC_CMDAT_DMA_EN (1 << 8)
1.238 -#define MSC_CMDAT_INIT (1 << 7)
1.239 -#define MSC_CMDAT_BUSY (1 << 6)
1.240 -#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
1.241 -#define MSC_CMDAT_WRITE (1 << 4)
1.242 -#define MSC_CMDAT_READ (0 << 4)
1.243 -#define MSC_CMDAT_DATA_EN (1 << 3)
1.244 +#define MSC_CMDAT_IO_ABORT (1 << 11)
1.245 +#define MSC_CMDAT_BUS_WIDTH_BIT 9
1.246 +#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
1.247 +#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
1.248 +#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
1.249 +#define MSC_CMDAT_DMA_EN (1 << 8)
1.250 +#define MSC_CMDAT_INIT (1 << 7)
1.251 +#define MSC_CMDAT_BUSY (1 << 6)
1.252 +#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
1.253 +#define MSC_CMDAT_WRITE (1 << 4)
1.254 +#define MSC_CMDAT_READ (0 << 4)
1.255 +#define MSC_CMDAT_DATA_EN (1 << 3)
1.256 #define MSC_CMDAT_RESPONSE_BIT 0
1.257 #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
1.258 - #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
1.259 - #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
1.260 - #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
1.261 - #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
1.262 - #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
1.263 - #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
1.264 - #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
1.265 -
1.266 -#define CMDAT_DMA_EN (1 << 8)
1.267 -#define CMDAT_INIT (1 << 7)
1.268 -#define CMDAT_BUSY (1 << 6)
1.269 -#define CMDAT_STREAM (1 << 5)
1.270 -#define CMDAT_WRITE (1 << 4)
1.271 -#define CMDAT_DATA_EN (1 << 3)
1.272 +#define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT)
1.273 +#define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT)
1.274 +#define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT)
1.275 +#define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT)
1.276 +#define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT)
1.277 +#define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT)
1.278 +#define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT)
1.279
1.280 /* MSC Interrupts Mask Register (MSC_IMASK) */
1.281 -
1.282 #define MSC_IMASK_SDIO (1 << 7)
1.283 #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
1.284 #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
1.285 @@ -1652,7 +1585,6 @@
1.286
1.287
1.288 /* MSC Interrupts Status Register (MSC_IREG) */
1.289 -
1.290 #define MSC_IREG_SDIO (1 << 7)
1.291 #define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
1.292 #define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
1.293 @@ -1661,9 +1593,9 @@
1.294 #define MSC_IREG_DATA_TRAN_DONE (1 << 0)
1.295
1.296
1.297 -/*************************************************************************
1.298 +/*
1.299 * EMC (External Memory Controller)
1.300 - *************************************************************************/
1.301 + */
1.302 #define EMC_BCR (EMC_BASE + 0x0) /* BCR */
1.303
1.304 #define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */
1.305 @@ -1894,7 +1826,6 @@
1.306 #define EMC_SDMR_CAS3_32BIT \
1.307 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1.308
1.309 -
1.310 /*************************************************************************
1.311 * CIM
1.312 *************************************************************************/
1.313 @@ -2126,9 +2057,11 @@
1.314 #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT)
1.315 #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT)
1.316 #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT)
1.317 + #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT)
1.318 #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT)
1.319 #define SLCD_CFG_CWIDTH_16BIT (0 << 8)
1.320 #define SLCD_CFG_CWIDTH_8BIT (1 << 8)
1.321 +#define SLCD_CFG_CWIDTH_18BIT (2 << 8)
1.322 #define SLCD_CFG_CS_ACTIVE_LOW (0 << 4)
1.323 #define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
1.324 #define SLCD_CFG_RS_CMD_LOW (0 << 3)
1.325 @@ -2467,175 +2400,163 @@
1.326 #define USB_CNTL_BURST_16 (3 << 9)
1.327
1.328
1.329 +
1.330 /* Module Operation Definitions */
1.331 #ifndef __ASSEMBLY__
1.332
1.333 -/***************************************************************************
1.334 - * GPIO
1.335 - ***************************************************************************/
1.336 -
1.337 -//------------------------------------------------------
1.338 -// GPIO Pins Description
1.339 -//
1.340 -// PORT 0:
1.341 -//
1.342 -// PIN/BIT N FUNC0 FUNC1
1.343 -// 0 D0 -
1.344 -// 1 D1 -
1.345 -// 2 D2 -
1.346 -// 3 D3 -
1.347 -// 4 D4 -
1.348 -// 5 D5 -
1.349 -// 6 D6 -
1.350 -// 7 D7 -
1.351 -// 8 D8 -
1.352 -// 9 D9 -
1.353 -// 10 D10 -
1.354 -// 11 D11 -
1.355 -// 12 D12 -
1.356 -// 13 D13 -
1.357 -// 14 D14 -
1.358 -// 15 D15 -
1.359 -// 16 D16 -
1.360 -// 17 D17 -
1.361 -// 18 D18 -
1.362 -// 19 D19 -
1.363 -// 20 D20 -
1.364 -// 21 D21 -
1.365 -// 22 D22 -
1.366 -// 23 D23 -
1.367 -// 24 D24 -
1.368 -// 25 D25 -
1.369 -// 26 D26 -
1.370 -// 27 D27 -
1.371 -// 28 D28 -
1.372 -// 29 D29 -
1.373 -// 30 D30 -
1.374 -// 31 D31 -
1.375 -//
1.376 -//------------------------------------------------------
1.377 -// PORT 1:
1.378 -//
1.379 -// PIN/BIT N FUNC0 FUNC1
1.380 -// 0 A0 -
1.381 -// 1 A1 -
1.382 -// 2 A2 -
1.383 -// 3 A3 -
1.384 -// 4 A4 -
1.385 -// 5 A5 -
1.386 -// 6 A6 -
1.387 -// 7 A7 -
1.388 -// 8 A8 -
1.389 -// 9 A9 -
1.390 -// 10 A10 -
1.391 -// 11 A11 -
1.392 -// 12 A12 -
1.393 -// 13 A13 -
1.394 -// 14 A14 -
1.395 -// 15 A15/CL -
1.396 -// 16 A16/AL -
1.397 -// 17 LCD_CLS A21
1.398 -// 18 LCD_SPL A22
1.399 -// 19 DCS# -
1.400 -// 20 RAS# -
1.401 -// 21 CAS# -
1.402 -// 22 RDWE#/BUFD# -
1.403 -// 23 CKE -
1.404 -// 24 CKO -
1.405 -// 25 CS1# -
1.406 -// 26 CS2# -
1.407 -// 27 CS3# -
1.408 -// 28 CS4# -
1.409 -// 29 RD# -
1.410 -// 30 WR# -
1.411 -// 31 WE0# -
1.412 -//
1.413 -// Note: PIN15&16 are CL&AL when connecting to NAND flash.
1.414 -//------------------------------------------------------
1.415 -// PORT 2:
1.416 -//
1.417 -// PIN/BIT N FUNC0 FUNC1
1.418 -// 0 LCD_D0 -
1.419 -// 1 LCD_D1 -
1.420 -// 2 LCD_D2 -
1.421 -// 3 LCD_D3 -
1.422 -// 4 LCD_D4 -
1.423 -// 5 LCD_D5 -
1.424 -// 6 LCD_D6 -
1.425 -// 7 LCD_D7 -
1.426 -// 8 LCD_D8 -
1.427 -// 9 LCD_D9 -
1.428 -// 10 LCD_D10 -
1.429 -// 11 LCD_D11 -
1.430 -// 12 LCD_D12 -
1.431 -// 13 LCD_D13 -
1.432 -// 14 LCD_D14 -
1.433 -// 15 LCD_D15 -
1.434 -// 16 LCD_D16 -
1.435 -// 17 LCD_D17 -
1.436 -// 18 LCD_PCLK -
1.437 -// 19 LCD_HSYNC -
1.438 -// 20 LCD_VSYNC -
1.439 -// 21 LCD_DE -
1.440 -// 22 LCD_PS A19
1.441 -// 23 LCD_REV A20
1.442 -// 24 WE1# -
1.443 -// 25 WE2# -
1.444 -// 26 WE3# -
1.445 -// 27 WAIT# -
1.446 -// 28 FRE# -
1.447 -// 29 FWE# -
1.448 -// 30(NOTE:FRB#) - -
1.449 -// 31 - -
1.450 -//
1.451 -// NOTE(1): PIN30 is used for FRB# when connecting to NAND flash.
1.452 -//------------------------------------------------------
1.453 -// PORT 3:
1.454 -//
1.455 -// PIN/BIT N FUNC0 FUNC1
1.456 -// 0 CIM_D0 -
1.457 -// 1 CIM_D1 -
1.458 -// 2 CIM_D2 -
1.459 -// 3 CIM_D3 -
1.460 -// 4 CIM_D4 -
1.461 -// 5 CIM_D5 -
1.462 -// 6 CIM_D6 -
1.463 -// 7 CIM_D7 -
1.464 -// 8 MSC_CMD -
1.465 -// 9 MSC_CLK -
1.466 -// 10 MSC_D0 -
1.467 -// 11 MSC_D1 -
1.468 -// 12 MSC_D2 -
1.469 -// 13 MSC_D3 -
1.470 -// 14 CIM_MCLK -
1.471 -// 15 CIM_PCLK -
1.472 -// 16 CIM_VSYNC -
1.473 -// 17 CIM_HSYNC -
1.474 -// 18 SSI_CLK SCLK_RSTN
1.475 -// 19 SSI_CE0# BIT_CLK(AIC)
1.476 -// 20 SSI_DT SDATA_OUT(AIC)
1.477 -// 21 SSI_DR SDATA_IN(AIC)
1.478 -// 22 SSI_CE1#&GPC SYNC(AIC)
1.479 -// 23 PWM0 I2C_SDA
1.480 -// 24 PWM1 I2C_SCK
1.481 -// 25 PWM2 UART0_TxD
1.482 -// 26 PWM3 UART0_RxD
1.483 -// 27 PWM4 A17
1.484 -// 28 PWM5 A18
1.485 -// 29 - -
1.486 -// 30 PWM6 UART0_CTS/UART1_RxD
1.487 -// 31 PWM7 UART0_RTS/UART1_TxD
1.488 -//
1.489 -//////////////////////////////////////////////////////////
1.490 -
1.491 +
1.492 +/* GPIO Pins Description */
1.493 +/* PORT 0: */
1.494 +/* PIN/BIT N FUNC0 FUNC1 */
1.495 +/* 0 D0 - */
1.496 +/* 1 D1 - */
1.497 +/* 2 D2 - */
1.498 +/* 3 D3 - */
1.499 +/* 4 D4 - */
1.500 +/* 5 D5 - */
1.501 +/* 6 D6 - */
1.502 +/* 7 D7 - */
1.503 +/* 8 D8 - */
1.504 +/* 9 D9 - */
1.505 +/* 10 D10 - */
1.506 +/* 11 D11 - */
1.507 +/* 12 D12 - */
1.508 +/* 13 D13 - */
1.509 +/* 14 D14 - */
1.510 +/* 15 D15 - */
1.511 +/* 16 D16 - */
1.512 +/* 17 D17 - */
1.513 +/* 18 D18 - */
1.514 +/* 19 D19 - */
1.515 +/* 20 D20 - */
1.516 +/* 21 D21 - */
1.517 +/* 22 D22 - */
1.518 +/* 23 D23 - */
1.519 +/* 24 D24 - */
1.520 +/* 25 D25 - */
1.521 +/* 26 D26 - */
1.522 +/* 27 D27 - */
1.523 +/* 28 D28 - */
1.524 +/* 29 D29 - */
1.525 +/* 30 D30 - */
1.526 +/* 31 D31 - */
1.527 +/*------------------------------------------------------ */
1.528 +/* PORT 1: */
1.529 +/* */
1.530 +/* PIN/BIT N FUNC0 FUNC1 */
1.531 +/* 0 A0 - */
1.532 +/* 1 A1 - */
1.533 +/* 2 A2 - */
1.534 +/* 3 A3 - */
1.535 +/* 4 A4 - */
1.536 +/* 5 A5 - */
1.537 +/* 6 A6 - */
1.538 +/* 7 A7 - */
1.539 +/* 8 A8 - */
1.540 +/* 9 A9 - */
1.541 +/* 10 A10 - */
1.542 +/* 11 A11 - */
1.543 +/* 12 A12 - */
1.544 +/* 13 A13 - */
1.545 +/* 14 A14 - */
1.546 +/* 15 A15/CL - */
1.547 +/* 16 A16/AL - */
1.548 +/* 17 LCD_CLS A21 */
1.549 +/* 18 LCD_SPL A22 */
1.550 +/* 19 DCS# - */
1.551 +/* 20 RAS# - */
1.552 +/* 21 CAS# - */
1.553 +/* 22 RDWE#/BUFD# - */
1.554 +/* 23 CKE - */
1.555 +/* 24 CKO - */
1.556 +/* 25 CS1# - */
1.557 +/* 26 CS2# - */
1.558 +/* 27 CS3# - */
1.559 +/* 28 CS4# - */
1.560 +/* 29 RD# - */
1.561 +/* 30 WR# - */
1.562 +/* 31 WE0# - */
1.563 +/* Note: PIN15&16 are CL&AL when connecting to NAND flash. */
1.564 +/*------------------------------------------------------ */
1.565 +/* PORT 2: */
1.566 +/* */
1.567 +/* PIN/BIT N FUNC0 FUNC1 */
1.568 +/* 0 LCD_D0 - */
1.569 +/* 1 LCD_D1 - */
1.570 +/* 2 LCD_D2 - */
1.571 +/* 3 LCD_D3 - */
1.572 +/* 4 LCD_D4 - */
1.573 +/* 5 LCD_D5 - */
1.574 +/* 6 LCD_D6 - */
1.575 +/* 7 LCD_D7 - */
1.576 +/* 8 LCD_D8 - */
1.577 +/* 9 LCD_D9 - */
1.578 +/* 10 LCD_D10 - */
1.579 +/* 11 LCD_D11 - */
1.580 +/* 12 LCD_D12 - */
1.581 +/* 13 LCD_D13 - */
1.582 +/* 14 LCD_D14 - */
1.583 +/* 15 LCD_D15 - */
1.584 +/* 16 LCD_D16 - */
1.585 +/* 17 LCD_D17 - */
1.586 +/* 18 LCD_PCLK - */
1.587 +/* 19 LCD_HSYNC - */
1.588 +/* 20 LCD_VSYNC - */
1.589 +/* 21 LCD_DE - */
1.590 +/* 22 LCD_PS A19 */
1.591 +/* 23 LCD_REV A20 */
1.592 +/* 24 WE1# - */
1.593 +/* 25 WE2# - */
1.594 +/* 26 WE3# - */
1.595 +/* 27 WAIT# - */
1.596 +/* 28 FRE# - */
1.597 +/* 29 FWE# - */
1.598 +/* 30(NOTE:FRB#) - - */
1.599 +/* 31 - - */
1.600 +/* NOTE(1): PIN30 is used for FRB# when connecting to NAND flash. */
1.601 +/*------------------------------------------------------ */
1.602 +/* PORT 3: */
1.603 +/* */
1.604 +/* PIN/BIT N FUNC0 FUNC1 */
1.605 +/* 0 CIM_D0 - */
1.606 +/* 1 CIM_D1 - */
1.607 +/* 2 CIM_D2 - */
1.608 +/* 3 CIM_D3 - */
1.609 +/* 4 CIM_D4 - */
1.610 +/* 5 CIM_D5 - */
1.611 +/* 6 CIM_D6 - */
1.612 +/* 7 CIM_D7 - */
1.613 +/* 8 MSC_CMD - */
1.614 +/* 9 MSC_CLK - */
1.615 +/* 10 MSC_D0 - */
1.616 +/* 11 MSC_D1 - */
1.617 +/* 12 MSC_D2 - */
1.618 +/* 13 MSC_D3 - */
1.619 +/* 14 CIM_MCLK - */
1.620 +/* 15 CIM_PCLK - */
1.621 +/* 16 CIM_VSYNC - */
1.622 +/* 17 CIM_HSYNC - */
1.623 +/* 18 SSI_CLK SCLK_RSTN */
1.624 +/* 19 SSI_CE0# BIT_CLK(AIC) */
1.625 +/* 20 SSI_DT SDATA_OUT(AIC) */
1.626 +/* 21 SSI_DR SDATA_IN(AIC) */
1.627 +/* 22 SSI_CE1#&GPC SYNC(AIC) */
1.628 +/* 23 PWM0 I2C_SDA */
1.629 +/* 24 PWM1 I2C_SCK */
1.630 +/* 25 PWM2 UART0_TxD */
1.631 +/* 26 PWM3 UART0_RxD */
1.632 +/* 27 PWM4 A17 */
1.633 +/* 28 PWM5 A18 */
1.634 +/* 29 - - */
1.635 +/* 30 PWM6 UART0_CTS/UART1_RxD */
1.636 +/* 31 PWM7 UART0_RTS/UART1_TxD */
1.637 /*
1.638 * p is the port number (0,1,2,3)
1.639 * o is the pin offset (0-31) inside the port
1.640 * n is the absolute number of a pin (0-127), regardless of the port
1.641 */
1.642
1.643 -//-------------------------------------------
1.644 -// Function Pins Mode
1.645 +/* Function Pins Mode */
1.646
1.647 #define __gpio_as_func0(n) \
1.648 do { \
1.649 @@ -2674,9 +2595,9 @@
1.650
1.651 /*
1.652 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
1.653 - * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
1.654 + * RDWE#, CKO#, WE0#, WE1#
1.655 */
1.656 -#define __gpio_as_sdram_16bit() \
1.657 +#define __gpio_as_sdram_16bit_4720() \
1.658 do { \
1.659 REG_GPIO_PXFUNS(0) = 0x5442bfaa; \
1.660 REG_GPIO_PXSELC(0) = 0x5442bfaa; \
1.661 @@ -2690,6 +2611,24 @@
1.662 } while (0)
1.663
1.664 /*
1.665 + * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
1.666 + * RDWE#, CKO#, WE0#, WE1#
1.667 + */
1.668 +#define __gpio_as_sdram_16bit_4725() \
1.669 +do { \
1.670 + REG_GPIO_PXFUNS(0) = 0x0000ffff; \
1.671 + REG_GPIO_PXSELC(0) = 0x0000ffff; \
1.672 + REG_GPIO_PXPES(0) = 0x0000ffff; \
1.673 + REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
1.674 + REG_GPIO_PXSELC(1) = 0x81f9ffff; \
1.675 + REG_GPIO_PXPES(1) = 0x81f9ffff; \
1.676 + REG_GPIO_PXFUNS(2) = 0x01000000; \
1.677 + REG_GPIO_PXSELC(2) = 0x01000000; \
1.678 + REG_GPIO_PXPES(2) = 0x01000000; \
1.679 +} while (0)
1.680 +
1.681 +
1.682 +/*
1.683 * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD#
1.684 */
1.685 #define __gpio_as_nand() \
1.686 @@ -2768,6 +2707,11 @@
1.687 REG_GPIO_PXPES(3) = 0x06000000; \
1.688 } while (0)
1.689
1.690 +#define __gpio_jtag_to_uart0() \
1.691 +do { \
1.692 + REG_GPIO_PXSELS(2) = 0x80000000; \
1.693 +} while (0)
1.694 +
1.695 /*
1.696 * UART0_CTS, UART0_RTS
1.697 */
1.698 @@ -2810,6 +2754,34 @@
1.699 REG_GPIO_PXPES(2) = 0x003fffff; \
1.700 } while (0)
1.701
1.702 +
1.703 +/* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */
1.704 +#define __gpio_as_slcd_8bit() \
1.705 +do { \
1.706 + REG_GPIO_PXFUNS(2) = 0x001800ff; \
1.707 + REG_GPIO_PXSELC(2) = 0x001800ff; \
1.708 +} while (0)
1.709 +
1.710 +/* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */
1.711 +#define __gpio_as_slcd_9bit() \
1.712 +do { \
1.713 + REG_GPIO_PXFUNS(2) = 0x001801ff; \
1.714 + REG_GPIO_PXSELC(2) = 0x001801ff; \
1.715 +} while (0)
1.716 +
1.717 +/* LCD_D0~LCD_D15, SLCD_RS, SLCD_CS */
1.718 +#define __gpio_as_slcd_16bit() \
1.719 +do { \
1.720 + REG_GPIO_PXFUNS(2) = 0x0018ffff; \
1.721 + REG_GPIO_PXSELC(2) = 0x0018ffff; \
1.722 +} while (0)
1.723 +
1.724 +/* LCD_D0~LCD_D17, SLCD_RS, SLCD_CS */
1.725 +#define __gpio_as_slcd_18bit() \
1.726 +do { \
1.727 + REG_GPIO_PXFUNS(2) = 0x001bffff; \
1.728 + REG_GPIO_PXSELC(2) = 0x001bffff; \
1.729 +} while (0)
1.730 /*
1.731 * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC
1.732 */
1.733 @@ -2945,8 +2917,7 @@
1.734 */
1.735 #define __gpio_as_pwm(n) __gpio_as_pwm##n()
1.736
1.737 -//-------------------------------------------
1.738 -// GPIO or Interrupt Mode
1.739 +/* GPIO or Interrupt Mode */
1.740
1.741 #define __gpio_get_port(p) (REG_GPIO_PXPIN(p))
1.742
1.743 @@ -3239,12 +3210,13 @@
1.744 ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT)
1.745 #define __cpm_set_o1st(v) \
1.746 (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT)))
1.747 -#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND)
1.748 +#define __cpm_suspend_udcphy() (REG_CPM_SCR &= ~CPM_SCR_UDCPHY_ENABLE)
1.749 +#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_DISABLE)
1.750 #define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE)
1.751
1.752
1.753 -#ifdef CFG_EXTAL
1.754 -#define JZ_EXTAL CFG_EXTAL
1.755 +#ifdef CONFIG_SYS_EXTAL
1.756 +#define JZ_EXTAL CONFIG_SYS_EXTAL
1.757 #else
1.758 #define JZ_EXTAL 3686400
1.759 #endif
1.760 @@ -3377,10 +3349,10 @@
1.761 REG_CPM_MSCCDR = div - 1;
1.762 }
1.763
1.764 -/***************************************************************************
1.765 +/*
1.766 * TCU
1.767 - ***************************************************************************/
1.768 -// where 'n' is the TCU channel
1.769 + */
1.770 +/* where 'n' is the TCU channel */
1.771 #define __tcu_select_extalclk(n) \
1.772 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN)
1.773 #define __tcu_select_rtcclk(n) \
1.774 @@ -3852,9 +3824,7 @@
1.775 #define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC )
1.776 #define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC )
1.777
1.778 -//
1.779 -// Define next ops for AC97 compatible
1.780 -//
1.781 +/* Define next ops for AC97 compatible */
1.782
1.783 #define AC97_ACSR AIC_ACSR
1.784
1.785 @@ -3895,9 +3865,7 @@
1.786 #define __ac97_write_tfifo(v) __aic_write_tfifo(v)
1.787 #define __ac97_read_rfifo() __aic_read_rfifo()
1.788
1.789 -//
1.790 -// Define next ops for I2S compatible
1.791 -//
1.792 +/* Define next ops for I2S compatible */
1.793
1.794 #define I2S_ACSR AIC_I2SSR
1.795
1.796 @@ -4713,7 +4681,7 @@
1.797 REG_RTC_RSAR; \
1.798 }while(0)
1.799
1.800 -
1.801 +
1.802 #define __rtc_set_alarm_second(v) \
1.803 do{ \
1.804 while(!__rtc_write_ready()); \
1.805 @@ -4751,7 +4719,7 @@
1.806 #define __rtc_get_nc1Hz_val() \
1.807 while(!__rtc_write_ready()); \
1.808 ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT )
1.809 -
1.810 +
1.811 #define __rtc_set_nc1Hz_val(v) \
1.812 do{ \
1.813 while(!__rtc_write_ready()); \
1.814 @@ -4832,6 +4800,7 @@
1.815 (REG_RTC_HSPR = n ); \
1.816 }while(0)
1.817
1.818 +
1.819 #endif /* !__ASSEMBLY__ */
1.820
1.821 #endif /* __JZ4740_H__ */