1.1 --- a/stage2/head2.S Sun Jun 14 21:17:08 2015 +0200
1.2 +++ b/stage2/head2.S Sun Jun 14 21:32:05 2015 +0200
1.3 @@ -1,9 +1,23 @@
1.4 /*
1.5 - * Entry point of the firmware.
1.6 - * The firmware code are executed in the ICache.
1.7 - * Do not edit!
1.8 - * Copyright (C) 2006 Ingenic Semiconductor Inc.
1.9 + * Initialisation code for the stage 2 payload.
1.10 + *
1.11 + * Copyright 2009 (C) Qi Hardware Inc.
1.12 + * Author: Wolfgang Spraul <wolfgang@sharism.cc>
1.13 + *
1.14 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
1.15 *
1.16 + * This program is free software: you can redistribute it and/or modify
1.17 + * it under the terms of the GNU General Public License as published by
1.18 + * the Free Software Foundation, either version 3 of the License, or
1.19 + * (at your option) any later version.
1.20 + *
1.21 + * This program is distributed in the hope that it will be useful,
1.22 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.23 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.24 + * GNU General Public License for more details.
1.25 + *
1.26 + * You should have received a copy of the GNU General Public License
1.27 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
1.28 */
1.29
1.30 .text
1.31 @@ -12,7 +26,7 @@
1.32 .globl _start
1.33 .set noreorder
1.34 _start:
1.35 - add $29, $20, 0x3ffff0 // sp locate at start address offset 0x2ffff0
1.36 + add $29, $20, 0x3ffff0 /* sp */
1.37 j c_main
1.38
1.39 .set reorder