1.1 --- a/include/nanonote.h Fri Jun 05 00:08:05 2015 +0200
1.2 +++ b/include/nanonote.h Fri Jun 05 00:51:53 2015 +0200
1.3 @@ -13,170 +13,6 @@
1.4 #ifndef __CONFIG_NANONOTE_H
1.5 #define __CONFIG_NANONOTE_H
1.6
1.7 -#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
1.8 -#define CONFIG_JzRISC 1 /* JzRISC core */
1.9 -#define CONFIG_JZSOC 1 /* Jz SoC */
1.10 -#define CONFIG_JZ4740 1 /* Jz4740 SoC */
1.11 -#define CONFIG_NAND_JZ4740
1.12 -#define CONFIG_JZ4740_MMC
1.13 -#define CONFIG_NANONOTE
1.14 -
1.15 -#define BOOT_FROM_SDCARD 1
1.16 -#define BOOT_WITH_ENABLE_UART (1 << 1) /* Vaule for global_data.h gd->boot_option */
1.17 -
1.18 -#define CONFIG_LCD 1 /* LCD support */
1.19 -#define LCD_BPP LCD_COLOR32 /*5:18,24,32 bits per pixel */
1.20 -#define CONFIG_SYS_WHITE_ON_BLACK
1.21 -#define CONFIG_VIDEO_GPM940B0
1.22 -
1.23 -#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
1.24 -#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
1.25 -#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */
1.26 -#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED
1.27 -
1.28 -#define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */
1.29 -#define CONFIG_BAUDRATE 57600
1.30 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
1.31 -
1.32 -#define CONFIG_MMC 1
1.33 -#define CONFIG_FAT 1
1.34 -#define CONFIG_DOS_PARTITION 1
1.35 -#define CONFIG_SKIP_LOWLEVEL_INIT 1
1.36 -#define CONFIG_BOARD_EARLY_INIT_F 1
1.37 -#define CONFIG_SYS_NO_FLASH 1
1.38 -#define CONFIG_SYS_FLASH_BASE 0 /* init flash_base as 0 */
1.39 -#define CONFIG_ENV_OVERWRITE 1
1.40 -
1.41 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
1.42 -#define CONFIG_BOOTDELAY 0
1.43 -/*
1.44 - * Command line configuration.
1.45 - */
1.46 -#define CONFIG_CMD_BOOTD /* bootd */
1.47 -#define CONFIG_CMD_CONSOLE /* coninfo */
1.48 -#define CONFIG_CMD_ECHO /* echo arguments */
1.49 -
1.50 -#define CONFIG_CMD_LOADB /* loadb */
1.51 -#define CONFIG_CMD_LOADS /* loads */
1.52 -#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
1.53 -#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
1.54 -#define CONFIG_CMD_RUN /* run command in env variable */
1.55 -#define CONFIG_CMD_SAVEENV /* saveenv */
1.56 -#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
1.57 -#define CONFIG_CMD_SOURCE /* "source" command support */
1.58 -
1.59 -#define CONFIG_CMD_NAND
1.60 -#define CONFIG_CMD_MMC
1.61 -#define CONFIG_CMD_FAT
1.62 -#define CONFIG_CMD_EXT2
1.63 -
1.64 -/*
1.65 - * Serial download configuration
1.66 - */
1.67 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
1.68 -#define CONFIG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
1.69 -
1.70 -/*
1.71 - * Miscellaneous configurable options
1.72 - */
1.73 -#define CONFIG_SYS_LONGHELP /* undef to save memory */
1.74 -#define CONFIG_SYS_PROMPT "NanoNote# " /* Monitor Command Prompt */
1.75 -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
1.76 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
1.77 -/* Print Buffer Size */
1.78 -#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
1.79 -
1.80 -#define CONFIG_SYS_MALLOC_LEN 896 * 1024
1.81 -#define CONFIG_SYS_BOOTPARAMS_LEN 128 * 1024
1.82 -
1.83 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
1.84 -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
1.85 -#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */
1.86 -#define CONFIG_SYS_MEMTEST_START 0x80100000
1.87 -#define CONFIG_SYS_MEMTEST_END 0x80800000
1.88 -
1.89 -#define CONFIG_SILENT_CONSOLE 1 /* Enable support for silent boot */
1.90 -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* Enable output sink */
1.91 -
1.92 -/*
1.93 - * Environment
1.94 - */
1.95 -#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
1.96 -
1.97 -/*
1.98 - * NAND FLASH configuration
1.99 - */
1.100 -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
1.101 -
1.102 -/* NAND Boot config code */
1.103 -#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3
1.104 -
1.105 -#define NANONOTE_NAND_SIZE 2 /* if board nand flash is 1GB, set to 1
1.106 - * if board nand flash is 2GB, set to 2
1.107 - * for change the PAGE_SIZE and BLOCK_SIZE
1.108 - * will delete when there is no 1GB flash
1.109 - */
1.110 -
1.111 -#define CONFIG_SYS_NAND_PAGE_SIZE (2048 * NANONOTE_NAND_SIZE)
1.112 -/* nand chip block size */
1.113 -#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * NANONOTE_NAND_SIZE << 10)
1.114 -/* nand bad block was marked at this page in a block, start from 0 */
1.115 -#define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
1.116 -/* ECC offset position in oob area, default value is 6 if it isn't defined */
1.117 -#define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE)
1.118 -#define CONFIG_SYS_NAND_ECCSIZE 512
1.119 -#define CONFIG_SYS_NAND_ECCBYTES 9
1.120 -
1.121 -#define CONFIG_SYS_NAND_BASE 0xB8000000
1.122 -#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
1.123 -#define NAND_MAX_CHIPS 1
1.124 -#define CONFIG_SYS_MAX_NAND_DEVICE 1
1.125 -#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
1.126 -
1.127 -/*
1.128 - * IPL (Initial Program Loader, integrated inside CPU)
1.129 - * Will load first 8k from NAND (SPL) into cache and execute it from there.
1.130 - *
1.131 - * SPL (Secondary Program Loader)
1.132 - * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
1.133 - * has to fit into 8kByte. It sets up the CPU and configures the SDRAM
1.134 - * controller and the NAND controller so that the special U-Boot image can be
1.135 - * loaded from NAND to SDRAM.
1.136 - *
1.137 - * NUB (NAND U-Boot)
1.138 - * This NAND U-Boot (NUB) is a special U-Boot version which can be started
1.139 - * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
1.140 - *
1.141 - */
1.142 -#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
1.143 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
1.144 -/* Start NUB from this addr*/
1.145 -
1.146 -/*
1.147 - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
1.148 - */
1.149 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
1.150 -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
1.151 -
1.152 -#define CONFIG_ENV_SIZE (4 << 10)
1.153 -#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE)
1.154 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_SYS_NAND_BLOCK_SIZE)
1.155 -
1.156 -/* in board/nanonote/config.mk TEXT_BAS = 0x88000000 */
1.157 -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
1.158 -
1.159 -/*
1.160 - * SDRAM Info.
1.161 - */
1.162 -#define CONFIG_NR_DRAM_BANKS 1
1.163 -
1.164 -/*
1.165 - * Cache Configuration
1.166 - */
1.167 -#define CONFIG_SYS_DCACHE_SIZE 16384
1.168 -#define CONFIG_SYS_ICACHE_SIZE 16384
1.169 -#define CONFIG_SYS_CACHELINE_SIZE 32
1.170 -
1.171 /*
1.172 * GPIO definition
1.173 */