1 /* 2 * Initialisation code for the stage 2 payload. 3 * 4 * Copyright 2009 (C) Qi Hardware Inc. 5 * Author: Wolfgang Spraul <wolfgang@sharism.cc> 6 * 7 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation, either version 3 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "sdram.h" 24 25 .text 26 .extern c_main 27 .extern _tlb_entry 28 .extern _exc_entry 29 .extern _irq_entry 30 .extern _end_entries 31 .globl _start 32 .set noreorder 33 34 _start: 35 /* Initialise the stack. */ 36 37 la $sp, 0x80080000 38 39 /* Initialise the globals pointer. */ 40 41 lui $gp, %hi(_GLOBAL_OFFSET_TABLE_) 42 ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_) 43 44 /* Copy TLB handling instructions. */ 45 46 la $t0, _tlb_entry /* start */ 47 li $t1, 0x80000000 48 la $t2, _cache_entry /* end */ 49 _tlb_copy: 50 lw $t3, 0($t0) 51 addiu $t0, $t0, 4 52 sw $t3, 0($t1) 53 bne $t0, $t2, _tlb_copy 54 addiu $t1, $t1, 4 /* executed in delay slot before branch */ 55 56 /* Copy cache handling instructions. */ 57 58 move $t0, $t2 /* start */ 59 li $t1, 0x80000100 60 la $t2, _exc_entry /* end */ 61 _cache_copy: 62 lw $t3, 0($t0) 63 addiu $t0, $t0, 4 64 sw $t3, 0($t1) 65 bne $t0, $t2, _cache_copy 66 addiu $t1, $t1, 4 /* executed in delay slot before branch */ 67 68 /* Copy exception handling instructions. */ 69 70 move $t0, $t2 /* start */ 71 li $t1, 0x80000180 72 la $t2, _irq_entry /* end */ 73 _exc_copy: 74 lw $t3, 0($t0) 75 addiu $t0, $t0, 4 76 sw $t3, 0($t1) 77 bne $t0, $t2, _exc_copy 78 addiu $t1, $t1, 4 /* executed in delay slot before branch */ 79 80 /* Copy IRQ handling instructions. */ 81 82 move $t0, $t2 /* start */ 83 li $t1, 0x80000200 84 la $t2, _end_entries /* end */ 85 _irq_copy: 86 lw $t3, 0($t0) 87 addiu $t0, $t0, 4 88 sw $t3, 0($t1) 89 bne $t0, $t2, _irq_copy 90 addiu $t1, $t1, 4 /* executed in delay slot before branch */ 91 92 /* Enable caching. */ 93 94 li $t0, CONFIG_CM_CACHABLE_NONCOHERENT 95 mtc0 $t0, $16 /* CP0_CONFIG */ 96 nop 97 98 /* Start the program. */ 99 100 j c_main 101 nop 102 103 .set reorder