1 /* 2 * Include file for Ingenic Semiconductor's JZ4730 CPU. 3 * 4 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc. 5 * Copyright (C) 2009 Qi Hardware Inc. 6 * Author: Xiangfu Liu <xiangfu@sharism.cc> 7 * Copyright (C) 2015, 2017 Paul Boddie <paul@boddie.org.uk> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 22 * Boston, MA 02110-1301, USA 23 */ 24 25 #ifndef __JZ4730_H__ 26 #define __JZ4730_H__ 27 28 #include "xburst_types.h" 29 30 /* NOTE: Independent of usbboot parameters. */ 31 32 #define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ 33 #define CONFIG_SYS_EXTAL 3686400 /* EXTAL freq: 3.7 MHz */ 34 #define CONFIG_SYS_HZ (CONFIG_SYS_CPU_SPEED / (3*256)) /* incrementer freq */ 35 36 #define JZ_EXTAL CONFIG_SYS_EXTAL 37 #define JZ_EXTAL2 32768 /* RTC clock */ 38 39 /* Register Definitions */ 40 #define HARB_BASE 0xB3000000 41 #define EMC_BASE 0xB3010000 42 #define DMAC_BASE 0xB3020000 43 #define UHC_BASE 0xB3030000 44 #define UDC_BASE 0xB3040000 45 #define LCD_BASE 0xB3050000 46 #define CIM_BASE 0xB3060000 47 #define ETH_BASE 0xB3100000 48 #define NBM_BASE 0xB3F00000 49 50 #define CPM_BASE 0xB0000000 51 #define INTC_BASE 0xB0001000 52 #define OST_BASE 0xB0002000 53 #define RTC_BASE 0xB0003000 54 #define WDT_BASE 0xB0004000 55 #define GPIO_BASE 0xB0010000 56 #define AIC_BASE 0xB0020000 57 #define MSC_BASE 0xB0021000 58 #define UART0_BASE 0xB0030000 59 #define UART1_BASE 0xB0031000 60 #define UART2_BASE 0xB0032000 61 #define UART3_BASE 0xB0033000 62 #define FIR_BASE 0xB0040000 63 #define SCC_BASE 0xB0041000 64 #define SCC0_BASE 0xB0041000 65 #define I2C_BASE 0xB0042000 66 #define SSI_BASE 0xB0043000 67 #define SCC1_BASE 0xB0044000 68 #define PWM0_BASE 0xB0050000 69 #define PWM1_BASE 0xB0051000 70 #define DES_BASE 0xB0060000 71 #define UPRT_BASE 0xB0061000 72 #define KBC_BASE 0xB0062000 73 74 75 76 77 /************************************************************************* 78 * MSC 79 *************************************************************************/ 80 #define MSC_STRPCL (MSC_BASE + 0x000) 81 #define MSC_STAT (MSC_BASE + 0x004) 82 #define MSC_CLKRT (MSC_BASE + 0x008) 83 #define MSC_CMDAT (MSC_BASE + 0x00C) 84 #define MSC_RESTO (MSC_BASE + 0x010) 85 #define MSC_RDTO (MSC_BASE + 0x014) 86 #define MSC_BLKLEN (MSC_BASE + 0x018) 87 #define MSC_NOB (MSC_BASE + 0x01C) 88 #define MSC_SNOB (MSC_BASE + 0x020) 89 #define MSC_IMASK (MSC_BASE + 0x024) 90 #define MSC_IREG (MSC_BASE + 0x028) 91 #define MSC_CMD (MSC_BASE + 0x02C) 92 #define MSC_ARG (MSC_BASE + 0x030) 93 #define MSC_RES (MSC_BASE + 0x034) 94 #define MSC_RXFIFO (MSC_BASE + 0x038) 95 #define MSC_TXFIFO (MSC_BASE + 0x03C) 96 97 #define REG_MSC_STRPCL REG16(MSC_STRPCL) 98 #define REG_MSC_STAT REG32(MSC_STAT) 99 #define REG_MSC_CLKRT REG16(MSC_CLKRT) 100 #define REG_MSC_CMDAT REG32(MSC_CMDAT) 101 #define REG_MSC_RESTO REG16(MSC_RESTO) 102 #define REG_MSC_RDTO REG16(MSC_RDTO) 103 #define REG_MSC_BLKLEN REG16(MSC_BLKLEN) 104 #define REG_MSC_NOB REG16(MSC_NOB) 105 #define REG_MSC_SNOB REG16(MSC_SNOB) 106 #define REG_MSC_IMASK REG16(MSC_IMASK) 107 #define REG_MSC_IREG REG16(MSC_IREG) 108 #define REG_MSC_CMD REG8(MSC_CMD) 109 #define REG_MSC_ARG REG32(MSC_ARG) 110 #define REG_MSC_RES REG16(MSC_RES) 111 #define REG_MSC_RXFIFO REG32(MSC_RXFIFO) 112 #define REG_MSC_TXFIFO REG32(MSC_TXFIFO) 113 114 /* MSC Clock and Control Register (MSC_STRPCL) */ 115 116 #define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) 117 #define MSC_STRPCL_EXIT_TRANSFER (1 << 6) 118 #define MSC_STRPCL_START_READWAIT (1 << 5) 119 #define MSC_STRPCL_STOP_READWAIT (1 << 4) 120 #define MSC_STRPCL_RESET (1 << 3) 121 #define MSC_STRPCL_START_OP (1 << 2) 122 #define MSC_STRPCL_CLOCK_CONTROL_BIT 0 123 #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) 124 #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ 125 #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ 126 127 /* MSC Status Register (MSC_STAT) */ 128 129 #define MSC_STAT_IS_RESETTING (1 << 15) 130 #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) 131 #define MSC_STAT_PRG_DONE (1 << 13) 132 #define MSC_STAT_DATA_TRAN_DONE (1 << 12) 133 #define MSC_STAT_END_CMD_RES (1 << 11) 134 #define MSC_STAT_DATA_FIFO_AFULL (1 << 10) 135 #define MSC_STAT_IS_READWAIT (1 << 9) 136 #define MSC_STAT_CLK_EN (1 << 8) 137 #define MSC_STAT_DATA_FIFO_FULL (1 << 7) 138 #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) 139 #define MSC_STAT_CRC_RES_ERR (1 << 5) 140 #define MSC_STAT_CRC_READ_ERROR (1 << 4) 141 #define MSC_STAT_CRC_WRITE_ERROR_BIT 2 142 #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) 143 #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ 144 #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ 145 #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ 146 #define MSC_STAT_TIME_OUT_RES (1 << 1) 147 #define MSC_STAT_TIME_OUT_READ (1 << 0) 148 149 /* MSC Bus Clock Control Register (MSC_CLKRT) */ 150 151 #define MSC_CLKRT_CLK_RATE_BIT 0 152 #define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) 153 #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ 154 #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ 155 #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ 156 #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ 157 #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ 158 #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ 159 #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ 160 #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ 161 162 /* MSC Command Sequence Control Register (MSC_CMDAT) */ 163 164 #define MSC_CMDAT_IO_ABORT (1 << 11) 165 #define MSC_CMDAT_BUS_WIDTH_BIT 9 166 #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) 167 #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */ 168 #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */ 169 #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) 170 #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) 171 #define MSC_CMDAT_DMA_EN (1 << 8) 172 #define MSC_CMDAT_INIT (1 << 7) 173 #define MSC_CMDAT_BUSY (1 << 6) 174 #define MSC_CMDAT_STREAM_BLOCK (1 << 5) 175 #define MSC_CMDAT_WRITE (1 << 4) 176 #define MSC_CMDAT_READ (0 << 4) 177 #define MSC_CMDAT_DATA_EN (1 << 3) 178 #define MSC_CMDAT_RESPONSE_BIT 0 179 #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) 180 #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */ 181 #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */ 182 #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */ 183 #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */ 184 #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */ 185 #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */ 186 #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */ 187 188 #define CMDAT_DMA_EN (1 << 8) 189 #define CMDAT_INIT (1 << 7) 190 #define CMDAT_BUSY (1 << 6) 191 #define CMDAT_STREAM (1 << 5) 192 #define CMDAT_WRITE (1 << 4) 193 #define CMDAT_DATA_EN (1 << 3) 194 195 /* MSC Interrupts Mask Register (MSC_IMASK) */ 196 197 #define MSC_IMASK_SDIO (1 << 7) 198 #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) 199 #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) 200 #define MSC_IMASK_END_CMD_RES (1 << 2) 201 #define MSC_IMASK_PRG_DONE (1 << 1) 202 #define MSC_IMASK_DATA_TRAN_DONE (1 << 0) 203 204 205 /* MSC Interrupts Status Register (MSC_IREG) */ 206 207 #define MSC_IREG_SDIO (1 << 7) 208 #define MSC_IREG_TXFIFO_WR_REQ (1 << 6) 209 #define MSC_IREG_RXFIFO_RD_REQ (1 << 5) 210 #define MSC_IREG_END_CMD_RES (1 << 2) 211 #define MSC_IREG_PRG_DONE (1 << 1) 212 #define MSC_IREG_DATA_TRAN_DONE (1 << 0) 213 214 /************************************************************************* 215 * RTC 216 *************************************************************************/ 217 #define RTC_RCR (RTC_BASE + 0x00) 218 #define RTC_RSR (RTC_BASE + 0x04) 219 #define RTC_RSAR (RTC_BASE + 0x08) 220 #define RTC_RGR (RTC_BASE + 0x0c) 221 222 #define REG_RTC_RCR REG32(RTC_RCR) 223 #define REG_RTC_RSR REG32(RTC_RSR) 224 #define REG_RTC_RSAR REG32(RTC_RSAR) 225 #define REG_RTC_RGR REG32(RTC_RGR) 226 227 #define RTC_RCR_HZ (1 << 6) 228 #define RTC_RCR_HZIE (1 << 5) 229 #define RTC_RCR_AF (1 << 4) 230 #define RTC_RCR_AIE (1 << 3) 231 #define RTC_RCR_AE (1 << 2) 232 #define RTC_RCR_START (1 << 0) 233 234 #define RTC_RGR_LOCK (1 << 31) 235 #define RTC_RGR_ADJ_BIT 16 236 #define RTC_RGR_ADJ_MASK (0x3ff << RTC_RGR_ADJ_BIT) 237 #define RTC_RGR_DIV_BIT 0 238 #define RTC_REG_DIV_MASK (0xff << RTC_RGR_DIV_BIT) 239 240 241 242 243 /************************************************************************* 244 * FIR 245 *************************************************************************/ 246 #define FIR_TDR (FIR_BASE + 0x000) 247 #define FIR_RDR (FIR_BASE + 0x004) 248 #define FIR_TFLR (FIR_BASE + 0x008) 249 #define FIR_AR (FIR_BASE + 0x00C) 250 #define FIR_CR1 (FIR_BASE + 0x010) 251 #define FIR_CR2 (FIR_BASE + 0x014) 252 #define FIR_SR (FIR_BASE + 0x018) 253 254 #define REG_FIR_TDR REG8(FIR_TDR) 255 #define REG_FIR_RDR REG8(FIR_RDR) 256 #define REG_FIR_TFLR REG16(FIR_TFLR) 257 #define REG_FIR_AR REG8(FIR_AR) 258 #define REG_FIR_CR1 REG8(FIR_CR1) 259 #define REG_FIR_CR2 REG16(FIR_CR2) 260 #define REG_FIR_SR REG16(FIR_SR) 261 262 /* FIR Control Register 1 (FIR_CR1) */ 263 264 #define FIR_CR1_FIRUE (1 << 7) 265 #define FIR_CR1_ACE (1 << 6) 266 #define FIR_CR1_EOUS (1 << 5) 267 #define FIR_CR1_TIIE (1 << 4) 268 #define FIR_CR1_TFIE (1 << 3) 269 #define FIR_CR1_RFIE (1 << 2) 270 #define FIR_CR1_TXE (1 << 1) 271 #define FIR_CR1_RXE (1 << 0) 272 273 /* FIR Control Register 2 (FIR_CR2) */ 274 275 #define FIR_CR2_SIPE (1 << 10) 276 #define FIR_CR2_BCRC (1 << 9) 277 #define FIR_CR2_TFLRS (1 << 8) 278 #define FIR_CR2_ISS (1 << 7) 279 #define FIR_CR2_LMS (1 << 6) 280 #define FIR_CR2_TPPS (1 << 5) 281 #define FIR_CR2_RPPS (1 << 4) 282 #define FIR_CR2_TTRG_BIT 2 283 #define FIR_CR2_TTRG_MASK (0x3 << FIR_CR2_TTRG_BIT) 284 #define FIR_CR2_TTRG_16 (0 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 16 */ 285 #define FIR_CR2_TTRG_32 (1 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 32 */ 286 #define FIR_CR2_TTRG_64 (2 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 64 */ 287 #define FIR_CR2_TTRG_128 (3 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 128 */ 288 #define FIR_CR2_RTRG_BIT 0 289 #define FIR_CR2_RTRG_MASK (0x3 << FIR_CR2_RTRG_BIT) 290 #define FIR_CR2_RTRG_16 (0 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 16 */ 291 #define FIR_CR2_RTRG_32 (1 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 32 */ 292 #define FIR_CR2_RTRG_64 (2 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 64 */ 293 #define FIR_CR2_RTRG_128 (3 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 128 */ 294 295 /* FIR Status Register (FIR_SR) */ 296 297 #define FIR_SR_RFW (1 << 12) 298 #define FIR_SR_RFA (1 << 11) 299 #define FIR_SR_TFRTL (1 << 10) 300 #define FIR_SR_RFRTL (1 << 9) 301 #define FIR_SR_URUN (1 << 8) 302 #define FIR_SR_RFTE (1 << 7) 303 #define FIR_SR_ORUN (1 << 6) 304 #define FIR_SR_CRCE (1 << 5) 305 #define FIR_SR_FEND (1 << 4) 306 #define FIR_SR_TFF (1 << 3) 307 #define FIR_SR_RFE (1 << 2) 308 #define FIR_SR_TIDLE (1 << 1) 309 #define FIR_SR_RB (1 << 0) 310 311 312 313 314 /************************************************************************* 315 * SCC 316 *************************************************************************/ 317 #define SCC_DR(base) ((base) + 0x000) 318 #define SCC_FDR(base) ((base) + 0x004) 319 #define SCC_CR(base) ((base) + 0x008) 320 #define SCC_SR(base) ((base) + 0x00C) 321 #define SCC_TFR(base) ((base) + 0x010) 322 #define SCC_EGTR(base) ((base) + 0x014) 323 #define SCC_ECR(base) ((base) + 0x018) 324 #define SCC_RTOR(base) ((base) + 0x01C) 325 326 #define REG_SCC_DR(base) REG8(SCC_DR(base)) 327 #define REG_SCC_FDR(base) REG8(SCC_FDR(base)) 328 #define REG_SCC_CR(base) REG32(SCC_CR(base)) 329 #define REG_SCC_SR(base) REG16(SCC_SR(base)) 330 #define REG_SCC_TFR(base) REG16(SCC_TFR(base)) 331 #define REG_SCC_EGTR(base) REG8(SCC_EGTR(base)) 332 #define REG_SCC_ECR(base) REG32(SCC_ECR(base)) 333 #define REG_SCC_RTOR(base) REG8(SCC_RTOR(base)) 334 335 /* SCC FIFO Data Count Register (SCC_FDR) */ 336 337 #define SCC_FDR_EMPTY 0x00 338 #define SCC_FDR_FULL 0x10 339 340 /* SCC Control Register (SCC_CR) */ 341 342 #define SCC_CR_SCCE (1 << 31) 343 #define SCC_CR_TRS (1 << 30) 344 #define SCC_CR_T2R (1 << 29) 345 #define SCC_CR_FDIV_BIT 24 346 #define SCC_CR_FDIV_MASK (0x3 << SCC_CR_FDIV_BIT) 347 #define SCC_CR_FDIV_1 (0 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is the same as device clock */ 348 #define SCC_CR_FDIV_2 (1 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is half of device clock */ 349 #define SCC_CR_FLUSH (1 << 23) 350 #define SCC_CR_TRIG_BIT 16 351 #define SCC_CR_TRIG_MASK (0x3 << SCC_CR_TRIG_BIT) 352 #define SCC_CR_TRIG_1 (0 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 1 */ 353 #define SCC_CR_TRIG_4 (1 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 4 */ 354 #define SCC_CR_TRIG_8 (2 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 8 */ 355 #define SCC_CR_TRIG_14 (3 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 14 */ 356 #define SCC_CR_TP (1 << 15) 357 #define SCC_CR_CONV (1 << 14) 358 #define SCC_CR_TXIE (1 << 13) 359 #define SCC_CR_RXIE (1 << 12) 360 #define SCC_CR_TENDIE (1 << 11) 361 #define SCC_CR_RTOIE (1 << 10) 362 #define SCC_CR_ECIE (1 << 9) 363 #define SCC_CR_EPIE (1 << 8) 364 #define SCC_CR_RETIE (1 << 7) 365 #define SCC_CR_EOIE (1 << 6) 366 #define SCC_CR_TSEND (1 << 3) 367 #define SCC_CR_PX_BIT 1 368 #define SCC_CR_PX_MASK (0x3 << SCC_CR_PX_BIT) 369 #define SCC_CR_PX_NOT_SUPPORT (0 << SCC_CR_PX_BIT) /* SCC does not support clock stop */ 370 #define SCC_CR_PX_STOP_LOW (1 << SCC_CR_PX_BIT) /* SCC_CLK stops at state low */ 371 #define SCC_CR_PX_STOP_HIGH (2 << SCC_CR_PX_BIT) /* SCC_CLK stops at state high */ 372 #define SCC_CR_CLKSTP (1 << 0) 373 374 /* SCC Status Register (SCC_SR) */ 375 376 #define SCC_SR_TRANS (1 << 15) 377 #define SCC_SR_ORER (1 << 12) 378 #define SCC_SR_RTO (1 << 11) 379 #define SCC_SR_PER (1 << 10) 380 #define SCC_SR_TFTG (1 << 9) 381 #define SCC_SR_RFTG (1 << 8) 382 #define SCC_SR_TEND (1 << 7) 383 #define SCC_SR_RETR_3 (1 << 4) 384 #define SCC_SR_ECNTO (1 << 0) 385 386 387 388 389 /************************************************************************* 390 * ETH 391 *************************************************************************/ 392 #define ETH_BMR (ETH_BASE + 0x1000) 393 #define ETH_TPDR (ETH_BASE + 0x1004) 394 #define ETH_RPDR (ETH_BASE + 0x1008) 395 #define ETH_RAR (ETH_BASE + 0x100C) 396 #define ETH_TAR (ETH_BASE + 0x1010) 397 #define ETH_SR (ETH_BASE + 0x1014) 398 #define ETH_CR (ETH_BASE + 0x1018) 399 #define ETH_IER (ETH_BASE + 0x101C) 400 #define ETH_MFCR (ETH_BASE + 0x1020) 401 #define ETH_CTAR (ETH_BASE + 0x1050) 402 #define ETH_CRAR (ETH_BASE + 0x1054) 403 #define ETH_MCR (ETH_BASE + 0x0000) 404 #define ETH_MAHR (ETH_BASE + 0x0004) 405 #define ETH_MALR (ETH_BASE + 0x0008) 406 #define ETH_HTHR (ETH_BASE + 0x000C) 407 #define ETH_HTLR (ETH_BASE + 0x0010) 408 #define ETH_MIAR (ETH_BASE + 0x0014) 409 #define ETH_MIDR (ETH_BASE + 0x0018) 410 #define ETH_FCR (ETH_BASE + 0x001C) 411 #define ETH_VTR1 (ETH_BASE + 0x0020) 412 #define ETH_VTR2 (ETH_BASE + 0x0024) 413 #define ETH_WKFR (ETH_BASE + 0x0028) 414 #define ETH_PMTR (ETH_BASE + 0x002C) 415 416 #define REG_ETH_BMR REG32(ETH_BMR) 417 #define REG_ETH_TPDR REG32(ETH_TPDR) 418 #define REG_ETH_RPDR REG32(ETH_RPDR) 419 #define REG_ETH_RAR REG32(ETH_RAR) 420 #define REG_ETH_TAR REG32(ETH_TAR) 421 #define REG_ETH_SR REG32(ETH_SR) 422 #define REG_ETH_CR REG32(ETH_CR) 423 #define REG_ETH_IER REG32(ETH_IER) 424 #define REG_ETH_MFCR REG32(ETH_MFCR) 425 #define REG_ETH_CTAR REG32(ETH_CTAR) 426 #define REG_ETH_CRAR REG32(ETH_CRAR) 427 #define REG_ETH_MCR REG32(ETH_MCR) 428 #define REG_ETH_MAHR REG32(ETH_MAHR) 429 #define REG_ETH_MALR REG32(ETH_MALR) 430 #define REG_ETH_HTHR REG32(ETH_HTHR) 431 #define REG_ETH_HTLR REG32(ETH_HTLR) 432 #define REG_ETH_MIAR REG32(ETH_MIAR) 433 #define REG_ETH_MIDR REG32(ETH_MIDR) 434 #define REG_ETH_FCR REG32(ETH_FCR) 435 #define REG_ETH_VTR1 REG32(ETH_VTR1) 436 #define REG_ETH_VTR2 REG32(ETH_VTR2) 437 #define REG_ETH_WKFR REG32(ETH_WKFR) 438 #define REG_ETH_PMTR REG32(ETH_PMTR) 439 440 /* Bus Mode Register (ETH_BMR) */ 441 442 #define ETH_BMR_DBO (1 << 20) 443 #define ETH_BMR_PBL_BIT 8 444 #define ETH_BMR_PBL_MASK (0x3f << ETH_BMR_PBL_BIT) 445 #define ETH_BMR_PBL_1 (0x1 << ETH_BMR_PBL_BIT) 446 #define ETH_BMR_PBL_4 (0x4 << ETH_BMR_PBL_BIT) 447 #define ETH_BMR_BLE (1 << 7) 448 #define ETH_BMR_DSL_BIT 2 449 #define ETH_BMR_DSL_MASK (0x1f << ETH_BMR_DSL_BIT) 450 #define ETH_BMR_DSL_0 (0x0 << ETH_BMR_DSL_BIT) 451 #define ETH_BMR_DSL_1 (0x1 << ETH_BMR_DSL_BIT) 452 #define ETH_BMR_DSL_2 (0x2 << ETH_BMR_DSL_BIT) 453 #define ETH_BMR_DSL_4 (0x4 << ETH_BMR_DSL_BIT) 454 #define ETH_BMR_DSL_8 (0x8 << ETH_BMR_DSL_BIT) 455 #define ETH_BMR_SWR (1 << 0) 456 457 /* DMA Status Register (ETH_SR) */ 458 459 #define ETH_SR_EB_BIT 23 460 #define ETH_SR_EB_MASK (0x7 << ETH_SR_EB_BIT) 461 #define ETH_SR_EB_TX_ABORT (0x1 << ETH_SR_EB_BIT) 462 #define ETH_SR_EB_RX_ABORT (0x2 << ETH_SR_EB_BIT) 463 #define ETH_SR_TS_BIT 20 464 #define ETH_SR_TS_MASK (0x7 << ETH_SR_TS_BIT) 465 #define ETH_SR_TS_STOP (0x0 << ETH_SR_TS_BIT) 466 #define ETH_SR_TS_FTD (0x1 << ETH_SR_TS_BIT) 467 #define ETH_SR_TS_WEOT (0x2 << ETH_SR_TS_BIT) 468 #define ETH_SR_TS_QDAT (0x3 << ETH_SR_TS_BIT) 469 #define ETH_SR_TS_SUSPEND (0x6 << ETH_SR_TS_BIT) 470 #define ETH_SR_TS_CTD (0x7 << ETH_SR_TS_BIT) 471 #define ETH_SR_RS_BIT 17 472 #define ETH_SR_RS_MASK (0x7 << ETH_SR_RS_BIT) 473 #define ETH_SR_RS_STOP (0x0 << ETH_SR_RS_BIT) 474 #define ETH_SR_RS_FRD (0x1 << ETH_SR_RS_BIT) 475 #define ETH_SR_RS_CEOR (0x2 << ETH_SR_RS_BIT) 476 #define ETH_SR_RS_WRP (0x3 << ETH_SR_RS_BIT) 477 #define ETH_SR_RS_SUSPEND (0x4 << ETH_SR_RS_BIT) 478 #define ETH_SR_RS_CRD (0x5 << ETH_SR_RS_BIT) 479 #define ETH_SR_RS_FCF (0x6 << ETH_SR_RS_BIT) 480 #define ETH_SR_RS_QRF (0x7 << ETH_SR_RS_BIT) 481 #define ETH_SR_NIS (1 << 16) 482 #define ETH_SR_AIS (1 << 15) 483 #define ETH_SR_ERI (1 << 14) 484 #define ETH_SR_FBE (1 << 13) 485 #define ETH_SR_ETI (1 << 10) 486 #define ETH_SR_RWT (1 << 9) 487 #define ETH_SR_RPS (1 << 8) 488 #define ETH_SR_RU (1 << 7) 489 #define ETH_SR_RI (1 << 6) 490 #define ETH_SR_UNF (1 << 5) 491 #define ETH_SR_TJT (1 << 3) 492 #define ETH_SR_TU (1 << 2) 493 #define ETH_SR_TPS (1 << 1) 494 #define ETH_SR_TI (1 << 0) 495 496 /* Control (Operation Mode) Register (ETH_CR) */ 497 498 #define ETH_CR_TTM (1 << 22) 499 #define ETH_CR_SF (1 << 21) 500 #define ETH_CR_TR_BIT 14 501 #define ETH_CR_TR_MASK (0x3 << ETH_CR_TR_BIT) 502 #define ETH_CR_ST (1 << 13) 503 #define ETH_CR_OSF (1 << 2) 504 #define ETH_CR_SR (1 << 1) 505 506 /* Interrupt Enable Register (ETH_IER) */ 507 508 #define ETH_IER_NI (1 << 16) 509 #define ETH_IER_AI (1 << 15) 510 #define ETH_IER_ERE (1 << 14) 511 #define ETH_IER_FBE (1 << 13) 512 #define ETH_IER_ET (1 << 10) 513 #define ETH_IER_RWE (1 << 9) 514 #define ETH_IER_RS (1 << 8) 515 #define ETH_IER_RU (1 << 7) 516 #define ETH_IER_RI (1 << 6) 517 #define ETH_IER_UN (1 << 5) 518 #define ETH_IER_TJ (1 << 3) 519 #define ETH_IER_TU (1 << 2) 520 #define ETH_IER_TS (1 << 1) 521 #define ETH_IER_TI (1 << 0) 522 523 /* Missed Frame and Buffer Overflow Counter Register (ETH_MFCR) */ 524 525 #define ETH_MFCR_OVERFLOW_BIT 17 526 #define ETH_MFCR_OVERFLOW_MASK (0x7ff << ETH_MFCR_OVERFLOW_BIT) 527 #define ETH_MFCR_MFC_BIT 0 528 #define ETH_MFCR_MFC_MASK (0xffff << ETH_MFCR_MFC_BIT) 529 530 /* MAC Control Register (ETH_MCR) */ 531 532 #define ETH_MCR_RA (1 << 31) 533 #define ETH_MCR_HBD (1 << 28) 534 #define ETH_MCR_PS (1 << 27) 535 #define ETH_MCR_DRO (1 << 23) 536 #define ETH_MCR_OM_BIT 21 537 #define ETH_MCR_OM_MASK (0x3 << ETH_MCR_OM_BIT) 538 #define ETH_MCR_OM_NORMAL (0x0 << ETH_MCR_OM_BIT) 539 #define ETH_MCR_OM_INTERNAL (0x1 << ETH_MCR_OM_BIT) 540 #define ETH_MCR_OM_EXTERNAL (0x2 << ETH_MCR_OM_BIT) 541 #define ETH_MCR_F (1 << 20) 542 #define ETH_MCR_PM (1 << 19) 543 #define ETH_MCR_PR (1 << 18) 544 #define ETH_MCR_IF (1 << 17) 545 #define ETH_MCR_PB (1 << 16) 546 #define ETH_MCR_HO (1 << 15) 547 #define ETH_MCR_HP (1 << 13) 548 #define ETH_MCR_LCC (1 << 12) 549 #define ETH_MCR_DBF (1 << 11) 550 #define ETH_MCR_DTRY (1 << 10) 551 #define ETH_MCR_ASTP (1 << 8) 552 #define ETH_MCR_BOLMT_BIT 6 553 #define ETH_MCR_BOLMT_MASK (0x3 << ETH_MCR_BOLMT_BIT) 554 #define ETH_MCR_BOLMT_10 (0 << ETH_MCR_BOLMT_BIT) 555 #define ETH_MCR_BOLMT_8 (1 << ETH_MCR_BOLMT_BIT) 556 #define ETH_MCR_BOLMT_4 (2 << ETH_MCR_BOLMT_BIT) 557 #define ETH_MCR_BOLMT_1 (3 << ETH_MCR_BOLMT_BIT) 558 #define ETH_MCR_DC (1 << 5) 559 #define ETH_MCR_TE (1 << 3) 560 #define ETH_MCR_RE (1 << 2) 561 562 /* MII Address Register (ETH_MIAR) */ 563 564 #define ETH_MIAR_PHY_ADDR_BIT 11 565 #define ETH_MIAR_PHY_ADDR_MASK (0x1f << ETH_MIAR_PHY_ADDR_BIT) 566 #define ETH_MIAR_MII_REG_BIT 6 567 #define ETH_MIAR_MII_REG_MASK (0x1f << ETH_MIAR_MII_REG_BIT) 568 #define ETH_MIAR_MII_WRITE (1 << 1) 569 #define ETH_MIAR_MII_BUSY (1 << 0) 570 571 /* Flow Control Register (ETH_FCR) */ 572 573 #define ETH_FCR_PAUSE_TIME_BIT 16 574 #define ETH_FCR_PAUSE_TIME_MASK (0xffff << ETH_FCR_PAUSE_TIME_BIT) 575 #define ETH_FCR_PCF (1 << 2) 576 #define ETH_FCR_FCE (1 << 1) 577 #define ETH_FCR_BUSY (1 << 0) 578 579 /* PMT Control and Status Register (ETH_PMTR) */ 580 581 #define ETH_PMTR_GU (1 << 9) 582 #define ETH_PMTR_RF (1 << 6) 583 #define ETH_PMTR_MF (1 << 5) 584 #define ETH_PMTR_RWK (1 << 2) 585 #define ETH_PMTR_MPK (1 << 1) 586 587 /* Receive Descriptor 0 (ETH_RD0) Bits */ 588 589 #define ETH_RD0_OWN (1 << 31) 590 #define ETH_RD0_FF (1 << 30) 591 #define ETH_RD0_FL_BIT 16 592 #define ETH_RD0_FL_MASK (0x3fff << ETH_RD0_FL_BIT) 593 #define ETH_RD0_ES (1 << 15) 594 #define ETH_RD0_DE (1 << 14) 595 #define ETH_RD0_LE (1 << 12) 596 #define ETH_RD0_RF (1 << 11) 597 #define ETH_RD0_MF (1 << 10) 598 #define ETH_RD0_FD (1 << 9) 599 #define ETH_RD0_LD (1 << 8) 600 #define ETH_RD0_TL (1 << 7) 601 #define ETH_RD0_CS (1 << 6) 602 #define ETH_RD0_FT (1 << 5) 603 #define ETH_RD0_WT (1 << 4) 604 #define ETH_RD0_ME (1 << 3) 605 #define ETH_RD0_DB (1 << 2) 606 #define ETH_RD0_CE (1 << 1) 607 608 /* Receive Descriptor 1 (ETH_RD1) Bits */ 609 610 #define ETH_RD1_RER (1 << 25) 611 #define ETH_RD1_RCH (1 << 24) 612 #define ETH_RD1_RBS2_BIT 11 613 #define ETH_RD1_RBS2_MASK (0x7ff << ETH_RD1_RBS2_BIT) 614 #define ETH_RD1_RBS1_BIT 0 615 #define ETH_RD1_RBS1_MASK (0x7ff << ETH_RD1_RBS1_BIT) 616 617 /* Transmit Descriptor 0 (ETH_TD0) Bits */ 618 619 #define ETH_TD0_OWN (1 << 31) 620 #define ETH_TD0_FA (1 << 15) 621 #define ETH_TD0_LOC (1 << 11) 622 #define ETH_TD0_NC (1 << 10) 623 #define ETH_TD0_LC (1 << 9) 624 #define ETH_TD0_EC (1 << 8) 625 #define ETH_TD0_HBF (1 << 7) 626 #define ETH_TD0_CC_BIT 3 627 #define ETH_TD0_CC_MASK (0xf << ETH_TD0_CC_BIT) 628 #define ETH_TD0_ED (1 << 2) 629 #define ETH_TD0_UF (1 << 1) 630 #define ETH_TD0_DF (1 << 0) 631 632 /* Transmit Descriptor 1 (ETH_TD1) Bits */ 633 634 #define ETH_TD1_IC (1 << 31) 635 #define ETH_TD1_LS (1 << 30) 636 #define ETH_TD1_FS (1 << 29) 637 #define ETH_TD1_AC (1 << 26) 638 #define ETH_TD1_TER (1 << 25) 639 #define ETH_TD1_TCH (1 << 24) 640 #define ETH_TD1_DPD (1 << 23) 641 #define ETH_TD1_TBS2_BIT 11 642 #define ETH_TD1_TBS2_MASK (0x7ff << ETH_TD1_TBS2_BIT) 643 #define ETH_TD1_TBS1_BIT 0 644 #define ETH_TD1_TBS1_MASK (0x7ff << ETH_TD1_TBS1_BIT) 645 646 647 648 649 /************************************************************************* 650 * WDT 651 *************************************************************************/ 652 #define WDT_WTCSR (WDT_BASE + 0x00) 653 #define WDT_WTCNT (WDT_BASE + 0x04) 654 655 #define REG_WDT_WTCSR REG8(WDT_WTCSR) 656 #define REG_WDT_WTCNT REG32(WDT_WTCNT) 657 658 #define WDT_WTCSR_START (1 << 4) 659 660 661 662 663 /************************************************************************* 664 * OST 665 *************************************************************************/ 666 #define OST_TER (OST_BASE + 0x00) 667 #define OST_TRDR(n) (OST_BASE + 0x10 + ((n) * 0x20)) 668 #define OST_TCNT(n) (OST_BASE + 0x14 + ((n) * 0x20)) 669 #define OST_TCSR(n) (OST_BASE + 0x18 + ((n) * 0x20)) 670 #define OST_TCRB(n) (OST_BASE + 0x1c + ((n) * 0x20)) 671 672 #define REG_OST_TER REG8(OST_TER) 673 #define REG_OST_TRDR(n) REG32(OST_TRDR((n))) 674 #define REG_OST_TCNT(n) REG32(OST_TCNT((n))) 675 #define REG_OST_TCSR(n) REG16(OST_TCSR((n))) 676 #define REG_OST_TCRB(n) REG32(OST_TCRB((n))) 677 678 #define OST_TCSR_BUSY (1 << 7) 679 #define OST_TCSR_UF (1 << 6) 680 #define OST_TCSR_UIE (1 << 5) 681 #define OST_TCSR_CKS_BIT 0 682 #define OST_TCSR_CKS_MASK (0x07 << OST_TCSR_CKS_BIT) 683 #define OST_TCSR_CKS_PCLK_4 (0 << OST_TCSR_CKS_BIT) 684 #define OST_TCSR_CKS_PCLK_16 (1 << OST_TCSR_CKS_BIT) 685 #define OST_TCSR_CKS_PCLK_64 (2 << OST_TCSR_CKS_BIT) 686 #define OST_TCSR_CKS_PCLK_256 (3 << OST_TCSR_CKS_BIT) 687 #define OST_TCSR_CKS_RTCCLK (4 << OST_TCSR_CKS_BIT) 688 #define OST_TCSR_CKS_EXTAL (5 << OST_TCSR_CKS_BIT) 689 690 #define OST_TCSR0 OST_TCSR(0) 691 #define OST_TCSR1 OST_TCSR(1) 692 #define OST_TCSR2 OST_TCSR(2) 693 #define OST_TRDR0 OST_TRDR(0) 694 #define OST_TRDR1 OST_TRDR(1) 695 #define OST_TRDR2 OST_TRDR(2) 696 #define OST_TCNT0 OST_TCNT(0) 697 #define OST_TCNT1 OST_TCNT(1) 698 #define OST_TCNT2 OST_TCNT(2) 699 #define OST_TCRB0 OST_TCRB(0) 700 #define OST_TCRB1 OST_TCRB(1) 701 #define OST_TCRB2 OST_TCRB(2) 702 703 /************************************************************************* 704 * UART 705 *************************************************************************/ 706 707 #define IRDA_BASE UART0_BASE 708 #define UART_BASE UART0_BASE 709 #define UART_OFF 0x1000 710 711 /* register offset */ 712 #define OFF_RDR (0x00) /* R 8b H'xx */ 713 #define OFF_TDR (0x00) /* W 8b H'xx */ 714 #define OFF_DLLR (0x00) /* RW 8b H'00 */ 715 #define OFF_DLHR (0x04) /* RW 8b H'00 */ 716 #define OFF_IER (0x04) /* RW 8b H'00 */ 717 #define OFF_ISR (0x08) /* R 8b H'01 */ 718 #define OFF_FCR (0x08) /* W 8b H'00 */ 719 #define OFF_LCR (0x0C) /* RW 8b H'00 */ 720 #define OFF_MCR (0x10) /* RW 8b H'00 */ 721 #define OFF_LSR (0x14) /* R 8b H'00 */ 722 #define OFF_MSR (0x18) /* R 8b H'00 */ 723 #define OFF_SPR (0x1C) /* RW 8b H'00 */ 724 #define OFF_MCR (0x10) /* RW 8b H'00 */ 725 #define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ 726 727 /* register address */ 728 #define UART0_RDR (UART0_BASE + OFF_RDR) 729 #define UART0_TDR (UART0_BASE + OFF_TDR) 730 #define UART0_DLLR (UART0_BASE + OFF_DLLR) 731 #define UART0_DLHR (UART0_BASE + OFF_DLHR) 732 #define UART0_IER (UART0_BASE + OFF_IER) 733 #define UART0_ISR (UART0_BASE + OFF_ISR) 734 #define UART0_FCR (UART0_BASE + OFF_FCR) 735 #define UART0_LCR (UART0_BASE + OFF_LCR) 736 #define UART0_MCR (UART0_BASE + OFF_MCR) 737 #define UART0_LSR (UART0_BASE + OFF_LSR) 738 #define UART0_MSR (UART0_BASE + OFF_MSR) 739 #define UART0_SPR (UART0_BASE + OFF_SPR) 740 #define UART0_SIRCR (UART0_BASE + OFF_SIRCR) 741 742 #define UART1_RDR (UART1_BASE + OFF_RDR) 743 #define UART1_TDR (UART1_BASE + OFF_TDR) 744 #define UART1_DLLR (UART1_BASE + OFF_DLLR) 745 #define UART1_DLHR (UART1_BASE + OFF_DLHR) 746 #define UART1_IER (UART1_BASE + OFF_IER) 747 #define UART1_ISR (UART1_BASE + OFF_ISR) 748 #define UART1_FCR (UART1_BASE + OFF_FCR) 749 #define UART1_LCR (UART1_BASE + OFF_LCR) 750 #define UART1_MCR (UART1_BASE + OFF_MCR) 751 #define UART1_LSR (UART1_BASE + OFF_LSR) 752 #define UART1_MSR (UART1_BASE + OFF_MSR) 753 #define UART1_SPR (UART1_BASE + OFF_SPR) 754 #define UART1_SIRCR (UART1_BASE + OFF_SIRCR) 755 756 #define UART2_RDR (UART2_BASE + OFF_RDR) 757 #define UART2_TDR (UART2_BASE + OFF_TDR) 758 #define UART2_DLLR (UART2_BASE + OFF_DLLR) 759 #define UART2_DLHR (UART2_BASE + OFF_DLHR) 760 #define UART2_IER (UART2_BASE + OFF_IER) 761 #define UART2_ISR (UART2_BASE + OFF_ISR) 762 #define UART2_FCR (UART2_BASE + OFF_FCR) 763 #define UART2_LCR (UART2_BASE + OFF_LCR) 764 #define UART2_MCR (UART2_BASE + OFF_MCR) 765 #define UART2_LSR (UART2_BASE + OFF_LSR) 766 #define UART2_MSR (UART2_BASE + OFF_MSR) 767 #define UART2_SPR (UART2_BASE + OFF_SPR) 768 #define UART2_SIRCR (UART2_BASE + OFF_SIRCR) 769 770 #define UART3_RDR (UART3_BASE + OFF_RDR) 771 #define UART3_TDR (UART3_BASE + OFF_TDR) 772 #define UART3_DLLR (UART3_BASE + OFF_DLLR) 773 #define UART3_DLHR (UART3_BASE + OFF_DLHR) 774 #define UART3_IER (UART3_BASE + OFF_IER) 775 #define UART3_ISR (UART3_BASE + OFF_ISR) 776 #define UART3_FCR (UART3_BASE + OFF_FCR) 777 #define UART3_LCR (UART3_BASE + OFF_LCR) 778 #define UART3_MCR (UART3_BASE + OFF_MCR) 779 #define UART3_LSR (UART3_BASE + OFF_LSR) 780 #define UART3_MSR (UART3_BASE + OFF_MSR) 781 #define UART3_SPR (UART3_BASE + OFF_SPR) 782 #define UART3_SIRCR (UART3_BASE + OFF_SIRCR) 783 784 /* 785 * Define macros for UART_IER 786 * UART Interrupt Enable Register 787 */ 788 #define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ 789 #define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ 790 #define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ 791 #define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ 792 #define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ 793 794 /* 795 * Define macros for UART_ISR 796 * UART Interrupt Status Register 797 */ 798 #define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ 799 #define UART_ISR_IID (7 << 1) /* Source of Interrupt */ 800 #define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ 801 #define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ 802 #define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ 803 #define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ 804 #define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */ 805 #define UART_ISR_FFMS_NO_FIFO (0 << 6) 806 #define UART_ISR_FFMS_FIFO_MODE (3 << 6) 807 808 /* 809 * Define macros for UART_FCR 810 * UART FIFO Control Register 811 */ 812 #define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ 813 #define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ 814 #define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ 815 #define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ 816 #define UART_FCR_UUE (1 << 4) /* 0: disable UART */ 817 #define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ 818 #define UART_FCR_RTRG_1 (0 << 6) 819 #define UART_FCR_RTRG_4 (1 << 6) 820 #define UART_FCR_RTRG_8 (2 << 6) 821 #define UART_FCR_RTRG_15 (3 << 6) 822 823 /* 824 * Define macros for UART_LCR 825 * UART Line Control Register 826 */ 827 #define UART_LCR_WLEN (3 << 0) /* word length */ 828 #define UART_LCR_WLEN_5 (0 << 0) 829 #define UART_LCR_WLEN_6 (1 << 0) 830 #define UART_LCR_WLEN_7 (2 << 0) 831 #define UART_LCR_WLEN_8 (3 << 0) 832 #define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 833 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 834 #define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 835 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 836 #define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 837 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 838 839 #define UART_LCR_PE (1 << 3) /* 0: parity disable */ 840 #define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ 841 #define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ 842 #define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ 843 #define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ 844 845 /* 846 * Define macros for UART_LSR 847 * UART Line Status Register 848 */ 849 #define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ 850 #define UART_LSR_ORER (1 << 1) /* 0: no overrun error */ 851 #define UART_LSR_PER (1 << 2) /* 0: no parity error */ 852 #define UART_LSR_FER (1 << 3) /* 0; no framing error */ 853 #define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ 854 #define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ 855 #define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ 856 #define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ 857 858 /* 859 * Define macros for UART_MCR 860 * UART Modem Control Register 861 */ 862 #define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ 863 #define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ 864 #define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */ 865 #define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ 866 #define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ 867 #define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ 868 869 /* 870 * Define macros for UART_MSR 871 * UART Modem Status Register 872 */ 873 #define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */ 874 #define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */ 875 #define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */ 876 #define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */ 877 #define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ 878 #define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ 879 #define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ 880 #define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ 881 882 /* 883 * Define macros for SIRCR 884 * Slow IrDA Control Register 885 */ 886 #define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ 887 #define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ 888 #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length 889 1: 0 pulse width is 1.6us for 115.2Kbps */ 890 #define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ 891 #define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ 892 893 894 895 /************************************************************************* 896 * INTC 897 *************************************************************************/ 898 #define INTC_ISR (INTC_BASE + 0x00) 899 #define INTC_IMR (INTC_BASE + 0x04) 900 #define INTC_IMSR (INTC_BASE + 0x08) 901 #define INTC_IMCR (INTC_BASE + 0x0c) 902 #define INTC_IPR (INTC_BASE + 0x10) 903 904 #define REG_INTC_ISR REG32(INTC_ISR) 905 #define REG_INTC_IMR REG32(INTC_IMR) 906 #define REG_INTC_IMSR REG32(INTC_IMSR) 907 #define REG_INTC_IMCR REG32(INTC_IMCR) 908 #define REG_INTC_IPR REG32(INTC_IPR) 909 910 #define IRQ_I2C 1 911 #define IRQ_PS2 2 912 #define IRQ_UPRT 3 913 #define IRQ_CORE 4 914 #define IRQ_UART3 6 915 #define IRQ_UART2 7 916 #define IRQ_UART1 8 917 #define IRQ_UART0 9 918 #define IRQ_SCC1 10 919 #define IRQ_SCC0 11 920 #define IRQ_UDC 12 921 #define IRQ_UHC 13 922 #define IRQ_MSC 14 923 #define IRQ_RTC 15 924 #define IRQ_FIR 16 925 #define IRQ_SSI 17 926 #define IRQ_CIM 18 927 #define IRQ_ETH 19 928 #define IRQ_AIC 20 929 #define IRQ_DMAC 21 930 #define IRQ_OST2 22 931 #define IRQ_OST1 23 932 #define IRQ_OST0 24 933 #define IRQ_GPIO3 25 934 #define IRQ_GPIO2 26 935 #define IRQ_GPIO1 27 936 #define IRQ_GPIO0 28 937 #define IRQ_LCD 30 938 939 940 941 942 /************************************************************************* 943 * CIM 944 *************************************************************************/ 945 #define CIM_CFG (CIM_BASE + 0x0000) 946 #define CIM_CTRL (CIM_BASE + 0x0004) 947 #define CIM_STATE (CIM_BASE + 0x0008) 948 #define CIM_IID (CIM_BASE + 0x000C) 949 #define CIM_RXFIFO (CIM_BASE + 0x0010) 950 #define CIM_DA (CIM_BASE + 0x0020) 951 #define CIM_FA (CIM_BASE + 0x0024) 952 #define CIM_FID (CIM_BASE + 0x0028) 953 #define CIM_CMD (CIM_BASE + 0x002C) 954 955 #define REG_CIM_CFG REG32(CIM_CFG) 956 #define REG_CIM_CTRL REG32(CIM_CTRL) 957 #define REG_CIM_STATE REG32(CIM_STATE) 958 #define REG_CIM_IID REG32(CIM_IID) 959 #define REG_CIM_RXFIFO REG32(CIM_RXFIFO) 960 #define REG_CIM_DA REG32(CIM_DA) 961 #define REG_CIM_FA REG32(CIM_FA) 962 #define REG_CIM_FID REG32(CIM_FID) 963 #define REG_CIM_CMD REG32(CIM_CMD) 964 965 /* CIM Configuration Register (CIM_CFG) */ 966 967 #define CIM_CFG_INV_DAT (1 << 15) 968 #define CIM_CFG_VSP (1 << 14) 969 #define CIM_CFG_HSP (1 << 13) 970 #define CIM_CFG_PCP (1 << 12) 971 #define CIM_CFG_DUMMY_ZERO (1 << 9) 972 #define CIM_CFG_EXT_VSYNC (1 << 8) 973 #define CIM_CFG_PACK_BIT 4 974 #define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) 975 #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) 976 #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) 977 #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) 978 #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) 979 #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) 980 #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) 981 #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) 982 #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) 983 #define CIM_CFG_DSM_BIT 0 984 #define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) 985 #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ 986 #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ 987 #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ 988 #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ 989 990 /* CIM Control Register (CIM_CTRL) */ 991 992 #define CIM_CTRL_MCLKDIV_BIT 24 993 #define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) 994 #define CIM_CTRL_FRC_BIT 16 995 #define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) 996 #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ 997 #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ 998 #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ 999 #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ 1000 #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ 1001 #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ 1002 #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ 1003 #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ 1004 #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ 1005 #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ 1006 #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ 1007 #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ 1008 #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ 1009 #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ 1010 #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ 1011 #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ 1012 #define CIM_CTRL_VDDM (1 << 13) 1013 #define CIM_CTRL_DMA_SOFM (1 << 12) 1014 #define CIM_CTRL_DMA_EOFM (1 << 11) 1015 #define CIM_CTRL_DMA_STOPM (1 << 10) 1016 #define CIM_CTRL_RXF_TRIGM (1 << 9) 1017 #define CIM_CTRL_RXF_OFM (1 << 8) 1018 #define CIM_CTRL_RXF_TRIG_BIT 4 1019 #define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) 1020 #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ 1021 #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ 1022 #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ 1023 #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ 1024 #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ 1025 #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ 1026 #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ 1027 #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ 1028 #define CIM_CTRL_DMA_EN (1 << 2) 1029 #define CIM_CTRL_RXF_RST (1 << 1) 1030 #define CIM_CTRL_ENA (1 << 0) 1031 1032 /* CIM State Register (CIM_STATE) */ 1033 1034 #define CIM_STATE_DMA_SOF (1 << 6) 1035 #define CIM_STATE_DMA_EOF (1 << 5) 1036 #define CIM_STATE_DMA_STOP (1 << 4) 1037 #define CIM_STATE_RXF_OF (1 << 3) 1038 #define CIM_STATE_RXF_TRIG (1 << 2) 1039 #define CIM_STATE_RXF_EMPTY (1 << 1) 1040 #define CIM_STATE_VDD (1 << 0) 1041 1042 /* CIM DMA Command Register (CIM_CMD) */ 1043 1044 #define CIM_CMD_SOFINT (1 << 31) 1045 #define CIM_CMD_EOFINT (1 << 30) 1046 #define CIM_CMD_STOP (1 << 28) 1047 #define CIM_CMD_LEN_BIT 0 1048 #define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) 1049 1050 1051 1052 1053 /************************************************************************* 1054 * PWM 1055 *************************************************************************/ 1056 #define PWM_CTR(n) (PWM##n##_BASE + 0x000) 1057 #define PWM_PER(n) (PWM##n##_BASE + 0x004) 1058 #define PWM_DUT(n) (PWM##n##_BASE + 0x008) 1059 1060 #define REG_PWM_CTR(n) REG8(PWM_CTR(n)) 1061 #define REG_PWM_PER(n) REG16(PWM_PER(n)) 1062 #define REG_PWM_DUT(n) REG16(PWM_DUT(n)) 1063 1064 /* PWM Control Register (PWM_CTR) */ 1065 1066 #define PWM_CTR_EN (1 << 7) 1067 #define PWM_CTR_SD (1 << 6) 1068 #define PWM_CTR_PRESCALE_BIT 0 1069 #define PWM_CTR_PRESCALE_MASK (0x3f << PWM_CTR_PRESCALE_BIT) 1070 1071 /* PWM Period Register (PWM_PER) */ 1072 1073 #define PWM_PER_PERIOD_BIT 0 1074 #define PWM_PER_PERIOD_MASK (0x3ff << PWM_PER_PERIOD_BIT) 1075 1076 /* PWM Duty Register (PWM_DUT) */ 1077 1078 #define PWM_DUT_FDUTY (1 << 10) 1079 #define PWM_DUT_DUTY_BIT 0 1080 #define PWM_DUT_DUTY_MASK (0x3ff << PWM_DUT_DUTY_BIT) 1081 1082 1083 1084 1085 /************************************************************************* 1086 * EMC 1087 *************************************************************************/ 1088 #define EMC_BCR (EMC_BASE + 0x00) 1089 #define EMC_SMCR0 (EMC_BASE + 0x10) 1090 #define EMC_SMCR1 (EMC_BASE + 0x14) 1091 #define EMC_SMCR2 (EMC_BASE + 0x18) 1092 #define EMC_SMCR3 (EMC_BASE + 0x1c) 1093 #define EMC_SMCR4 (EMC_BASE + 0x20) 1094 #define EMC_SMCR5 (EMC_BASE + 0x24) 1095 #define EMC_SMCR6 (EMC_BASE + 0x28) 1096 #define EMC_SMCR7 (EMC_BASE + 0x2c) 1097 #define EMC_SACR0 (EMC_BASE + 0x30) 1098 #define EMC_SACR1 (EMC_BASE + 0x34) 1099 #define EMC_SACR2 (EMC_BASE + 0x38) 1100 #define EMC_SACR3 (EMC_BASE + 0x3c) 1101 #define EMC_SACR4 (EMC_BASE + 0x40) 1102 #define EMC_SACR5 (EMC_BASE + 0x44) 1103 #define EMC_SACR6 (EMC_BASE + 0x48) 1104 #define EMC_SACR7 (EMC_BASE + 0x4c) 1105 #define EMC_NFCSR (EMC_BASE + 0x50) 1106 #define EMC_NFECC (EMC_BASE + 0x54) 1107 #define EMC_PCCR1 (EMC_BASE + 0x60) 1108 #define EMC_PCCR2 (EMC_BASE + 0x64) 1109 #define EMC_PCCR3 (EMC_BASE + 0x68) 1110 #define EMC_PCCR4 (EMC_BASE + 0x6c) 1111 #define EMC_DMCR (EMC_BASE + 0x80) 1112 #define EMC_RTCSR (EMC_BASE + 0x84) 1113 #define EMC_RTCNT (EMC_BASE + 0x88) 1114 #define EMC_RTCOR (EMC_BASE + 0x8c) 1115 #define EMC_DMAR1 (EMC_BASE + 0x90) 1116 #define EMC_DMAR2 (EMC_BASE + 0x94) 1117 #define EMC_DMAR3 (EMC_BASE + 0x98) 1118 #define EMC_DMAR4 (EMC_BASE + 0x9c) 1119 1120 #define EMC_SDMR0 (EMC_BASE + 0xa000) 1121 #define EMC_SDMR1 (EMC_BASE + 0xb000) 1122 #define EMC_SDMR2 (EMC_BASE + 0xc000) 1123 #define EMC_SDMR3 (EMC_BASE + 0xd000) 1124 1125 /* NAND command/address/data port */ 1126 #define NAND_DATAPORT 0xB4000000 /* read-write area */ 1127 #define NAND_COMMPORT 0xB4040000 /* write only area */ 1128 #define NAND_ADDRPORT 0xB4080000 /* write only area */ 1129 1130 #define REG_EMC_BCR REG32(EMC_BCR) 1131 #define REG_EMC_SMCR0 REG32(EMC_SMCR0) 1132 #define REG_EMC_SMCR1 REG32(EMC_SMCR1) 1133 #define REG_EMC_SMCR2 REG32(EMC_SMCR2) 1134 #define REG_EMC_SMCR3 REG32(EMC_SMCR3) 1135 #define REG_EMC_SMCR4 REG32(EMC_SMCR4) 1136 #define REG_EMC_SMCR5 REG32(EMC_SMCR5) 1137 #define REG_EMC_SMCR6 REG32(EMC_SMCR6) 1138 #define REG_EMC_SMCR7 REG32(EMC_SMCR7) 1139 #define REG_EMC_SACR0 REG32(EMC_SACR0) 1140 #define REG_EMC_SACR1 REG32(EMC_SACR1) 1141 #define REG_EMC_SACR2 REG32(EMC_SACR2) 1142 #define REG_EMC_SACR3 REG32(EMC_SACR3) 1143 #define REG_EMC_SACR4 REG32(EMC_SACR4) 1144 #define REG_EMC_SACR5 REG32(EMC_SACR5) 1145 #define REG_EMC_SACR6 REG32(EMC_SACR6) 1146 #define REG_EMC_SACR7 REG32(EMC_SACR7) 1147 #define REG_EMC_NFCSR REG32(EMC_NFCSR) 1148 #define REG_EMC_NFECC REG32(EMC_NFECC) 1149 #define REG_EMC_DMCR REG32(EMC_DMCR) 1150 #define REG_EMC_RTCSR REG16(EMC_RTCSR) 1151 #define REG_EMC_RTCNT REG16(EMC_RTCNT) 1152 #define REG_EMC_RTCOR REG16(EMC_RTCOR) 1153 #define REG_EMC_DMAR1 REG32(EMC_DMAR1) 1154 #define REG_EMC_DMAR2 REG32(EMC_DMAR2) 1155 #define REG_EMC_DMAR3 REG32(EMC_DMAR3) 1156 #define REG_EMC_DMAR4 REG32(EMC_DMAR4) 1157 #define REG_EMC_PCCR1 REG32(EMC_PCCR1) 1158 #define REG_EMC_PCCR2 REG32(EMC_PCCR2) 1159 #define REG_EMC_PCCR3 REG32(EMC_PCCR3) 1160 #define REG_EMC_PCCR4 REG32(EMC_PCCR4) 1161 1162 1163 #define EMC_BCR_BRE (1 << 1) 1164 1165 #define EMC_SMCR_STRV_BIT 24 1166 #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) 1167 #define EMC_SMCR_TAW_BIT 20 1168 #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) 1169 #define EMC_SMCR_TBP_BIT 16 1170 #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) 1171 #define EMC_SMCR_TAH_BIT 12 1172 #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) 1173 #define EMC_SMCR_TAS_BIT 8 1174 #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) 1175 #define EMC_SMCR_BW_BIT 6 1176 #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) 1177 #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) 1178 #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) 1179 #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) 1180 #define EMC_SMCR_BCM (1 << 3) 1181 #define EMC_SMCR_BL_BIT 1 1182 #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) 1183 #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) 1184 #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) 1185 #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) 1186 #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) 1187 #define EMC_SMCR_SMT (1 << 0) 1188 1189 #define EMC_SACR_BASE_BIT 8 1190 #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) 1191 #define EMC_SACR_MASK_BIT 0 1192 #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) 1193 1194 #define EMC_NFCSR_RB (1 << 7) 1195 #define EMC_NFCSR_BOOT_SEL_BIT 4 1196 #define EMC_NFCSR_BOOT_SEL_MASK (0x07 << EMC_NFCSR_BOOT_SEL_BIT) 1197 #define EMC_NFCSR_ERST (1 << 3) 1198 #define EMC_NFCSR_ECCE (1 << 2) 1199 #define EMC_NFCSR_FCE (1 << 1) 1200 #define EMC_NFCSR_NFE (1 << 0) 1201 1202 #define EMC_NFECC_ECC2_BIT 16 1203 #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) 1204 #define EMC_NFECC_ECC1_BIT 8 1205 #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) 1206 #define EMC_NFECC_ECC0_BIT 0 1207 #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) 1208 1209 #define EMC_DMCR_BW_BIT 31 1210 #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) 1211 #define EMC_DMCR_BW_32 (0 << EMC_DMCR_BW_BIT) 1212 #define EMC_DMCR_BW_16 (1 << EMC_DMCR_BW_BIT) 1213 #define EMC_DMCR_CA_BIT 26 1214 #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) 1215 #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) 1216 #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) 1217 #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) 1218 #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) 1219 #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) 1220 #define EMC_DMCR_RMODE (1 << 25) 1221 #define EMC_DMCR_RFSH (1 << 24) 1222 #define EMC_DMCR_MRSET (1 << 23) 1223 #define EMC_DMCR_RA_BIT 20 1224 #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) 1225 #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) 1226 #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) 1227 #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) 1228 #define EMC_DMCR_BA_BIT 19 1229 #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) 1230 #define EMC_DMCR_BA_2 (0 << EMC_DMCR_BA_BIT) 1231 #define EMC_DMCR_BA_4 (1 << EMC_DMCR_BA_BIT) 1232 #define EMC_DMCR_PDM (1 << 18) 1233 #define EMC_DMCR_EPIN (1 << 17) 1234 #define EMC_DMCR_TRAS_BIT 13 1235 #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) 1236 #define EMC_DMCR_RCD_BIT 11 1237 #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) 1238 #define EMC_DMCR_TPC_BIT 8 1239 #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) 1240 #define EMC_DMCR_TRWL_BIT 5 1241 #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) 1242 #define EMC_DMCR_TRC_BIT 2 1243 #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) 1244 #define EMC_DMCR_TCL_BIT 0 1245 #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) 1246 #define EMC_DMCR_CASL_2 (1 << EMC_DMCR_TCL_BIT) 1247 #define EMC_DMCR_CASL_3 (2 << EMC_DMCR_TCL_BIT) 1248 1249 #define EMC_RTCSR_CMF (1 << 7) 1250 #define EMC_RTCSR_CKS_BIT 0 1251 #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) 1252 #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) 1253 #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) 1254 #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) 1255 #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) 1256 #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) 1257 #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) 1258 #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) 1259 #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) 1260 1261 #define EMC_DMAR_BASE_BIT 8 1262 #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) 1263 #define EMC_DMAR_MASK_BIT 0 1264 #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) 1265 1266 #define EMC_SDMR_BM (1 << 9) 1267 #define EMC_SDMR_OM_BIT 7 1268 #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) 1269 #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) 1270 #define EMC_SDMR_CAS_BIT 4 1271 #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) 1272 #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) 1273 #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) 1274 #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) 1275 #define EMC_SDMR_BT_BIT 3 1276 #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) 1277 #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) 1278 #define EMC_SDMR_BT_INTR (1 << EMC_SDMR_BT_BIT) 1279 #define EMC_SDMR_BL_BIT 0 1280 #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) 1281 #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) 1282 #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) 1283 #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) 1284 #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) 1285 1286 #define EMC_SDMR_CAS2_16BIT \ 1287 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) 1288 #define EMC_SDMR_CAS2_32BIT \ 1289 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) 1290 #define EMC_SDMR_CAS3_16BIT \ 1291 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) 1292 #define EMC_SDMR_CAS3_32BIT \ 1293 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) 1294 1295 #define EMC_PCCR12_AMW (1 << 31) 1296 #define EMC_PCCR12_AMAS_BIT 28 1297 #define EMC_PCCR12_AMAS_MASK (0x07 << EMC_PCCR12_AMAS_BIT) 1298 #define EMC_PCCR12_AMAH_BIT 24 1299 #define EMC_PCCR12_AMAH_MASK (0x07 << EMC_PCCR12_AMAH_BIT) 1300 #define EMC_PCCR12_AMPW_BIT 20 1301 #define EMC_PCCR12_AMPW_MASK (0x0f << EMC_PCCR12_AMPW_BIT) 1302 #define EMC_PCCR12_AMRT_BIT 16 1303 #define EMC_PCCR12_AMRT_MASK (0x0f << EMC_PCCR12_AMRT_BIT) 1304 #define EMC_PCCR12_CMW (1 << 15) 1305 #define EMC_PCCR12_CMAS_BIT 12 1306 #define EMC_PCCR12_CMAS_MASK (0x07 << EMC_PCCR12_CMAS_BIT) 1307 #define EMC_PCCR12_CMAH_BIT 8 1308 #define EMC_PCCR12_CMAH_MASK (0x07 << EMC_PCCR12_CMAH_BIT) 1309 #define EMC_PCCR12_CMPW_BIT 4 1310 #define EMC_PCCR12_CMPW_MASK (0x0f << EMC_PCCR12_CMPW_BIT) 1311 #define EMC_PCCR12_CMRT_BIT 0 1312 #define EMC_PCCR12_CMRT_MASK (0x07 << EMC_PCCR12_CMRT_BIT) 1313 1314 #define EMC_PCCR34_DRS_BIT 16 1315 #define EMC_PCCR34_DRS_MASK (0x03 << EMC_PCCR34_DRS_BIT) 1316 #define EMC_PCCR34_DRS_SPKR (1 << EMC_PCCR34_DRS_BIT) 1317 #define EMC_PCCR34_DRS_IOIS16 (2 << EMC_PCCR34_DRS_BIT) 1318 #define EMC_PCCR34_DRS_INPACK (3 << EMC_PCCR34_DRS_BIT) 1319 #define EMC_PCCR34_IOIS16 (1 << 15) 1320 #define EMC_PCCR34_IOW (1 << 14) 1321 #define EMC_PCCR34_TCB_BIT 12 1322 #define EMC_PCCR34_TCB_MASK (0x03 << EMC_PCCR34_TCB_BIT) 1323 #define EMC_PCCR34_IORT_BIT 8 1324 #define EMC_PCCR34_IORT_MASK (0x07 << EMC_PCCR34_IORT_BIT) 1325 #define EMC_PCCR34_IOAE_BIT 6 1326 #define EMC_PCCR34_IOAE_MASK (0x03 << EMC_PCCR34_IOAE_BIT) 1327 #define EMC_PCCR34_IOAE_NONE (0 << EMC_PCCR34_IOAE_BIT) 1328 #define EMC_PCCR34_IOAE_1 (1 << EMC_PCCR34_IOAE_BIT) 1329 #define EMC_PCCR34_IOAE_2 (2 << EMC_PCCR34_IOAE_BIT) 1330 #define EMC_PCCR34_IOAE_5 (3 << EMC_PCCR34_IOAE_BIT) 1331 #define EMC_PCCR34_IOAH_BIT 4 1332 #define EMC_PCCR34_IOAH_MASK (0x03 << EMC_PCCR34_IOAH_BIT) 1333 #define EMC_PCCR34_IOAH_NONE (0 << EMC_PCCR34_IOAH_BIT) 1334 #define EMC_PCCR34_IOAH_1 (1 << EMC_PCCR34_IOAH_BIT) 1335 #define EMC_PCCR34_IOAH_2 (2 << EMC_PCCR34_IOAH_BIT) 1336 #define EMC_PCCR34_IOAH_5 (3 << EMC_PCCR34_IOAH_BIT) 1337 #define EMC_PCCR34_IOPW_BIT 0 1338 #define EMC_PCCR34_IOPW_MASK (0x0f << EMC_PCCR34_IOPW_BIT) 1339 1340 1341 1342 1343 /************************************************************************* 1344 * GPIO 1345 *************************************************************************/ 1346 #define GPIO_GPDR(n) (GPIO_BASE + (0x00 + (n)*0x30)) 1347 #define GPIO_GPDIR(n) (GPIO_BASE + (0x04 + (n)*0x30)) 1348 #define GPIO_GPODR(n) (GPIO_BASE + (0x08 + (n)*0x30)) 1349 #define GPIO_GPPUR(n) (GPIO_BASE + (0x0c + (n)*0x30)) 1350 #define GPIO_GPALR(n) (GPIO_BASE + (0x10 + (n)*0x30)) 1351 #define GPIO_GPAUR(n) (GPIO_BASE + (0x14 + (n)*0x30)) 1352 #define GPIO_GPIDLR(n) (GPIO_BASE + (0x18 + (n)*0x30)) 1353 #define GPIO_GPIDUR(n) (GPIO_BASE + (0x1c + (n)*0x30)) 1354 #define GPIO_GPIER(n) (GPIO_BASE + (0x20 + (n)*0x30)) 1355 #define GPIO_GPIMR(n) (GPIO_BASE + (0x24 + (n)*0x30)) 1356 #define GPIO_GPFR(n) (GPIO_BASE + (0x28 + (n)*0x30)) 1357 1358 #define REG_GPIO_GPDR(n) REG32(GPIO_GPDR((n))) 1359 #define REG_GPIO_GPDIR(n) REG32(GPIO_GPDIR((n))) 1360 #define REG_GPIO_GPODR(n) REG32(GPIO_GPODR((n))) 1361 #define REG_GPIO_GPPUR(n) REG32(GPIO_GPPUR((n))) 1362 #define REG_GPIO_GPALR(n) REG32(GPIO_GPALR((n))) 1363 #define REG_GPIO_GPAUR(n) REG32(GPIO_GPAUR((n))) 1364 #define REG_GPIO_GPIDLR(n) REG32(GPIO_GPIDLR((n))) 1365 #define REG_GPIO_GPIDUR(n) REG32(GPIO_GPIDUR((n))) 1366 #define REG_GPIO_GPIER(n) REG32(GPIO_GPIER((n))) 1367 #define REG_GPIO_GPIMR(n) REG32(GPIO_GPIMR((n))) 1368 #define REG_GPIO_GPFR(n) REG32(GPIO_GPFR((n))) 1369 1370 #define GPIO_IRQ_LOLEVEL 0 1371 #define GPIO_IRQ_HILEVEL 1 1372 #define GPIO_IRQ_FALLEDG 2 1373 #define GPIO_IRQ_RAISEDG 3 1374 1375 #define IRQ_GPIO_0 48 1376 #define NUM_GPIO 100 1377 1378 #define GPIO_GPDR0 GPIO_GPDR(0) 1379 #define GPIO_GPDR1 GPIO_GPDR(1) 1380 #define GPIO_GPDR2 GPIO_GPDR(2) 1381 #define GPIO_GPDR3 GPIO_GPDR(3) 1382 #define GPIO_GPDIR0 GPIO_GPDIR(0) 1383 #define GPIO_GPDIR1 GPIO_GPDIR(1) 1384 #define GPIO_GPDIR2 GPIO_GPDIR(2) 1385 #define GPIO_GPDIR3 GPIO_GPDIR(3) 1386 #define GPIO_GPODR0 GPIO_GPODR(0) 1387 #define GPIO_GPODR1 GPIO_GPODR(1) 1388 #define GPIO_GPODR2 GPIO_GPODR(2) 1389 #define GPIO_GPODR3 GPIO_GPODR(3) 1390 #define GPIO_GPPUR0 GPIO_GPPUR(0) 1391 #define GPIO_GPPUR1 GPIO_GPPUR(1) 1392 #define GPIO_GPPUR2 GPIO_GPPUR(2) 1393 #define GPIO_GPPUR3 GPIO_GPPUR(3) 1394 #define GPIO_GPALR0 GPIO_GPALR(0) 1395 #define GPIO_GPALR1 GPIO_GPALR(1) 1396 #define GPIO_GPALR2 GPIO_GPALR(2) 1397 #define GPIO_GPALR3 GPIO_GPALR(3) 1398 #define GPIO_GPAUR0 GPIO_GPAUR(0) 1399 #define GPIO_GPAUR1 GPIO_GPAUR(1) 1400 #define GPIO_GPAUR2 GPIO_GPAUR(2) 1401 #define GPIO_GPAUR3 GPIO_GPAUR(3) 1402 #define GPIO_GPIDLR0 GPIO_GPIDLR(0) 1403 #define GPIO_GPIDLR1 GPIO_GPIDLR(1) 1404 #define GPIO_GPIDLR2 GPIO_GPIDLR(2) 1405 #define GPIO_GPIDLR3 GPIO_GPIDLR(3) 1406 #define GPIO_GPIDUR0 GPIO_GPIDUR(0) 1407 #define GPIO_GPIDUR1 GPIO_GPIDUR(1) 1408 #define GPIO_GPIDUR2 GPIO_GPIDUR(2) 1409 #define GPIO_GPIDUR3 GPIO_GPIDUR(3) 1410 #define GPIO_GPIER0 GPIO_GPIER(0) 1411 #define GPIO_GPIER1 GPIO_GPIER(1) 1412 #define GPIO_GPIER2 GPIO_GPIER(2) 1413 #define GPIO_GPIER3 GPIO_GPIER(3) 1414 #define GPIO_GPIMR0 GPIO_GPIMR(0) 1415 #define GPIO_GPIMR1 GPIO_GPIMR(1) 1416 #define GPIO_GPIMR2 GPIO_GPIMR(2) 1417 #define GPIO_GPIMR3 GPIO_GPIMR(3) 1418 #define GPIO_GPFR0 GPIO_GPFR(0) 1419 #define GPIO_GPFR1 GPIO_GPFR(1) 1420 #define GPIO_GPFR2 GPIO_GPFR(2) 1421 #define GPIO_GPFR3 GPIO_GPFR(3) 1422 1423 1424 /************************************************************************* 1425 * HARB 1426 *************************************************************************/ 1427 #define HARB_HAPOR (HARB_BASE + 0x000) 1428 #define HARB_HMCTR (HARB_BASE + 0x010) 1429 #define HARB_HME8H (HARB_BASE + 0x014) 1430 #define HARB_HMCR1 (HARB_BASE + 0x018) 1431 #define HARB_HMER2 (HARB_BASE + 0x01C) 1432 #define HARB_HMER3 (HARB_BASE + 0x020) 1433 #define HARB_HMLTR (HARB_BASE + 0x024) 1434 1435 #define REG_HARB_HAPOR REG32(HARB_HAPOR) 1436 #define REG_HARB_HMCTR REG32(HARB_HMCTR) 1437 #define REG_HARB_HME8H REG32(HARB_HME8H) 1438 #define REG_HARB_HMCR1 REG32(HARB_HMCR1) 1439 #define REG_HARB_HMER2 REG32(HARB_HMER2) 1440 #define REG_HARB_HMER3 REG32(HARB_HMER3) 1441 #define REG_HARB_HMLTR REG32(HARB_HMLTR) 1442 1443 /* HARB Priority Order Register (HARB_HAPOR) */ 1444 1445 #define HARB_HAPOR_UCHSEL (1 << 7) 1446 #define HARB_HAPOR_PRIO_BIT 0 1447 #define HARB_HAPOR_PRIO_MASK (0xf << HARB_HAPOR_PRIO_BIT) 1448 1449 /* AHB Monitor Control Register (HARB_HMCTR) */ 1450 1451 #define HARB_HMCTR_HET3_BIT 20 1452 #define HARB_HMCTR_HET3_MASK (0xf << HARB_HMCTR_HET3_BIT) 1453 #define HARB_HMCTR_HMS3_BIT 16 1454 #define HARB_HMCTR_HMS3_MASK (0xf << HARB_HMCTR_HMS3_BIT) 1455 #define HARB_HMCTR_HET2_BIT 12 1456 #define HARB_HMCTR_HET2_MASK (0xf << HARB_HMCTR_HET2_BIT) 1457 #define HARB_HMCTR_HMS2_BIT 8 1458 #define HARB_HMCTR_HMS2_MASK (0xf << HARB_HMCTR_HMS2_BIT) 1459 #define HARB_HMCTR_HOVF3 (1 << 7) 1460 #define HARB_HMCTR_HOVF2 (1 << 6) 1461 #define HARB_HMCTR_HOVF1 (1 << 5) 1462 #define HARB_HMCTR_HRST (1 << 4) 1463 #define HARB_HMCTR_HEE3 (1 << 2) 1464 #define HARB_HMCTR_HEE2 (1 << 1) 1465 #define HARB_HMCTR_HEE1 (1 << 0) 1466 1467 /* AHB Monitor Event 8bits High Register (HARB_HME8H) */ 1468 1469 #define HARB_HME8H_HC8H1_BIT 16 1470 #define HARB_HME8H_HC8H1_MASK (0xff << HARB_HME8H_HC8H1_BIT) 1471 #define HARB_HME8H_HC8H2_BIT 8 1472 #define HARB_HME8H_HC8H2_MASK (0xff << HARB_HME8H_HC8H2_BIT) 1473 #define HARB_HME8H_HC8H3_BIT 0 1474 #define HARB_HME8H_HC8H3_MASK (0xff << HARB_HME8H_HC8H3_BIT) 1475 1476 /* AHB Monitor Latency Register (HARB_HMLTR) */ 1477 1478 #define HARB_HMLTR_HLT2_BIT 16 1479 #define HARB_HMLTR_HLT2_MASK (0xffff << HARB_HMLTR_HLT2_BIT) 1480 #define HARB_HMLTR_HLT3_BIT 0 1481 #define HARB_HMLTR_HLT3_MASK (0xffff << HARB_HMLTR_HLT3_BIT) 1482 1483 1484 1485 1486 /************************************************************************* 1487 * I2C 1488 *************************************************************************/ 1489 #define I2C_DR (I2C_BASE + 0x000) 1490 #define I2C_CR (I2C_BASE + 0x004) 1491 #define I2C_SR (I2C_BASE + 0x008) 1492 #define I2C_GR (I2C_BASE + 0x00C) 1493 1494 #define REG_I2C_DR REG8(I2C_DR) 1495 #define REG_I2C_CR REG8(I2C_CR) 1496 #define REG_I2C_SR REG8(I2C_SR) 1497 #define REG_I2C_GR REG16(I2C_GR) 1498 1499 /* I2C Control Register (I2C_CR) */ 1500 1501 #define I2C_CR_IEN (1 << 4) 1502 #define I2C_CR_STA (1 << 3) 1503 #define I2C_CR_STO (1 << 2) 1504 #define I2C_CR_AC (1 << 1) 1505 #define I2C_CR_I2CE (1 << 0) 1506 1507 /* I2C Status Register (I2C_SR) */ 1508 1509 #define I2C_SR_STX (1 << 4) 1510 #define I2C_SR_BUSY (1 << 3) 1511 #define I2C_SR_TEND (1 << 2) 1512 #define I2C_SR_DRF (1 << 1) 1513 #define I2C_SR_ACKF (1 << 0) 1514 1515 1516 1517 1518 /************************************************************************* 1519 * UDC 1520 *************************************************************************/ 1521 #define UDC_EP0InCR (UDC_BASE + 0x00) 1522 #define UDC_EP0InSR (UDC_BASE + 0x04) 1523 #define UDC_EP0InBSR (UDC_BASE + 0x08) 1524 #define UDC_EP0InMPSR (UDC_BASE + 0x0c) 1525 #define UDC_EP0InDesR (UDC_BASE + 0x14) 1526 #define UDC_EP1InCR (UDC_BASE + 0x20) 1527 #define UDC_EP1InSR (UDC_BASE + 0x24) 1528 #define UDC_EP1InBSR (UDC_BASE + 0x28) 1529 #define UDC_EP1InMPSR (UDC_BASE + 0x2c) 1530 #define UDC_EP1InDesR (UDC_BASE + 0x34) 1531 #define UDC_EP2InCR (UDC_BASE + 0x40) 1532 #define UDC_EP2InSR (UDC_BASE + 0x44) 1533 #define UDC_EP2InBSR (UDC_BASE + 0x48) 1534 #define UDC_EP2InMPSR (UDC_BASE + 0x4c) 1535 #define UDC_EP2InDesR (UDC_BASE + 0x54) 1536 #define UDC_EP3InCR (UDC_BASE + 0x60) 1537 #define UDC_EP3InSR (UDC_BASE + 0x64) 1538 #define UDC_EP3InBSR (UDC_BASE + 0x68) 1539 #define UDC_EP3InMPSR (UDC_BASE + 0x6c) 1540 #define UDC_EP3InDesR (UDC_BASE + 0x74) 1541 #define UDC_EP4InCR (UDC_BASE + 0x80) 1542 #define UDC_EP4InSR (UDC_BASE + 0x84) 1543 #define UDC_EP4InBSR (UDC_BASE + 0x88) 1544 #define UDC_EP4InMPSR (UDC_BASE + 0x8c) 1545 #define UDC_EP4InDesR (UDC_BASE + 0x94) 1546 1547 #define UDC_EP0OutCR (UDC_BASE + 0x200) 1548 #define UDC_EP0OutSR (UDC_BASE + 0x204) 1549 #define UDC_EP0OutPFNR (UDC_BASE + 0x208) 1550 #define UDC_EP0OutMPSR (UDC_BASE + 0x20c) 1551 #define UDC_EP0OutSBPR (UDC_BASE + 0x210) 1552 #define UDC_EP0OutDesR (UDC_BASE + 0x214) 1553 #define UDC_EP5OutCR (UDC_BASE + 0x2a0) 1554 #define UDC_EP5OutSR (UDC_BASE + 0x2a4) 1555 #define UDC_EP5OutPFNR (UDC_BASE + 0x2a8) 1556 #define UDC_EP5OutMPSR (UDC_BASE + 0x2ac) 1557 #define UDC_EP5OutDesR (UDC_BASE + 0x2b4) 1558 #define UDC_EP6OutCR (UDC_BASE + 0x2c0) 1559 #define UDC_EP6OutSR (UDC_BASE + 0x2c4) 1560 #define UDC_EP6OutPFNR (UDC_BASE + 0x2c8) 1561 #define UDC_EP6OutMPSR (UDC_BASE + 0x2cc) 1562 #define UDC_EP6OutDesR (UDC_BASE + 0x2d4) 1563 #define UDC_EP7OutCR (UDC_BASE + 0x2e0) 1564 #define UDC_EP7OutSR (UDC_BASE + 0x2e4) 1565 #define UDC_EP7OutPFNR (UDC_BASE + 0x2e8) 1566 #define UDC_EP7OutMPSR (UDC_BASE + 0x2ec) 1567 #define UDC_EP7OutDesR (UDC_BASE + 0x2f4) 1568 1569 #define UDC_DevCFGR (UDC_BASE + 0x400) 1570 #define UDC_DevCR (UDC_BASE + 0x404) 1571 #define UDC_DevSR (UDC_BASE + 0x408) 1572 #define UDC_DevIntR (UDC_BASE + 0x40c) 1573 #define UDC_DevIntMR (UDC_BASE + 0x410) 1574 #define UDC_EPIntR (UDC_BASE + 0x414) 1575 #define UDC_EPIntMR (UDC_BASE + 0x418) 1576 1577 #define UDC_STCMAR (UDC_BASE + 0x500) 1578 #define UDC_EP0InfR (UDC_BASE + 0x504) 1579 #define UDC_EP1InfR (UDC_BASE + 0x508) 1580 #define UDC_EP2InfR (UDC_BASE + 0x50c) 1581 #define UDC_EP3InfR (UDC_BASE + 0x510) 1582 #define UDC_EP4InfR (UDC_BASE + 0x514) 1583 #define UDC_EP5InfR (UDC_BASE + 0x518) 1584 #define UDC_EP6InfR (UDC_BASE + 0x51c) 1585 #define UDC_EP7InfR (UDC_BASE + 0x520) 1586 1587 #define UDC_TXCONFIRM (UDC_BASE + 0x41C) 1588 #define UDC_TXZLP (UDC_BASE + 0x420) 1589 #define UDC_RXCONFIRM (UDC_BASE + 0x41C) 1590 1591 #define UDC_RXFIFO (UDC_BASE + 0x800) 1592 #define UDC_TXFIFOEP0 (UDC_BASE + 0x840) 1593 1594 #define REG_UDC_EP0InCR REG32(UDC_EP0InCR) 1595 #define REG_UDC_EP0InSR REG32(UDC_EP0InSR) 1596 #define REG_UDC_EP0InBSR REG32(UDC_EP0InBSR) 1597 #define REG_UDC_EP0InMPSR REG32(UDC_EP0InMPSR) 1598 #define REG_UDC_EP0InDesR REG32(UDC_EP0InDesR) 1599 #define REG_UDC_EP1InCR REG32(UDC_EP1InCR) 1600 #define REG_UDC_EP1InSR REG32(UDC_EP1InSR) 1601 #define REG_UDC_EP1InBSR REG32(UDC_EP1InBSR) 1602 #define REG_UDC_EP1InMPSR REG32(UDC_EP1InMPSR) 1603 #define REG_UDC_EP1InDesR REG32(UDC_EP1InDesR) 1604 #define REG_UDC_EP2InCR REG32(UDC_EP2InCR) 1605 #define REG_UDC_EP2InSR REG32(UDC_EP2InSR) 1606 #define REG_UDC_EP2InBSR REG32(UDC_EP2InBSR) 1607 #define REG_UDC_EP2InMPSR REG32(UDC_EP2InMPSR) 1608 #define REG_UDC_EP2InDesR REG32(UDC_EP2InDesR) 1609 #define REG_UDC_EP3InCR REG32(UDC_EP3InCR) 1610 #define REG_UDC_EP3InSR REG32(UDC_EP3InSR) 1611 #define REG_UDC_EP3InBSR REG32(UDC_EP3InBSR) 1612 #define REG_UDC_EP3InMPSR REG32(UDC_EP3InMPSR) 1613 #define REG_UDC_EP3InDesR REG32(UDC_EP3InDesR) 1614 #define REG_UDC_EP4InCR REG32(UDC_EP4InCR) 1615 #define REG_UDC_EP4InSR REG32(UDC_EP4InSR) 1616 #define REG_UDC_EP4InBSR REG32(UDC_EP4InBSR) 1617 #define REG_UDC_EP4InMPSR REG32(UDC_EP4InMPSR) 1618 #define REG_UDC_EP4InDesR REG32(UDC_EP4InDesR) 1619 1620 #define REG_UDC_EP0OutCR REG32(UDC_EP0OutCR) 1621 #define REG_UDC_EP0OutSR REG32(UDC_EP0OutSR) 1622 #define REG_UDC_EP0OutPFNR REG32(UDC_EP0OutPFNR) 1623 #define REG_UDC_EP0OutMPSR REG32(UDC_EP0OutMPSR) 1624 #define REG_UDC_EP0OutSBPR REG32(UDC_EP0OutSBPR) 1625 #define REG_UDC_EP0OutDesR REG32(UDC_EP0OutDesR) 1626 #define REG_UDC_EP5OutCR REG32(UDC_EP5OutCR) 1627 #define REG_UDC_EP5OutSR REG32(UDC_EP5OutSR) 1628 #define REG_UDC_EP5OutPFNR REG32(UDC_EP5OutPFNR) 1629 #define REG_UDC_EP5OutMPSR REG32(UDC_EP5OutMPSR) 1630 #define REG_UDC_EP5OutDesR REG32(UDC_EP5OutDesR) 1631 #define REG_UDC_EP6OutCR REG32(UDC_EP6OutCR) 1632 #define REG_UDC_EP6OutSR REG32(UDC_EP6OutSR) 1633 #define REG_UDC_EP6OutPFNR REG32(UDC_EP6OutPFNR) 1634 #define REG_UDC_EP6OutMPSR REG32(UDC_EP6OutMPSR) 1635 #define REG_UDC_EP6OutDesR REG32(UDC_EP6OutDesR) 1636 #define REG_UDC_EP7OutCR REG32(UDC_EP7OutCR) 1637 #define REG_UDC_EP7OutSR REG32(UDC_EP7OutSR) 1638 #define REG_UDC_EP7OutPFNR REG32(UDC_EP7OutPFNR) 1639 #define REG_UDC_EP7OutMPSR REG32(UDC_EP7OutMPSR) 1640 #define REG_UDC_EP7OutDesR REG32(UDC_EP7OutDesR) 1641 1642 #define REG_UDC_DevCFGR REG32(UDC_DevCFGR) 1643 #define REG_UDC_DevCR REG32(UDC_DevCR) 1644 #define REG_UDC_DevSR REG32(UDC_DevSR) 1645 #define REG_UDC_DevIntR REG32(UDC_DevIntR) 1646 #define REG_UDC_DevIntMR REG32(UDC_DevIntMR) 1647 #define REG_UDC_EPIntR REG32(UDC_EPIntR) 1648 #define REG_UDC_EPIntMR REG32(UDC_EPIntMR) 1649 1650 #define REG_UDC_STCMAR REG32(UDC_STCMAR) 1651 #define REG_UDC_EP0InfR REG32(UDC_EP0InfR) 1652 #define REG_UDC_EP1InfR REG32(UDC_EP1InfR) 1653 #define REG_UDC_EP2InfR REG32(UDC_EP2InfR) 1654 #define REG_UDC_EP3InfR REG32(UDC_EP3InfR) 1655 #define REG_UDC_EP4InfR REG32(UDC_EP4InfR) 1656 #define REG_UDC_EP5InfR REG32(UDC_EP5InfR) 1657 #define REG_UDC_EP6InfR REG32(UDC_EP6InfR) 1658 #define REG_UDC_EP7InfR REG32(UDC_EP7InfR) 1659 1660 #define UDC_DevCFGR_PI (1 << 5) 1661 #define UDC_DevCFGR_SS (1 << 4) 1662 #define UDC_DevCFGR_SP (1 << 3) 1663 #define UDC_DevCFGR_RW (1 << 2) 1664 #define UDC_DevCFGR_SPD_BIT 0 1665 #define UDC_DevCFGR_SPD_MASK (0x03 << UDC_DevCFGR_SPD_BIT) 1666 #define UDC_DevCFGR_SPD_HS (0 << UDC_DevCFGR_SPD_BIT) 1667 #define UDC_DevCFGR_SPD_LS (2 << UDC_DevCFGR_SPD_BIT) 1668 #define UDC_DevCFGR_SPD_FS (3 << UDC_DevCFGR_SPD_BIT) 1669 1670 #define UDC_DevCR_DM (1 << 9) 1671 #define UDC_DevCR_BE (1 << 5) 1672 #define UDC_DevCR_RES (1 << 0) 1673 1674 #define UDC_DevSR_ENUMSPD_BIT 13 1675 #define UDC_DevSR_ENUMSPD_MASK (0x03 << UDC_DevSR_ENUMSPD_BIT) 1676 #define UDC_DevSR_ENUMSPD_HS (0 << UDC_DevSR_ENUMSPD_BIT) 1677 #define UDC_DevSR_ENUMSPD_LS (2 << UDC_DevSR_ENUMSPD_BIT) 1678 #define UDC_DevSR_ENUMSPD_FS (3 << UDC_DevSR_ENUMSPD_BIT) 1679 #define UDC_DevSR_SUSP (1 << 12) 1680 #define UDC_DevSR_ALT_BIT 8 1681 #define UDC_DevSR_ALT_MASK (0x0f << UDC_DevSR_ALT_BIT) 1682 #define UDC_DevSR_INTF_BIT 4 1683 #define UDC_DevSR_INTF_MASK (0x0f << UDC_DevSR_INTF_BIT) 1684 #define UDC_DevSR_CFG_BIT 0 1685 #define UDC_DevSR_CFG_MASK (0x0f << UDC_DevSR_CFG_BIT) 1686 1687 #define UDC_DevIntR_ENUM (1 << 6) 1688 #define UDC_DevIntR_SOF (1 << 5) 1689 #define UDC_DevIntR_US (1 << 4) 1690 #define UDC_DevIntR_UR (1 << 3) 1691 #define UDC_DevIntR_SI (1 << 1) 1692 #define UDC_DevIntR_SC (1 << 0) 1693 1694 #define UDC_EPIntR_OUTEP_BIT 16 1695 #define UDC_EPIntR_OUTEP_MASK (0xffff << UDC_EPIntR_OUTEP_BIT) 1696 #define UDC_EPIntR_OUTEP0 0x00010000 1697 #define UDC_EPIntR_OUTEP5 0x00200000 1698 #define UDC_EPIntR_OUTEP6 0x00400000 1699 #define UDC_EPIntR_OUTEP7 0x00800000 1700 #define UDC_EPIntR_INEP_BIT 0 1701 #define UDC_EPIntR_INEP_MASK (0xffff << UDC_EPIntR_INEP_BIT) 1702 #define UDC_EPIntR_INEP0 0x00000001 1703 #define UDC_EPIntR_INEP1 0x00000002 1704 #define UDC_EPIntR_INEP2 0x00000004 1705 #define UDC_EPIntR_INEP3 0x00000008 1706 #define UDC_EPIntR_INEP4 0x00000010 1707 1708 1709 #define UDC_EPIntMR_OUTEP_BIT 16 1710 #define UDC_EPIntMR_OUTEP_MASK (0xffff << UDC_EPIntMR_OUTEP_BIT) 1711 #define UDC_EPIntMR_INEP_BIT 0 1712 #define UDC_EPIntMR_INEP_MASK (0xffff << UDC_EPIntMR_INEP_BIT) 1713 1714 #define UDC_EPCR_ET_BIT 4 1715 #define UDC_EPCR_ET_MASK (0x03 << UDC_EPCR_ET_BIT) 1716 #define UDC_EPCR_ET_CTRL (0 << UDC_EPCR_ET_BIT) 1717 #define UDC_EPCR_ET_ISO (1 << UDC_EPCR_ET_BIT) 1718 #define UDC_EPCR_ET_BULK (2 << UDC_EPCR_ET_BIT) 1719 #define UDC_EPCR_ET_INTR (3 << UDC_EPCR_ET_BIT) 1720 #define UDC_EPCR_SN (1 << 2) 1721 #define UDC_EPCR_F (1 << 1) 1722 #define UDC_EPCR_S (1 << 0) 1723 1724 #define UDC_EPSR_RXPKTSIZE_BIT 11 1725 #define UDC_EPSR_RXPKTSIZE_MASK (0x7ff << UDC_EPSR_RXPKTSIZE_BIT) 1726 #define UDC_EPSR_IN (1 << 6) 1727 #define UDC_EPSR_OUT_BIT 4 1728 #define UDC_EPSR_OUT_MASK (0x03 << UDC_EPSR_OUT_BIT) 1729 #define UDC_EPSR_OUT_NONE (0 << UDC_EPSR_OUT_BIT) 1730 #define UDC_EPSR_OUT_RCVDATA (1 << UDC_EPSR_OUT_BIT) 1731 #define UDC_EPSR_OUT_RCVSETUP (2 << UDC_EPSR_OUT_BIT) 1732 #define UDC_EPSR_PID_BIT 0 1733 #define UDC_EPSR_PID_MASK (0x0f << UDC_EPSR_PID_BIT) 1734 1735 #define UDC_EPInfR_MPS_BIT 19 1736 #define UDC_EPInfR_MPS_MASK (0x3ff << UDC_EPInfR_MPS_BIT) 1737 #define UDC_EPInfR_ALTS_BIT 15 1738 #define UDC_EPInfR_ALTS_MASK (0x0f << UDC_EPInfR_ALTS_BIT) 1739 #define UDC_EPInfR_IFN_BIT 11 1740 #define UDC_EPInfR_IFN_MASK (0x0f << UDC_EPInfR_IFN_BIT) 1741 #define UDC_EPInfR_CGN_BIT 7 1742 #define UDC_EPInfR_CGN_MASK (0x0f << UDC_EPInfR_CGN_BIT) 1743 #define UDC_EPInfR_EPT_BIT 5 1744 #define UDC_EPInfR_EPT_MASK (0x03 << UDC_EPInfR_EPT_BIT) 1745 #define UDC_EPInfR_EPT_CTRL (0 << UDC_EPInfR_EPT_BIT) 1746 #define UDC_EPInfR_EPT_ISO (1 << UDC_EPInfR_EPT_BIT) 1747 #define UDC_EPInfR_EPT_BULK (2 << UDC_EPInfR_EPT_BIT) 1748 #define UDC_EPInfR_EPT_INTR (3 << UDC_EPInfR_EPT_BIT) 1749 #define UDC_EPInfR_EPD (1 << 4) 1750 #define UDC_EPInfR_EPD_OUT (0 << 4) 1751 #define UDC_EPInfR_EPD_IN (1 << 4) 1752 1753 #define UDC_EPInfR_EPN_BIT 0 1754 #define UDC_EPInfR_EPN_MASK (0xf << UDC_EPInfR_EPN_BIT) 1755 1756 1757 1758 1759 /************************************************************************* 1760 * DMAC 1761 *************************************************************************/ 1762 #define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) 1763 #define DMAC_DDAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) 1764 #define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) 1765 #define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) 1766 #define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) 1767 #define DMAC_DMAIPR (DMAC_BASE + 0xf8) 1768 #define DMAC_DMACR (DMAC_BASE + 0xfc) 1769 1770 #define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) 1771 #define REG_DMAC_DDAR(n) REG32(DMAC_DDAR((n))) 1772 #define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) 1773 #define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) 1774 #define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) 1775 #define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR) 1776 #define REG_DMAC_DMACR REG32(DMAC_DMACR) 1777 1778 #define DMAC_DRSR_RS_BIT 0 1779 #define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) 1780 #define DMAC_DRSR_RS_EXTREXTR (0 << DMAC_DRSR_RS_BIT) 1781 #define DMAC_DRSR_RS_PCMCIAOUT (4 << DMAC_DRSR_RS_BIT) 1782 #define DMAC_DRSR_RS_PCMCIAIN (5 << DMAC_DRSR_RS_BIT) 1783 #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) 1784 #define DMAC_DRSR_RS_DESOUT (10 << DMAC_DRSR_RS_BIT) 1785 #define DMAC_DRSR_RS_DESIN (11 << DMAC_DRSR_RS_BIT) 1786 #define DMAC_DRSR_RS_UART3OUT (14 << DMAC_DRSR_RS_BIT) 1787 #define DMAC_DRSR_RS_UART3IN (15 << DMAC_DRSR_RS_BIT) 1788 #define DMAC_DRSR_RS_UART2OUT (16 << DMAC_DRSR_RS_BIT) 1789 #define DMAC_DRSR_RS_UART2IN (17 << DMAC_DRSR_RS_BIT) 1790 #define DMAC_DRSR_RS_UART1OUT (18 << DMAC_DRSR_RS_BIT) 1791 #define DMAC_DRSR_RS_UART1IN (19 << DMAC_DRSR_RS_BIT) 1792 #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) 1793 #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) 1794 #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) 1795 #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) 1796 #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) 1797 #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) 1798 #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) 1799 #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) 1800 #define DMAC_DRSR_RS_OST2 (28 << DMAC_DRSR_RS_BIT) 1801 1802 #define DMAC_DCCSR_EACKS (1 << 31) 1803 #define DMAC_DCCSR_EACKM (1 << 30) 1804 #define DMAC_DCCSR_ERDM_BIT 28 1805 #define DMAC_DCCSR_ERDM_MASK (0x03 << DMAC_DCCSR_ERDM_BIT) 1806 #define DMAC_DCCSR_ERDM_LLEVEL (0 << DMAC_DCCSR_ERDM_BIT) 1807 #define DMAC_DCCSR_ERDM_FEDGE (1 << DMAC_DCCSR_ERDM_BIT) 1808 #define DMAC_DCCSR_ERDM_HLEVEL (2 << DMAC_DCCSR_ERDM_BIT) 1809 #define DMAC_DCCSR_ERDM_REDGE (3 << DMAC_DCCSR_ERDM_BIT) 1810 #define DMAC_DCCSR_EOPM (1 << 27) 1811 #define DMAC_DCCSR_SAM (1 << 23) 1812 #define DMAC_DCCSR_DAM (1 << 22) 1813 #define DMAC_DCCSR_RDIL_BIT 16 1814 #define DMAC_DCCSR_RDIL_MASK (0x0f << DMAC_DCCSR_RDIL_BIT) 1815 #define DMAC_DCCSR_RDIL_IGN (0 << DMAC_DCCSR_RDIL_BIT) 1816 #define DMAC_DCCSR_RDIL_2 (1 << DMAC_DCCSR_RDIL_BIT) 1817 #define DMAC_DCCSR_RDIL_4 (2 << DMAC_DCCSR_RDIL_BIT) 1818 #define DMAC_DCCSR_RDIL_8 (3 << DMAC_DCCSR_RDIL_BIT) 1819 #define DMAC_DCCSR_RDIL_12 (4 << DMAC_DCCSR_RDIL_BIT) 1820 #define DMAC_DCCSR_RDIL_16 (5 << DMAC_DCCSR_RDIL_BIT) 1821 #define DMAC_DCCSR_RDIL_20 (6 << DMAC_DCCSR_RDIL_BIT) 1822 #define DMAC_DCCSR_RDIL_24 (7 << DMAC_DCCSR_RDIL_BIT) 1823 #define DMAC_DCCSR_RDIL_28 (8 << DMAC_DCCSR_RDIL_BIT) 1824 #define DMAC_DCCSR_RDIL_32 (9 << DMAC_DCCSR_RDIL_BIT) 1825 #define DMAC_DCCSR_RDIL_48 (10 << DMAC_DCCSR_RDIL_BIT) 1826 #define DMAC_DCCSR_RDIL_60 (11 << DMAC_DCCSR_RDIL_BIT) 1827 #define DMAC_DCCSR_RDIL_64 (12 << DMAC_DCCSR_RDIL_BIT) 1828 #define DMAC_DCCSR_RDIL_124 (13 << DMAC_DCCSR_RDIL_BIT) 1829 #define DMAC_DCCSR_RDIL_128 (14 << DMAC_DCCSR_RDIL_BIT) 1830 #define DMAC_DCCSR_RDIL_200 (15 << DMAC_DCCSR_RDIL_BIT) 1831 #define DMAC_DCCSR_SWDH_BIT 14 1832 #define DMAC_DCCSR_SWDH_MASK (0x03 << DMAC_DCCSR_SWDH_BIT) 1833 #define DMAC_DCCSR_SWDH_32 (0 << DMAC_DCCSR_SWDH_BIT) 1834 #define DMAC_DCCSR_SWDH_8 (1 << DMAC_DCCSR_SWDH_BIT) 1835 #define DMAC_DCCSR_SWDH_16 (2 << DMAC_DCCSR_SWDH_BIT) 1836 #define DMAC_DCCSR_DWDH_BIT 12 1837 #define DMAC_DCCSR_DWDH_MASK (0x03 << DMAC_DCCSR_DWDH_BIT) 1838 #define DMAC_DCCSR_DWDH_32 (0 << DMAC_DCCSR_DWDH_BIT) 1839 #define DMAC_DCCSR_DWDH_8 (1 << DMAC_DCCSR_DWDH_BIT) 1840 #define DMAC_DCCSR_DWDH_16 (2 << DMAC_DCCSR_DWDH_BIT) 1841 #define DMAC_DCCSR_DS_BIT 8 1842 #define DMAC_DCCSR_DS_MASK (0x07 << DMAC_DCCSR_DS_BIT) 1843 #define DMAC_DCCSR_DS_32b (0 << DMAC_DCCSR_DS_BIT) 1844 #define DMAC_DCCSR_DS_8b (1 << DMAC_DCCSR_DS_BIT) 1845 #define DMAC_DCCSR_DS_16b (2 << DMAC_DCCSR_DS_BIT) 1846 #define DMAC_DCCSR_DS_16B (3 << DMAC_DCCSR_DS_BIT) 1847 #define DMAC_DCCSR_DS_32B (4 << DMAC_DCCSR_DS_BIT) 1848 #define DMAC_DCCSR_TM (1 << 7) 1849 #define DMAC_DCCSR_AR (1 << 4) 1850 #define DMAC_DCCSR_TC (1 << 3) 1851 #define DMAC_DCCSR_HLT (1 << 2) 1852 #define DMAC_DCCSR_TCIE (1 << 1) 1853 #define DMAC_DCCSR_CHDE (1 << 0) 1854 1855 #define DMAC_DMAIPR_CINT_BIT 8 1856 #define DMAC_DMAIPR_CINT_MASK (0xff << DMAC_DMAIPR_CINT_BIT) 1857 1858 #define DMAC_DMACR_PR_BIT 8 1859 #define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) 1860 #define DMAC_DMACR_PR_01234567 (0 << DMAC_DMACR_PR_BIT) 1861 #define DMAC_DMACR_PR_02314675 (1 << DMAC_DMACR_PR_BIT) 1862 #define DMAC_DMACR_PR_20136457 (2 << DMAC_DMACR_PR_BIT) 1863 #define DMAC_DMACR_PR_ROUNDROBIN (3 << DMAC_DMACR_PR_BIT) 1864 #define DMAC_DMACR_HTR (1 << 3) 1865 #define DMAC_DMACR_AER (1 << 2) 1866 #define DMAC_DMACR_DME (1 << 0) 1867 1868 #define IRQ_DMA_0 32 1869 #define NUM_DMA 6 1870 1871 1872 /************************************************************************* 1873 * AIC 1874 *************************************************************************/ 1875 #define AIC_FR (AIC_BASE + 0x000) 1876 #define AIC_CR (AIC_BASE + 0x004) 1877 #define AIC_ACCR1 (AIC_BASE + 0x008) 1878 #define AIC_ACCR2 (AIC_BASE + 0x00C) 1879 #define AIC_I2SCR (AIC_BASE + 0x010) 1880 #define AIC_SR (AIC_BASE + 0x014) 1881 #define AIC_ACSR (AIC_BASE + 0x018) 1882 #define AIC_I2SSR (AIC_BASE + 0x01C) 1883 #define AIC_ACCAR (AIC_BASE + 0x020) 1884 #define AIC_ACCDR (AIC_BASE + 0x024) 1885 #define AIC_ACSAR (AIC_BASE + 0x028) 1886 #define AIC_ACSDR (AIC_BASE + 0x02C) 1887 #define AIC_I2SDIV (AIC_BASE + 0x030) 1888 #define AIC_DR (AIC_BASE + 0x034) 1889 1890 #define REG_AIC_FR REG32(AIC_FR) 1891 #define REG_AIC_CR REG32(AIC_CR) 1892 #define REG_AIC_ACCR1 REG32(AIC_ACCR1) 1893 #define REG_AIC_ACCR2 REG32(AIC_ACCR2) 1894 #define REG_AIC_I2SCR REG32(AIC_I2SCR) 1895 #define REG_AIC_SR REG32(AIC_SR) 1896 #define REG_AIC_ACSR REG32(AIC_ACSR) 1897 #define REG_AIC_I2SSR REG32(AIC_I2SSR) 1898 #define REG_AIC_ACCAR REG32(AIC_ACCAR) 1899 #define REG_AIC_ACCDR REG32(AIC_ACCDR) 1900 #define REG_AIC_ACSAR REG32(AIC_ACSAR) 1901 #define REG_AIC_ACSDR REG32(AIC_ACSDR) 1902 #define REG_AIC_I2SDIV REG32(AIC_I2SDIV) 1903 #define REG_AIC_DR REG32(AIC_DR) 1904 1905 /* AIC Controller Configuration Register (AIC_FR) */ 1906 1907 #define AIC_FR_RFTH_BIT 12 1908 #define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) 1909 #define AIC_FR_TFTH_BIT 8 1910 #define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) 1911 #define AIC_FR_AUSEL (1 << 4) 1912 #define AIC_FR_RST (1 << 3) 1913 #define AIC_FR_BCKD (1 << 2) 1914 #define AIC_FR_SYNCD (1 << 1) 1915 #define AIC_FR_ENB (1 << 0) 1916 1917 /* AIC Controller Common Control Register (AIC_CR) */ 1918 1919 #define AIC_CR_RDMS (1 << 15) 1920 #define AIC_CR_TDMS (1 << 14) 1921 #define AIC_CR_FLUSH (1 << 8) 1922 #define AIC_CR_EROR (1 << 6) 1923 #define AIC_CR_ETUR (1 << 5) 1924 #define AIC_CR_ERFS (1 << 4) 1925 #define AIC_CR_ETFS (1 << 3) 1926 #define AIC_CR_ENLBF (1 << 2) 1927 #define AIC_CR_ERPL (1 << 1) 1928 #define AIC_CR_EREC (1 << 0) 1929 1930 /* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ 1931 1932 #define AIC_ACCR1_RS_BIT 16 1933 #define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) 1934 #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ 1935 #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ 1936 #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ 1937 #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit */ 1938 #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit */ 1939 #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit */ 1940 #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit */ 1941 #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ 1942 #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit */ 1943 #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit */ 1944 #define AIC_ACCR1_XS_BIT 0 1945 #define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) 1946 #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ 1947 #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ 1948 #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ 1949 #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit */ 1950 #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit */ 1951 #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit */ 1952 #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit */ 1953 #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ 1954 #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit */ 1955 #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit */ 1956 1957 /* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ 1958 1959 #define AIC_ACCR2_ERSTO (1 << 18) 1960 #define AIC_ACCR2_ESADR (1 << 17) 1961 #define AIC_ACCR2_ECADT (1 << 16) 1962 #define AIC_ACCR2_OASS_BIT 8 1963 #define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) 1964 #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ 1965 #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ 1966 #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ 1967 #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ 1968 #define AIC_ACCR2_IASS_BIT 6 1969 #define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) 1970 #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ 1971 #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ 1972 #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ 1973 #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ 1974 #define AIC_ACCR2_SO (1 << 3) 1975 #define AIC_ACCR2_SR (1 << 2) 1976 #define AIC_ACCR2_SS (1 << 1) 1977 #define AIC_ACCR2_SA (1 << 0) 1978 1979 /* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ 1980 1981 #define AIC_I2SCR_STPBK (1 << 12) 1982 #define AIC_I2SCR_WL_BIT 1 1983 #define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) 1984 #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ 1985 #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ 1986 #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ 1987 #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ 1988 #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ 1989 #define AIC_I2SCR_AMSL (1 << 0) 1990 1991 /* AIC Controller FIFO Status Register (AIC_SR) */ 1992 1993 #define AIC_SR_RFL_BIT 24 1994 #define AIC_SR_RFL_MASK (0x1f << AIC_SR_RFL_BIT) 1995 #define AIC_SR_TFL_BIT 8 1996 #define AIC_SR_TFL_MASK (0x1f << AIC_SR_TFL_BIT) 1997 #define AIC_SR_ROR (1 << 6) 1998 #define AIC_SR_TUR (1 << 5) 1999 #define AIC_SR_RFS (1 << 4) 2000 #define AIC_SR_TFS (1 << 3) 2001 2002 /* AIC Controller AC-link Status Register (AIC_ACSR) */ 2003 2004 #define AIC_ACSR_CRDY (1 << 20) 2005 #define AIC_ACSR_CLPM (1 << 19) 2006 #define AIC_ACSR_RSTO (1 << 18) 2007 #define AIC_ACSR_SADR (1 << 17) 2008 #define AIC_ACSR_CADT (1 << 16) 2009 2010 /* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ 2011 2012 #define AIC_I2SSR_BSY (1 << 2) 2013 2014 /* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ 2015 2016 #define AIC_ACCAR_CAR_BIT 0 2017 #define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) 2018 2019 /* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ 2020 2021 #define AIC_ACCDR_CDR_BIT 0 2022 #define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) 2023 2024 /* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ 2025 2026 #define AIC_ACSAR_SAR_BIT 0 2027 #define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) 2028 2029 /* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ 2030 2031 #define AIC_ACSDR_SDR_BIT 0 2032 #define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) 2033 2034 /* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ 2035 2036 #define AIC_I2SDIV_DIV_BIT 0 2037 #define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) 2038 #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ 2039 #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ 2040 #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ 2041 #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ 2042 #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ 2043 #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ 2044 2045 2046 2047 2048 /************************************************************************* 2049 * LCD 2050 *************************************************************************/ 2051 2052 /* Register definitions with absolute positioning have been removed. */ 2053 2054 #define LCD_CFG_PDW_BIT 4 2055 #define LCD_CFG_PDW_MASK (0x03 << LCD_DEV_PDW_BIT) 2056 #define LCD_CFG_PDW_1 (0 << LCD_DEV_PDW_BIT) 2057 #define LCD_CFG_PDW_2 (1 << LCD_DEV_PDW_BIT) 2058 #define LCD_CFG_PDW_4 (2 << LCD_DEV_PDW_BIT) 2059 #define LCD_CFG_PDW_8 (3 << LCD_DEV_PDW_BIT) 2060 #define LCD_CFG_MODE_BIT 0 2061 #define LCD_CFG_MODE_MASK (0x0f << LCD_DEV_MODE_BIT) 2062 #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_DEV_MODE_BIT) 2063 #define LCD_CFG_MODE_SHARP_HR (1 << LCD_DEV_MODE_BIT) 2064 #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_DEV_MODE_BIT) 2065 #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_DEV_MODE_BIT) 2066 #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_DEV_MODE_BIT) 2067 #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_DEV_MODE_BIT) 2068 #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_DEV_MODE_BIT) 2069 #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_DEV_MODE_BIT) 2070 #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_DEV_MODE_BIT) 2071 #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_DEV_MODE_BIT) 2072 2073 #define LCD_VSYNC_VPS_BIT 16 2074 #define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) 2075 #define LCD_VSYNC_VPE_BIT 0 2076 #define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) 2077 2078 #define LCD_HSYNC_HPS_BIT 16 2079 #define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) 2080 #define LCD_HSYNC_HPE_BIT 0 2081 #define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) 2082 2083 #define LCD_VAT_HT_BIT 16 2084 #define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) 2085 #define LCD_VAT_VT_BIT 0 2086 #define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) 2087 2088 #define LCD_DAH_HDS_BIT 16 2089 #define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) 2090 #define LCD_DAH_HDE_BIT 0 2091 #define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) 2092 2093 #define LCD_DAV_VDS_BIT 16 2094 #define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) 2095 #define LCD_DAV_VDE_BIT 0 2096 #define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) 2097 2098 #define LCD_CTRL_BST_BIT 28 2099 #define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) 2100 #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) 2101 #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) 2102 #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) 2103 #define LCD_CTRL_RGB555 (1 << 27) 2104 #define LCD_CTRL_OFUP (1 << 26) 2105 #define LCD_CTRL_FRC_BIT 24 2106 #define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) 2107 #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) 2108 #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) 2109 #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) 2110 #define LCD_CTRL_PDD_BIT 16 2111 #define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) 2112 #define LCD_CTRL_EOFM (1 << 13) 2113 #define LCD_CTRL_SOFM (1 << 12) 2114 #define LCD_CTRL_OFUM (1 << 11) 2115 #define LCD_CTRL_IFUM0 (1 << 10) 2116 #define LCD_CTRL_IFUM1 (1 << 9) 2117 #define LCD_CTRL_LDDM (1 << 8) 2118 #define LCD_CTRL_QDM (1 << 7) 2119 #define LCD_CTRL_BEDN (1 << 6) 2120 #define LCD_CTRL_PEDN (1 << 5) 2121 #define LCD_CTRL_DIS (1 << 4) 2122 #define LCD_CTRL_ENA (1 << 3) 2123 #define LCD_CTRL_BPP_BIT 0 2124 #define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) 2125 #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) 2126 #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) 2127 #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) 2128 #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) 2129 #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) 2130 2131 #define LCD_STATE_QD (1 << 7) 2132 #define LCD_STATE_EOF (1 << 5) 2133 #define LCD_STATE_SOF (1 << 4) 2134 #define LCD_STATE_OFU (1 << 3) 2135 #define LCD_STATE_IFU0 (1 << 2) 2136 #define LCD_STATE_IFU1 (1 << 1) 2137 #define LCD_STATE_LDD (1 << 0) 2138 2139 #define LCD_CMD_SOFINT (1 << 31) 2140 #define LCD_CMD_EOFINT (1 << 30) 2141 #define LCD_CMD_PAL (1 << 28) 2142 #define LCD_CMD_LEN_BIT 0 2143 #define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) 2144 2145 2146 2147 2148 /************************************************************************* 2149 * DES 2150 *************************************************************************/ 2151 #define DES_CR1 (DES_BASE + 0x000) 2152 #define DES_CR2 (DES_BASE + 0x004) 2153 #define DES_SR (DES_BASE + 0x008) 2154 #define DES_K1L (DES_BASE + 0x010) 2155 #define DES_K1R (DES_BASE + 0x014) 2156 #define DES_K2L (DES_BASE + 0x018) 2157 #define DES_K2R (DES_BASE + 0x01C) 2158 #define DES_K3L (DES_BASE + 0x020) 2159 #define DES_K3R (DES_BASE + 0x024) 2160 #define DES_IVL (DES_BASE + 0x028) 2161 #define DES_IVR (DES_BASE + 0x02C) 2162 #define DES_DIN (DES_BASE + 0x030) 2163 #define DES_DOUT (DES_BASE + 0x034) 2164 2165 #define REG_DES_CR1 REG32(DES_CR1) 2166 #define REG_DES_CR2 REG32(DES_CR2) 2167 #define REG_DES_SR REG32(DES_SR) 2168 #define REG_DES_K1L REG32(DES_K1L) 2169 #define REG_DES_K1R REG32(DES_K1R) 2170 #define REG_DES_K2L REG32(DES_K2L) 2171 #define REG_DES_K2R REG32(DES_K2R) 2172 #define REG_DES_K3L REG32(DES_K3L) 2173 #define REG_DES_K3R REG32(DES_K3R) 2174 #define REG_DES_IVL REG32(DES_IVL) 2175 #define REG_DES_IVR REG32(DES_IVR) 2176 #define REG_DES_DIN REG32(DES_DIN) 2177 #define REG_DES_DOUT REG32(DES_DOUT) 2178 2179 /* DES Control Register 1 (DES_CR1) */ 2180 2181 #define DES_CR1_EN (1 << 0) 2182 2183 /* DES Control Register 2 (DES_CR2) */ 2184 2185 #define DES_CR2_ENDEC (1 << 3) 2186 #define DES_CR2_MODE (1 << 2) 2187 #define DES_CR2_ALG (1 << 1) 2188 #define DES_CR2_DMAE (1 << 0) 2189 2190 /* DES State Register (DES_SR) */ 2191 2192 #define DES_SR_IN_FULL (1 << 5) 2193 #define DES_SR_IN_LHF (1 << 4) 2194 #define DES_SR_IN_EMPTY (1 << 3) 2195 #define DES_SR_OUT_FULL (1 << 2) 2196 #define DES_SR_OUT_GHF (1 << 1) 2197 #define DES_SR_OUT_EMPTY (1 << 0) 2198 2199 2200 2201 2202 /************************************************************************* 2203 * CPM 2204 *************************************************************************/ 2205 2206 /* Register definitions with absolute positioning have been removed. */ 2207 2208 #define CPM_CFCR_SSI (1 << 31) 2209 #define CPM_CFCR_LCD (1 << 30) 2210 #define CPM_CFCR_I2S (1 << 29) 2211 #define CPM_CFCR_UCS (1 << 28) 2212 #define CPM_CFCR_UFR_BIT 25 2213 #define CPM_CFCR_UFR_MASK (0x07 << CPM_CFCR_UFR_BIT) 2214 #define CPM_CFCR_MSC (1 << 24) 2215 #define CPM_CFCR_CKOEN2 (1 << 23) 2216 #define CPM_CFCR_CKOEN1 (1 << 22) 2217 #define CPM_CFCR_UPE (1 << 20) 2218 #define CPM_CFCR_MFR_BIT 16 2219 #define CPM_CFCR_MFR_MASK (0x0f << CPM_CFCR_MFR_BIT) 2220 #define CFCR_MDIV_1 (0 << CPM_CFCR_MFR_BIT) 2221 #define CFCR_MDIV_2 (1 << CPM_CFCR_MFR_BIT) 2222 #define CFCR_MDIV_3 (2 << CPM_CFCR_MFR_BIT) 2223 #define CFCR_MDIV_4 (3 << CPM_CFCR_MFR_BIT) 2224 #define CFCR_MDIV_6 (4 << CPM_CFCR_MFR_BIT) 2225 #define CFCR_MDIV_8 (5 << CPM_CFCR_MFR_BIT) 2226 #define CFCR_MDIV_12 (6 << CPM_CFCR_MFR_BIT) 2227 #define CFCR_MDIV_16 (7 << CPM_CFCR_MFR_BIT) 2228 #define CFCR_MDIV_24 (8 << CPM_CFCR_MFR_BIT) 2229 #define CFCR_MDIV_32 (9 << CPM_CFCR_MFR_BIT) 2230 #define CPM_CFCR_LFR_BIT 12 2231 #define CPM_CFCR_LFR_MASK (0x0f << CPM_CFCR_LFR_BIT) 2232 #define CPM_CFCR_PFR_BIT 8 2233 #define CPM_CFCR_PFR_MASK (0x0f << CPM_CFCR_PFR_BIT) 2234 #define CFCR_PDIV_1 (0 << CPM_CFCR_PFR_BIT) 2235 #define CFCR_PDIV_2 (1 << CPM_CFCR_PFR_BIT) 2236 #define CFCR_PDIV_3 (2 << CPM_CFCR_PFR_BIT) 2237 #define CFCR_PDIV_4 (3 << CPM_CFCR_PFR_BIT) 2238 #define CFCR_PDIV_6 (4 << CPM_CFCR_PFR_BIT) 2239 #define CFCR_PDIV_8 (5 << CPM_CFCR_PFR_BIT) 2240 #define CFCR_PDIV_12 (6 << CPM_CFCR_PFR_BIT) 2241 #define CFCR_PDIV_16 (7 << CPM_CFCR_PFR_BIT) 2242 #define CFCR_PDIV_24 (8 << CPM_CFCR_PFR_BIT) 2243 #define CFCR_PDIV_32 (9 << CPM_CFCR_PFR_BIT) 2244 #define CPM_CFCR_SFR_BIT 4 2245 #define CPM_CFCR_SFR_MASK (0x0f << CPM_CFCR_SFR_BIT) 2246 #define CFCR_SDIV_1 (0 << CPM_CFCR_SFR_BIT) 2247 #define CFCR_SDIV_2 (1 << CPM_CFCR_SFR_BIT) 2248 #define CFCR_SDIV_3 (2 << CPM_CFCR_SFR_BIT) 2249 #define CFCR_SDIV_4 (3 << CPM_CFCR_SFR_BIT) 2250 #define CFCR_SDIV_6 (4 << CPM_CFCR_SFR_BIT) 2251 #define CFCR_SDIV_8 (5 << CPM_CFCR_SFR_BIT) 2252 #define CFCR_SDIV_12 (6 << CPM_CFCR_SFR_BIT) 2253 #define CFCR_SDIV_16 (7 << CPM_CFCR_SFR_BIT) 2254 #define CFCR_SDIV_24 (8 << CPM_CFCR_SFR_BIT) 2255 #define CFCR_SDIV_32 (9 << CPM_CFCR_SFR_BIT) 2256 #define CPM_CFCR_IFR_BIT 0 2257 #define CPM_CFCR_IFR_MASK (0x0f << CPM_CFCR_IFR_BIT) 2258 #define CFCR_IDIV_1 (0 << CPM_CFCR_IFR_BIT) 2259 #define CFCR_IDIV_2 (1 << CPM_CFCR_IFR_BIT) 2260 #define CFCR_IDIV_3 (2 << CPM_CFCR_IFR_BIT) 2261 #define CFCR_IDIV_4 (3 << CPM_CFCR_IFR_BIT) 2262 #define CFCR_IDIV_6 (4 << CPM_CFCR_IFR_BIT) 2263 #define CFCR_IDIV_8 (5 << CPM_CFCR_IFR_BIT) 2264 #define CFCR_IDIV_12 (6 << CPM_CFCR_IFR_BIT) 2265 #define CFCR_IDIV_16 (7 << CPM_CFCR_IFR_BIT) 2266 #define CFCR_IDIV_24 (8 << CPM_CFCR_IFR_BIT) 2267 #define CFCR_IDIV_32 (9 << CPM_CFCR_IFR_BIT) 2268 2269 #define CPM_PLCR1_PLL1FD_BIT 23 2270 #define CPM_PLCR1_PLL1FD_MASK (0x1ff << CPM_PLCR1_PLL1FD_BIT) 2271 #define CPM_PLCR1_PLL1RD_BIT 18 2272 #define CPM_PLCR1_PLL1RD_MASK (0x1f << CPM_PLCR1_PLL1RD_BIT) 2273 #define CPM_PLCR1_PLL1OD_BIT 16 2274 #define CPM_PLCR1_PLL1OD_MASK (0x03 << CPM_PLCR1_PLL1OD_BIT) 2275 #define CPM_PLCR1_PLL1S (1 << 10) 2276 #define CPM_PLCR1_PLL1BP (1 << 9) 2277 #define CPM_PLCR1_PLL1EN (1 << 8) 2278 #define CPM_PLCR1_PLL1ST_BIT 0 2279 #define CPM_PLCR1_PLL1ST_MASK (0xff << CPM_PLCR1_PLL1ST_BIT) 2280 2281 #define CPM_OCR_O1ST_BIT 16 2282 #define CPM_OCR_O1ST_MASK (0xff << CPM_OCR_O1ST_BIT) 2283 #define CPM_OCR_EXT_RTC_CLK (1<<8) 2284 #define CPM_OCR_SUSPEND_PHY1 (1<<7) 2285 #define CPM_OCR_SUSPEND_PHY0 (1<<6) 2286 2287 #define CPM_CFCR2_PXFR_BIT 0 2288 #define CPM_CFCR2_PXFR_MASK (0x1ff << CPM_CFCR2_PXFR_BIT) 2289 2290 #define CPM_LPCR_DUTY_BIT 3 2291 #define CPM_LPCR_DUTY_MASK (0x1f << CPM_LPCR_DUTY_BIT) 2292 #define CPM_LPCR_DOZE (1 << 2) 2293 #define CPM_LPCR_LPM_BIT 0 2294 #define CPM_LPCR_LPM_MASK (0x03 << CPM_LPCR_LPM_BIT) 2295 #define CPM_LPCR_LPM_IDLE (0 << CPM_LPCR_LPM_BIT) 2296 #define CPM_LPCR_LPM_SLEEP (1 << CPM_LPCR_LPM_BIT) 2297 #define CPM_LPCR_LPM_HIBERNATE (2 << CPM_LPCR_LPM_BIT) 2298 2299 #define CPM_RSTR_SR (1 << 2) 2300 #define CPM_RSTR_WR (1 << 1) 2301 #define CPM_RSTR_HR (1 << 0) 2302 2303 #define CPM_MSCR_MSTP_BIT 0 2304 #define CPM_MSCR_MSTP_MASK (0x1ffffff << CPM_MSCR_MSTP_BIT) 2305 #define CPM_MSCR_MSTP_UART0 0 2306 #define CPM_MSCR_MSTP_UART1 1 2307 #define CPM_MSCR_MSTP_UART2 2 2308 #define CPM_MSCR_MSTP_OST 3 2309 #define CPM_MSCR_MSTP_DMAC 5 2310 #define CPM_MSCR_MSTP_UHC 6 2311 #define CPM_MSCR_MSTP_LCD 7 2312 #define CPM_MSCR_MSTP_I2C 8 2313 #define CPM_MSCR_MSTP_AICPCLK 9 2314 #define CPM_MSCR_MSTP_PWM0 10 2315 #define CPM_MSCR_MSTP_PWM1 11 2316 #define CPM_MSCR_MSTP_SSI 12 2317 #define CPM_MSCR_MSTP_MSC 13 2318 #define CPM_MSCR_MSTP_SCC 14 2319 #define CPM_MSCR_MSTP_AICBCLK 18 2320 #define CPM_MSCR_MSTP_UART3 20 2321 #define CPM_MSCR_MSTP_ETH 21 2322 #define CPM_MSCR_MSTP_KBC 22 2323 #define CPM_MSCR_MSTP_CIM 23 2324 #define CPM_MSCR_MSTP_UDC 24 2325 #define CPM_MSCR_MSTP_UPRT 25 2326 2327 #define CPM_SCR_O1SE (1 << 4) 2328 #define CPM_SCR_HGP (1 << 3) 2329 #define CPM_SCR_HZP (1 << 2) 2330 #define CPM_SCR_HZM (1 << 1) 2331 2332 #define CPM_WRER_RE_BIT 0 2333 #define CPM_WRER_RE_MASK (0xffff << CPM_WRER_RE_BIT) 2334 2335 #define CPM_WFER_FE_BIT 0 2336 #define CPM_WFER_FE_MASK (0xffff << CPM_WFER_FE_BIT) 2337 2338 #define CPM_WER_WERTC (1 << 31) 2339 #define CPM_WER_WEETH (1 << 30) 2340 #define CPM_WER_WE_BIT 0 2341 #define CPM_WER_WE_MASK (0xffff << CPM_WER_WE_BIT) 2342 2343 #define CPM_WSR_WSRTC (1 << 31) 2344 #define CPM_WSR_WSETH (1 << 30) 2345 #define CPM_WSR_WS_BIT 0 2346 #define CPM_WSR_WS_MASK (0xffff << CPM_WSR_WS_BIT) 2347 2348 2349 2350 2351 /************************************************************************* 2352 * SSI 2353 *************************************************************************/ 2354 #define SSI_DR (SSI_BASE + 0x000) 2355 #define SSI_CR0 (SSI_BASE + 0x004) 2356 #define SSI_CR1 (SSI_BASE + 0x008) 2357 #define SSI_SR (SSI_BASE + 0x00C) 2358 #define SSI_ITR (SSI_BASE + 0x010) 2359 #define SSI_ICR (SSI_BASE + 0x014) 2360 #define SSI_GR (SSI_BASE + 0x018) 2361 2362 #define REG_SSI_DR REG32(SSI_DR) 2363 #define REG_SSI_CR0 REG16(SSI_CR0) 2364 #define REG_SSI_CR1 REG32(SSI_CR1) 2365 #define REG_SSI_SR REG32(SSI_SR) 2366 #define REG_SSI_ITR REG16(SSI_ITR) 2367 #define REG_SSI_ICR REG8(SSI_ICR) 2368 #define REG_SSI_GR REG16(SSI_GR) 2369 2370 /* SSI Data Register (SSI_DR) */ 2371 2372 #define SSI_DR_GPC_BIT 0 2373 #define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) 2374 2375 /* SSI Control Register 0 (SSI_CR0) */ 2376 2377 #define SSI_CR0_SSIE (1 << 15) 2378 #define SSI_CR0_TIE (1 << 14) 2379 #define SSI_CR0_RIE (1 << 13) 2380 #define SSI_CR0_TEIE (1 << 12) 2381 #define SSI_CR0_REIE (1 << 11) 2382 #define SSI_CR0_LOOP (1 << 10) 2383 #define SSI_CR0_RFINE (1 << 9) 2384 #define SSI_CR0_RFINC (1 << 8) 2385 #define SSI_CR0_FSEL (1 << 6) 2386 #define SSI_CR0_TFLUSH (1 << 2) 2387 #define SSI_CR0_RFLUSH (1 << 1) 2388 #define SSI_CR0_DISREV (1 << 0) 2389 2390 /* SSI Control Register 1 (SSI_CR1) */ 2391 2392 #define SSI_CR1_FRMHL_BIT 30 2393 #define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) 2394 #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ 2395 #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ 2396 #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ 2397 #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ 2398 #define SSI_CR1_TFVCK_BIT 28 2399 #define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) 2400 #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) 2401 #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) 2402 #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) 2403 #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) 2404 #define SSI_CR1_TCKFI_BIT 26 2405 #define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) 2406 #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) 2407 #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) 2408 #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) 2409 #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) 2410 #define SSI_CR1_LFST (1 << 25) 2411 #define SSI_CR1_ITFRM (1 << 24) 2412 #define SSI_CR1_UNFIN (1 << 23) 2413 #define SSI_CR1_MULTS (1 << 22) 2414 #define SSI_CR1_FMAT_BIT 20 2415 #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) 2416 #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola????s SPI format */ 2417 #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ 2418 #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ 2419 #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ 2420 #define SSI_CR1_MCOM_BIT 12 2421 #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) 2422 #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ 2423 #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ 2424 #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ 2425 #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ 2426 #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ 2427 #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ 2428 #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ 2429 #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ 2430 #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ 2431 #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ 2432 #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ 2433 #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ 2434 #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ 2435 #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ 2436 #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ 2437 #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ 2438 #define SSI_CR1_TTRG_BIT 10 2439 #define SSI_CR1_TTRG_MASK (0x3 << SSI_CR1_TTRG_BIT) 2440 #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)/* Less than or equal to 1 */ 2441 #define SSI_CR1_TTRG_4 (1 << SSI_CR1_TTRG_BIT) /* Less than or equal to 4 */ 2442 #define SSI_CR1_TTRG_8 (2 << SSI_CR1_TTRG_BIT) /* Less than or equal to 8 */ 2443 #define SSI_CR1_TTRG_14 (3 << SSI_CR1_TTRG_BIT) /* Less than or equal to 14 */ 2444 #define SSI_CR1_RTRG_BIT 8 2445 #define SSI_CR1_RTRG_MASK (0x3 << SSI_CR1_RTRG_BIT) 2446 #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) /* More than or equal to 1 */ 2447 #define SSI_CR1_RTRG_4 (1 << SSI_CR1_RTRG_BIT) /* More than or equal to 4 */ 2448 #define SSI_CR1_RTRG_8 (2 << SSI_CR1_RTRG_BIT) /* More than or equal to 8 */ 2449 #define SSI_CR1_RTRG_14 (3 << SSI_CR1_RTRG_BIT) /* More than or equal to 14 */ 2450 #define SSI_CR1_FLEN_BIT 4 2451 #define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) 2452 #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) 2453 #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) 2454 #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) 2455 #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) 2456 #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) 2457 #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) 2458 #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) 2459 #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) 2460 #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) 2461 #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) 2462 #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) 2463 #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) 2464 #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) 2465 #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) 2466 #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) 2467 #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) 2468 #define SSI_CR1_PHA (1 << 1) 2469 #define SSI_CR1_POL (1 << 0) 2470 2471 /* SSI Status Register (SSI_SR) */ 2472 2473 #define SSI_SR_TFIFONUM_BIT 13 2474 #define SSI_SR_TFIFONUM_MASK (0x1f << SSI_SR_TFIFONUM_BIT) 2475 #define SSI_SR_RFIFONUM_BIT 8 2476 #define SSI_SR_RFIFONUM_MASK (0x1f << SSI_SR_RFIFONUM_BIT) 2477 #define SSI_SR_END (1 << 7) 2478 #define SSI_SR_BUSY (1 << 6) 2479 #define SSI_SR_TFF (1 << 5) 2480 #define SSI_SR_RFE (1 << 4) 2481 #define SSI_SR_TFHE (1 << 3) 2482 #define SSI_SR_RFHF (1 << 2) 2483 #define SSI_SR_UNDR (1 << 1) 2484 #define SSI_SR_OVER (1 << 0) 2485 2486 /* SSI Interval Time Control Register (SSI_ITR) */ 2487 2488 #define SSI_ITR_CNTCLK (1 << 15) 2489 #define SSI_ITR_IVLTM_BIT 0 2490 #define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) 2491 2492 #ifndef __ASSEMBLY__ 2493 2494 /*************************************************************************** 2495 * MSC 2496 ***************************************************************************/ 2497 2498 #define __msc_start_op() \ 2499 ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) 2500 2501 #define __msc_set_resto(to) ( REG_MSC_RESTO = to ) 2502 #define __msc_set_rdto(to) ( REG_MSC_RDTO = to ) 2503 #define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd ) 2504 #define __msc_set_arg(arg) ( REG_MSC_ARG = arg ) 2505 #define __msc_set_nob(nob) ( REG_MSC_NOB = nob ) 2506 #define __msc_get_nob() ( REG_MSC_NOB ) 2507 #define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len ) 2508 #define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat ) 2509 #define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) 2510 #define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) 2511 2512 #define __msc_set_cmdat_bus_width1() \ 2513 do { \ 2514 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ 2515 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \ 2516 } while(0) 2517 2518 #define __msc_set_cmdat_bus_width4() \ 2519 do { \ 2520 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ 2521 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \ 2522 } while(0) 2523 2524 #define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN ) 2525 #define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT ) 2526 #define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY ) 2527 #define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) 2528 #define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) 2529 #define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) 2530 #define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) 2531 #define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN ) 2532 2533 /* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ 2534 #define __msc_set_cmdat_res_format(r) \ 2535 do { \ 2536 REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ 2537 REG_MSC_CMDAT |= (r); \ 2538 } while(0) 2539 2540 #define __msc_clear_cmdat() \ 2541 REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ 2542 MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ 2543 MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ) 2544 2545 #define __msc_get_imask() ( REG_MSC_IMASK ) 2546 #define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff ) 2547 #define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 ) 2548 #define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) 2549 #define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) 2550 #define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) 2551 #define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) 2552 #define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES ) 2553 #define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) 2554 #define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) 2555 #define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) 2556 #define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE ) 2557 #define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) 2558 2559 /* n=1,2,4,8,16,32,64,128 */ 2560 #define __msc_set_clkrt_div(n) \ 2561 do { \ 2562 REG_MSC_CLKRT &= ~MSC_CLKRT_CLK_RATE_MASK; \ 2563 REG_MSC_CLKRT |= MSC_CLKRT_CLK_RATE_DIV_##n; \ 2564 } while(0) 2565 2566 #define __msc_get_ireg() ( REG_MSC_IREG ) 2567 #define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) 2568 #define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) 2569 #define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES ) 2570 #define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) 2571 #define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE ) 2572 #define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES ) 2573 #define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) 2574 #define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE ) 2575 2576 #define __msc_get_stat() ( REG_MSC_STAT ) 2577 #define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0) 2578 #define __msc_stat_crc_err() \ 2579 ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) 2580 #define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR ) 2581 #define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR ) 2582 #define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) 2583 #define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES ) 2584 #define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ ) 2585 2586 #define __msc_rd_resfifo() ( REG_MSC_RES ) 2587 #define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) 2588 #define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) 2589 2590 #define __msc_reset() \ 2591 do { \ 2592 REG_MSC_STRPCL = MSC_STRPCL_RESET; \ 2593 while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ 2594 } while (0) 2595 2596 #define __msc_start_clk() \ 2597 do { \ 2598 REG_MSC_STRPCL &= ~MSC_STRPCL_CLOCK_CONTROL_MASK; \ 2599 REG_MSC_STRPCL |= MSC_STRPCL_CLOCK_CONTROL_START; \ 2600 } while (0) 2601 2602 #define __msc_stop_clk() \ 2603 do { \ 2604 REG_MSC_STRPCL &= ~MSC_STRPCL_CLOCK_CONTROL_MASK; \ 2605 REG_MSC_STRPCL |= MSC_STRPCL_CLOCK_CONTROL_STOP; \ 2606 } while (0) 2607 2608 #define MMC_CLK 19169200 2609 #define SD_CLK 24576000 2610 2611 /* msc_clk should little than pclk and little than clk retrieve from card */ 2612 #define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ 2613 do { \ 2614 unsigned int rate, pclk, i; \ 2615 pclk = dev_clk; \ 2616 rate = type?SD_CLK:MMC_CLK; \ 2617 if (msc_clk && msc_clk < pclk) \ 2618 pclk = msc_clk; \ 2619 i = 0; \ 2620 while (pclk < rate) \ 2621 { \ 2622 i ++; \ 2623 rate >>= 1; \ 2624 } \ 2625 lv = i; \ 2626 } while(0) 2627 2628 /* divide rate to little than or equal to 400kHz */ 2629 #define __msc_calc_slow_clk_divisor(type, lv) \ 2630 do { \ 2631 unsigned int rate, i; \ 2632 rate = (type?SD_CLK:MMC_CLK)/1000/400; \ 2633 i = 0; \ 2634 while (rate > 0) \ 2635 { \ 2636 rate >>= 1; \ 2637 i ++; \ 2638 } \ 2639 lv = i; \ 2640 } while(0) 2641 2642 /*************************************************************************** 2643 * RTC 2644 ***************************************************************************/ 2645 2646 #define __rtc_start() ( REG_RTC_RCR |= RTC_RCR_START ) 2647 #define __rtc_stop() ( REG_RTC_RCR &= ~RTC_RCR_START ) 2648 2649 #define __rtc_enable_alarm() ( REG_RTC_RCR |= RTC_RCR_AE ) 2650 #define __rtc_disable_alarm() ( REG_RTC_RCR &= ~RTC_RCR_AE ) 2651 #define __rtc_enable_alarm_irq() ( REG_RTC_RCR |= RTC_RCR_AIE ) 2652 #define __rtc_disable_alarm_irq() ( REG_RTC_RCR &= ~RTC_RCR_AIE ) 2653 2654 #define __rtc_enable_1hz_irq() ( REG_RTC_RCR |= RTC_RCR_HZIE ) 2655 #define __rtc_disable_1hz_irq() ( REG_RTC_RCR &= ~RTC_RCR_HZIE ) 2656 2657 #define __rtc_is_alarm_flag() ( REG_RTC_RCR & RTC_RCR_AF ) 2658 #define __rtc_is_1hz_flag() ( REG_RTC_RCR & RTC_RCR_HZ ) 2659 #define __rtc_clear_alarm_flag() ( REG_RTC_RCR &= ~RTC_RCR_AF ) 2660 #define __rtc_clear_1hz_flag() ( REG_RTC_RCR &= ~RTC_RCR_HZ ) 2661 2662 #define __rtc_set_second(s) ( REG_RTC_RSR = (s) ) 2663 #define __rtc_get_second() REG_RTC_RSR 2664 #define __rtc_set_alarm(s) ( REG_RTC_RSAR = (s) ) 2665 #define __rtc_get_alarm() REG_RTC_RSAR 2666 2667 #define __rtc_adjust_1hz(f32k) \ 2668 ( REG_RTC_RGR = (REG_RTC_RGR & ~(RTC_REG_DIV_MASK | RTC_RGR_ADJ_MASK)) | f32k | 0 ) 2669 #define __rtc_lock_1hz() ( REG_RTC_RGR |= RTC_RGR_LOCK ) 2670 2671 2672 /*************************************************************************** 2673 * FIR 2674 ***************************************************************************/ 2675 2676 /* enable/disable fir unit */ 2677 #define __fir_enable() ( REG_FIR_CR1 |= FIR_CR1_FIRUE ) 2678 #define __fir_disable() ( REG_FIR_CR1 &= ~FIR_CR1_FIRUE ) 2679 2680 /* enable/disable address comparison */ 2681 #define __fir_enable_ac() ( REG_FIR_CR1 |= FIR_CR1_ACE ) 2682 #define __fir_disable_ac() ( REG_FIR_CR1 &= ~FIR_CR1_ACE ) 2683 2684 /* select frame end mode as underrun or normal */ 2685 #define __fir_set_eous() ( REG_FIR_CR1 |= FIR_CR1_EOUS ) 2686 #define __fir_clear_eous() ( REG_FIR_CR1 &= ~FIR_CR1_EOUS ) 2687 2688 /* enable/disable transmitter idle interrupt */ 2689 #define __fir_enable_tii() ( REG_FIR_CR1 |= FIR_CR1_TIIE ) 2690 #define __fir_disable_tii() ( REG_FIR_CR1 &= ~FIR_CR1_TIIE ) 2691 2692 /* enable/disable transmit FIFO service request interrupt */ 2693 #define __fir_enable_tfi() ( REG_FIR_CR1 |= FIR_CR1_TFIE ) 2694 #define __fir_disable_tfi() ( REG_FIR_CR1 &= ~FIR_CR1_TFIE ) 2695 2696 /* enable/disable receive FIFO service request interrupt */ 2697 #define __fir_enable_rfi() ( REG_FIR_CR1 |= FIR_CR1_RFIE ) 2698 #define __fir_disable_rfi() ( REG_FIR_CR1 &= ~FIR_CR1_RFIE ) 2699 2700 /* enable/disable tx function */ 2701 #define __fir_tx_enable() ( REG_FIR_CR1 |= FIR_CR1_TXE ) 2702 #define __fir_tx_disable() ( REG_FIR_CR1 &= ~FIR_CR1_TXE ) 2703 2704 /* enable/disable rx function */ 2705 #define __fir_rx_enable() ( REG_FIR_CR1 |= FIR_CR1_RXE ) 2706 #define __fir_rx_disable() ( REG_FIR_CR1 &= ~FIR_CR1_RXE ) 2707 2708 2709 /* enable/disable serial infrared interaction pulse (SIP) */ 2710 #define __fir_enable_sip() ( REG_FIR_CR2 |= FIR_CR2_SIPE ) 2711 #define __fir_disable_sip() ( REG_FIR_CR2 &= ~FIR_CR2_SIPE ) 2712 2713 /* un-inverted CRC value is sent out */ 2714 #define __fir_enable_bcrc() ( REG_FIR_CR2 |= FIR_CR2_BCRC ) 2715 2716 /* inverted CRC value is sent out */ 2717 #define __fir_disable_bcrc() ( REG_FIR_CR2 &= ~FIR_CR2_BCRC ) 2718 2719 /* enable/disable Transmit Frame Length Register */ 2720 #define __fir_enable_tflr() ( REG_FIR_CR2 |= FIR_CR2_TFLRS ) 2721 #define __fir_disable_tflr() ( REG_FIR_CR2 &= ~FIR_CR2_TFLRS ) 2722 2723 /* Preamble is transmitted in idle state */ 2724 #define __fir_set_iss() ( REG_FIR_CR2 |= FIR_CR2_ISS ) 2725 2726 /* Abort symbol is transmitted in idle state */ 2727 #define __fir_clear_iss() ( REG_FIR_CR2 &= ~FIR_CR2_ISS ) 2728 2729 /* enable/disable loopback mode */ 2730 #define __fir_enable_loopback() ( REG_FIR_CR2 |= FIR_CR2_LMS ) 2731 #define __fir_disable_loopback() ( REG_FIR_CR2 &= ~FIR_CR2_LMS ) 2732 2733 /* select transmit pin polarity */ 2734 #define __fir_tpp_negative() ( REG_FIR_CR2 |= FIR_CR2_TPPS ) 2735 #define __fir_tpp_positive() ( REG_FIR_CR2 &= ~FIR_CR2_TPPS ) 2736 2737 /* select receive pin polarity */ 2738 #define __fir_rpp_negative() ( REG_FIR_CR2 |= FIR_CR2_RPPS ) 2739 #define __fir_rpp_positive() ( REG_FIR_CR2 &= ~FIR_CR2_RPPS ) 2740 2741 /* n=16,32,64,128 */ 2742 #define __fir_set_txfifo_trigger(n) \ 2743 do { \ 2744 REG_FIR_CR2 &= ~FIR_CR2_TTRG_MASK; \ 2745 REG_FIR_CR2 |= FIR_CR2_TTRG_##n; \ 2746 } while (0) 2747 2748 /* n=16,32,64,128 */ 2749 #define __fir_set_rxfifo_trigger(n) \ 2750 do { \ 2751 REG_FIR_CR2 &= ~FIR_CR2_RTRG_MASK; \ 2752 REG_FIR_CR2 |= FIR_CR2_RTRG_##n; \ 2753 } while (0) 2754 2755 2756 /* FIR status checking */ 2757 2758 #define __fir_test_rfw() ( REG_FIR_SR & FIR_SR_RFW ) 2759 #define __fir_test_rfa() ( REG_FIR_SR & FIR_SR_RFA ) 2760 #define __fir_test_tfrtl() ( REG_FIR_SR & FIR_SR_TFRTL ) 2761 #define __fir_test_rfrtl() ( REG_FIR_SR & FIR_SR_RFRTL ) 2762 #define __fir_test_urun() ( REG_FIR_SR & FIR_SR_URUN ) 2763 #define __fir_test_rfte() ( REG_FIR_SR & FIR_SR_RFTE ) 2764 #define __fir_test_orun() ( REG_FIR_SR & FIR_SR_ORUN ) 2765 #define __fir_test_crce() ( REG_FIR_SR & FIR_SR_CRCE ) 2766 #define __fir_test_fend() ( REG_FIR_SR & FIR_SR_FEND ) 2767 #define __fir_test_tff() ( REG_FIR_SR & FIR_SR_TFF ) 2768 #define __fir_test_rfe() ( REG_FIR_SR & FIR_SR_RFE ) 2769 #define __fir_test_tidle() ( REG_FIR_SR & FIR_SR_TIDLE ) 2770 #define __fir_test_rb() ( REG_FIR_SR & FIR_SR_RB ) 2771 2772 #define __fir_clear_status() \ 2773 do { \ 2774 REG_FIR_SR |= FIR_SR_RFW | FIR_SR_RFA | FIR_SR_URUN; \ 2775 } while (0) 2776 2777 #define __fir_clear_rfw() ( REG_FIR_SR |= FIR_SR_RFW ) 2778 #define __fir_clear_rfa() ( REG_FIR_SR |= FIR_SR_RFA ) 2779 #define __fir_clear_urun() ( REG_FIR_SR |= FIR_SR_URUN ) 2780 2781 #define __fir_set_tflr(len) \ 2782 do { \ 2783 REG_FIR_TFLR = len; \ 2784 } while (0) 2785 2786 #define __fir_set_addr(a) ( REG_FIR_AR = (a) ) 2787 2788 #define __fir_write_data(data) ( REG_FIR_TDR = data ) 2789 #define __fir_read_data(data) ( data = REG_FIR_RDR ) 2790 2791 /*************************************************************************** 2792 * SCC 2793 ***************************************************************************/ 2794 2795 #define __scc_enable(base) ( REG_SCC_CR(base) |= SCC_CR_SCCE ) 2796 #define __scc_disable(base) ( REG_SCC_CR(base) &= ~SCC_CR_SCCE ) 2797 2798 #define __scc_set_tx_mode(base) ( REG_SCC_CR(base) |= SCC_CR_TRS ) 2799 #define __scc_set_rx_mode(base) ( REG_SCC_CR(base) &= ~SCC_CR_TRS ) 2800 2801 #define __scc_enable_t2r(base) ( REG_SCC_CR(base) |= SCC_CR_T2R ) 2802 #define __scc_disable_t2r(base) ( REG_SCC_CR(base) &= ~SCC_CR_T2R ) 2803 2804 #define __scc_clk_as_devclk(base) \ 2805 do { \ 2806 REG_SCC_CR(base) &= ~SCC_CR_FDIV_MASK; \ 2807 REG_SCC_CR(base) |= SCC_CR_FDIV_1; \ 2808 } while (0) 2809 2810 #define __scc_clk_as_half_devclk(base) \ 2811 do { \ 2812 REG_SCC_CR(base) &= ~SCC_CR_FDIV_MASK; \ 2813 REG_SCC_CR(base) |= SCC_CR_FDIV_2; \ 2814 } while (0) 2815 2816 /* n=1,4,8,14 */ 2817 #define __scc_set_fifo_trigger(base, n) \ 2818 do { \ 2819 REG_SCC_CR(base) &= ~SCC_CR_TRIG_MASK; \ 2820 REG_SCC_CR(base) |= SCC_CR_TRIG_##n; \ 2821 } while (0) 2822 2823 #define __scc_set_protocol(base, p) \ 2824 do { \ 2825 if (p) \ 2826 REG_SCC_CR(base) |= SCC_CR_TP; \ 2827 else \ 2828 REG_SCC_CR(base) &= ~SCC_CR_TP; \ 2829 } while (0) 2830 2831 #define __scc_flush_fifo(base) ( REG_SCC_CR(base) |= SCC_CR_FLUSH ) 2832 2833 #define __scc_set_invert_mode(base) ( REG_SCC_CR(base) |= SCC_CR_CONV ) 2834 #define __scc_set_direct_mode(base) ( REG_SCC_CR(base) &= ~SCC_CR_CONV ) 2835 2836 #define SCC_ERR_INTRS \ 2837 ( SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE ) 2838 #define SCC_ALL_INTRS \ 2839 ( SCC_CR_TXIE | SCC_CR_RXIE | SCC_CR_TENDIE | SCC_CR_RTOIE | \ 2840 SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE ) 2841 2842 #define __scc_enable_err_intrs(base) ( REG_SCC_CR(base) |= SCC_ERR_INTRS ) 2843 #define __scc_disable_err_intrs(base) ( REG_SCC_CR(base) &= ~SCC_ERR_INTRS ) 2844 2845 #define SCC_ALL_ERRORS \ 2846 ( SCC_SR_ORER | SCC_SR_RTO | SCC_SR_PER | SCC_SR_RETR_3 | SCC_SR_ECNTO) 2847 2848 #define __scc_clear_errors(base) ( REG_SCC_SR(base) &= ~SCC_ALL_ERRORS ) 2849 2850 #define __scc_enable_all_intrs(base) ( REG_SCC_CR(base) |= SCC_ALL_INTRS ) 2851 #define __scc_disable_all_intrs(base) ( REG_SCC_CR(base) &= ~SCC_ALL_INTRS ) 2852 2853 #define __scc_enable_tx_intr(base) ( REG_SCC_CR(base) |= SCC_CR_TXIE | SCC_CR_TENDIE ) 2854 #define __scc_disable_tx_intr(base) ( REG_SCC_CR(base) &= ~(SCC_CR_TXIE | SCC_CR_TENDIE) ) 2855 2856 #define __scc_enable_rx_intr(base) ( REG_SCC_CR(base) |= SCC_CR_RXIE) 2857 #define __scc_disable_rx_intr(base) ( REG_SCC_CR(base) &= ~SCC_CR_RXIE) 2858 2859 #define __scc_set_tsend(base) ( REG_SCC_CR(base) |= SCC_CR_TSEND ) 2860 #define __scc_clear_tsend(base) ( REG_SCC_CR(base) &= ~SCC_CR_TSEND ) 2861 2862 #define __scc_set_clockstop(base) ( REG_SCC_CR(base) |= SCC_CR_CLKSTP ) 2863 #define __scc_clear_clockstop(base) ( REG_SCC_CR(base) &= ~SCC_CR_CLKSTP ) 2864 2865 #define __scc_clockstop_low(base) \ 2866 do { \ 2867 REG_SCC_CR(base) &= ~SCC_CR_PX_MASK; \ 2868 REG_SCC_CR(base) |= SCC_CR_PX_STOP_LOW; \ 2869 } while (0) 2870 2871 #define __scc_clockstop_high(base) \ 2872 do { \ 2873 REG_SCC_CR(base) &= ~SCC_CR_PX_MASK; \ 2874 REG_SCC_CR(base) |= SCC_CR_PX_STOP_HIGH; \ 2875 } while (0) 2876 2877 2878 /* SCC status checking */ 2879 #define __scc_check_transfer_status(base) ( REG_SCC_SR(base) & SCC_SR_TRANS ) 2880 #define __scc_check_rx_overrun_error(base) ( REG_SCC_SR(base) & SCC_SR_ORER ) 2881 #define __scc_check_rx_timeout(base) ( REG_SCC_SR(base) & SCC_SR_RTO ) 2882 #define __scc_check_parity_error(base) ( REG_SCC_SR(base) & SCC_SR_PER ) 2883 #define __scc_check_txfifo_trigger(base) ( REG_SCC_SR(base) & SCC_SR_TFTG ) 2884 #define __scc_check_rxfifo_trigger(base) ( REG_SCC_SR(base) & SCC_SR_RFTG ) 2885 #define __scc_check_tx_end(base) ( REG_SCC_SR(base) & SCC_SR_TEND ) 2886 #define __scc_check_retx_3(base) ( REG_SCC_SR(base) & SCC_SR_RETR_3 ) 2887 #define __scc_check_ecnt_overflow(base) ( REG_SCC_SR(base) & SCC_SR_ECNTO ) 2888 2889 2890 /*************************************************************************** 2891 * WDT 2892 ***************************************************************************/ 2893 2894 #define __wdt_set_count(count) ( REG_WDT_WTCNT = (count) ) 2895 #define __wdt_start() ( REG_WDT_WTCSR |= WDT_WTCSR_START ) 2896 #define __wdt_stop() ( REG_WDT_WTCSR &= ~WDT_WTCSR_START ) 2897 2898 2899 /*************************************************************************** 2900 * OST 2901 ***************************************************************************/ 2902 2903 #define __ost_enable_all() ( REG_OST_TER |= 0x07 ) 2904 #define __ost_disable_all() ( REG_OST_TER &= ~0x07 ) 2905 #define __ost_enable_channel(n) ( REG_OST_TER |= (1 << (n)) ) 2906 #define __ost_disable_channel(n) ( REG_OST_TER &= ~(1 << (n)) ) 2907 #define __ost_set_reload(n, val) ( REG_OST_TRDR(n) = (val) ) 2908 #define __ost_set_count(n, val) ( REG_OST_TCNT(n) = (val) ) 2909 #define __ost_get_count(n) ( REG_OST_TCNT(n) ) 2910 #define __ost_set_clock(n, cs) ( REG_OST_TCSR(n) |= (cs) ) 2911 #define __ost_set_mode(n, val) ( REG_OST_TCSR(n) = (val) ) 2912 #define __ost_enable_interrupt(n) ( REG_OST_TCSR(n) |= OST_TCSR_UIE ) 2913 #define __ost_disable_interrupt(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_UIE ) 2914 #define __ost_uf_detected(n) ( REG_OST_TCSR(n) & OST_TCSR_UF ) 2915 #define __ost_clear_uf(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_UF ) 2916 #define __ost_is_busy(n) ( REG_OST_TCSR(n) & OST_TCSR_BUSY ) 2917 #define __ost_clear_busy(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_BUSY ) 2918 2919 2920 /*************************************************************************** 2921 * UART 2922 ***************************************************************************/ 2923 2924 #define __uart_enable(n) \ 2925 ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = UARTFCR_UUE | UARTFCR_FE ) 2926 #define __uart_disable(n) \ 2927 ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = ~UARTFCR_UUE ) 2928 2929 #define __uart_enable_transmit_irq(n) \ 2930 ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_TIE ) 2931 #define __uart_disable_transmit_irq(n) \ 2932 ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~UARTIER_TIE ) 2933 2934 #define __uart_enable_receive_irq(n) \ 2935 ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) 2936 #define __uart_disable_receive_irq(n) \ 2937 ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) 2938 2939 #define __uart_enable_loopback(n) \ 2940 ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) |= UARTMCR_LOOP ) 2941 #define __uart_disable_loopback(n) \ 2942 ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) &= ~UARTMCR_LOOP ) 2943 2944 #define __uart_set_8n1(n) \ 2945 ( REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) = UARTLCR_WLEN_8 ) 2946 2947 #define __uart_set_baud(n, devclk, baud) \ 2948 do { \ 2949 REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) |= UARTLCR_DLAB; \ 2950 REG8(UART_BASE + UART_OFF*(n) + OFF_DLLR) = (devclk / 16 / baud) & 0xff; \ 2951 REG8(UART_BASE + UART_OFF*(n) + OFF_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ 2952 REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) &= ~UARTLCR_DLAB; \ 2953 } while (0) 2954 2955 #define __uart_parity_error(n) \ 2956 ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_PER) != 0 ) 2957 2958 #define __uart_clear_errors(n) \ 2959 ( REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTSR_RFER) ) 2960 2961 #define __uart_transmit_fifo_empty(n) \ 2962 ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TDRQ) != 0 ) 2963 2964 #define __uart_transmit_end(n) \ 2965 ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TEMT) != 0 ) 2966 2967 #define __uart_transmit_char(n, ch) \ 2968 REG8(UART_BASE + UART_OFF*(n) + OFF_TDR) = (ch) 2969 2970 #define __uart_receive_fifo_full(n) \ 2971 ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) 2972 2973 #define __uart_receive_ready(n) \ 2974 ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) 2975 2976 #define __uart_receive_char(n) \ 2977 REG8(UART_BASE + UART_OFF*(n) + OFF_RDR) 2978 2979 #define __uart_disable_irda() \ 2980 ( REG8(IRDA_BASE + OFF_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) 2981 #define __uart_enable_irda() \ 2982 /* Tx high pulse as 0, Rx low pulse as 0 */ \ 2983 ( REG8(IRDA_BASE + OFF_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) 2984 2985 2986 /*************************************************************************** 2987 * INTC 2988 ***************************************************************************/ 2989 #define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) 2990 #define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) 2991 #define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) 2992 2993 /*************************************************************************** 2994 * CIM 2995 ***************************************************************************/ 2996 2997 #define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) 2998 #define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) 2999 3000 #define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) 3001 #define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) 3002 3003 #define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) 3004 #define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) 3005 3006 #define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) 3007 #define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) 3008 3009 #define __cim_sample_data_at_pclk_falling_edge() \ 3010 ( REG_CIM_CFG |= CIM_CFG_PCP ) 3011 #define __cim_sample_data_at_pclk_rising_edge() \ 3012 ( REG_CIM_CFG &= ~CIM_CFG_PCP ) 3013 3014 #define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) 3015 #define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) 3016 3017 #define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) 3018 #define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) 3019 3020 /* n=0-7 */ 3021 #define __cim_set_data_packing_mode(n) \ 3022 do { \ 3023 REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ 3024 REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ 3025 } while (0) 3026 3027 #define __cim_enable_ccir656_progressive_mode() \ 3028 do { \ 3029 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 3030 REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ 3031 } while (0) 3032 3033 #define __cim_enable_ccir656_interlace_mode() \ 3034 do { \ 3035 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 3036 REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ 3037 } while (0) 3038 3039 #define __cim_enable_gated_clock_mode() \ 3040 do { \ 3041 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 3042 REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ 3043 } while (0) 3044 3045 #define __cim_enable_nongated_clock_mode() \ 3046 do { \ 3047 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 3048 REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ 3049 } while (0) 3050 3051 /* sclk:system bus clock 3052 * mclk: CIM master clock 3053 */ 3054 #define __cim_set_master_clk(sclk, mclk) \ 3055 do { \ 3056 REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \ 3057 REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \ 3058 } while (0) 3059 3060 #define __cim_enable_sof_intr() \ 3061 ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) 3062 #define __cim_disable_sof_intr() \ 3063 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) 3064 3065 #define __cim_enable_eof_intr() \ 3066 ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) 3067 #define __cim_disable_eof_intr() \ 3068 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) 3069 3070 #define __cim_enable_stop_intr() \ 3071 ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) 3072 #define __cim_disable_stop_intr() \ 3073 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) 3074 3075 #define __cim_enable_trig_intr() \ 3076 ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) 3077 #define __cim_disable_trig_intr() \ 3078 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) 3079 3080 #define __cim_enable_rxfifo_overflow_intr() \ 3081 ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) 3082 #define __cim_disable_rxfifo_overflow_intr() \ 3083 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) 3084 3085 /* n=1-16 */ 3086 #define __cim_set_frame_rate(n) \ 3087 do { \ 3088 REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ 3089 REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ 3090 } while (0) 3091 3092 #define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) 3093 #define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) 3094 3095 #define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) 3096 #define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) 3097 3098 /* n=4,8,12,16,20,24,28,32 */ 3099 #define __cim_set_rxfifo_trigger(n) \ 3100 do { \ 3101 REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \ 3102 REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \ 3103 } while (0) 3104 3105 #define __cim_clear_state() ( REG_CIM_STATE = 0 ) 3106 3107 #define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) 3108 #define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) 3109 #define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) 3110 #define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) 3111 #define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) 3112 #define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) 3113 #define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) 3114 #define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) 3115 3116 #define __cim_get_iid() ( REG_CIM_IID ) 3117 #define __cim_get_image_data() ( REG_CIM_RXFIFO ) 3118 #define __cim_get_dam_cmd() ( REG_CIM_CMD ) 3119 3120 #define __cim_set_da(a) ( REG_CIM_DA = (a) ) 3121 3122 /*************************************************************************** 3123 * PWM 3124 ***************************************************************************/ 3125 3126 /* n is the pwm channel (0,1,..) */ 3127 #define __pwm_enable_module(n) ( REG_PWM_CTR(n) |= PWM_CTR_EN ) 3128 #define __pwm_disable_module(n) ( REG_PWM_CTR(n) &= ~PWM_CTR_EN ) 3129 #define __pwm_graceful_shutdown_mode(n) ( REG_PWM_CTR(n) &= ~PWM_CTR_SD ) 3130 #define __pwm_abrupt_shutdown_mode(n) ( REG_PWM_CTR(n) |= PWM_CTR_SD ) 3131 #define __pwm_set_full_duty(n) ( REG_PWM_DUT(n) |= PWM_DUT_FDUTY ) 3132 3133 #define __pwm_set_prescale(n, p) \ 3134 ( REG_PWM_CTR(n) = ((REG_PWM_CTR(n) & ~PWM_CTR_PRESCALE_MASK) | (p) ) ) 3135 #define __pwm_set_period(n, p) \ 3136 ( REG_PWM_PER(n) = ( (REG_PWM_PER(n) & ~PWM_PER_PERIOD_MASK) | (p) ) ) 3137 #define __pwm_set_duty(n, d) \ 3138 ( REG_PWM_DUT(n) = ( (REG_PWM_DUT(n) & ~PWM_DUT_FDUTY) | (d) ) ) 3139 3140 /*************************************************************************** 3141 * EMC 3142 ***************************************************************************/ 3143 3144 #define __emc_enable_split() ( REG_EMC_BCR = EMC_BCR_BRE ) 3145 #define __emc_disable_split() ( REG_EMC_BCR = 0 ) 3146 3147 #define __emc_smem_bus_width(n) /* 8, 16 or 32*/ \ 3148 ( REG_EMC_SMCR = (REG_EMC_SMCR & EMC_SMCR_BW_MASK) | \ 3149 EMC_SMCR_BW_##n##BIT ) 3150 #define __emc_smem_byte_control() \ 3151 ( REG_EMC_SMCR = (REG_EMC_SMCR | EMC_SMCR_BCM ) 3152 #define __emc_normal_smem() \ 3153 ( REG_EMC_SMCR = (REG_EMC_SMCR & ~EMC_SMCR_SMT ) 3154 #define __emc_burst_smem() \ 3155 ( REG_EMC_SMCR = (REG_EMC_SMCR | EMC_SMCR_SMT ) 3156 #define __emc_smem_burstlen(n) /* 4, 8, 16 or 32 */ \ 3157 ( REG_EMC_SMCR = (REG_EMC_SMCR & EMC_SMCR_BL_MASK) | (EMC_SMCR_BL_##n ) 3158 3159 /*************************************************************************** 3160 * GPIO 3161 ***************************************************************************/ 3162 3163 /* p is the port number (0,1,2,3) 3164 * o is the pin offset (0-31) inside the port 3165 * n is the absolute number of a pin (0-124), regardless of the port 3166 * m is the interrupt manner (low/high/falling/rising) 3167 */ 3168 3169 #define __gpio_port_data(p) ( REG_GPIO_GPDR(p) ) 3170 3171 #define __gpio_port_as_output(p, o) \ 3172 do { \ 3173 unsigned int tmp; \ 3174 REG_GPIO_GPIER(p) &= ~(1 << (o)); \ 3175 REG_GPIO_GPDIR(p) |= (1 << (o)); \ 3176 if (o < 16) { \ 3177 tmp = REG_GPIO_GPALR(p); \ 3178 tmp &= ~(3 << ((o) << 1)); \ 3179 REG_GPIO_GPALR(p) = tmp; \ 3180 } else { \ 3181 tmp = REG_GPIO_GPAUR(p); \ 3182 tmp &= ~(3 << (((o) - 16)<< 1)); \ 3183 REG_GPIO_GPAUR(p) = tmp; \ 3184 } \ 3185 } while (0) 3186 3187 #define __gpio_port_as_input(p, o) \ 3188 do { \ 3189 unsigned int tmp; \ 3190 REG_GPIO_GPIER(p) &= ~(1 << (o)); \ 3191 REG_GPIO_GPDIR(p) &= ~(1 << (o)); \ 3192 if (o < 16) { \ 3193 tmp = REG_GPIO_GPALR(p); \ 3194 tmp &= ~(3 << ((o) << 1)); \ 3195 REG_GPIO_GPALR(p) = tmp; \ 3196 } else { \ 3197 tmp = REG_GPIO_GPAUR(p); \ 3198 tmp &= ~(3 << (((o) - 16)<< 1)); \ 3199 REG_GPIO_GPAUR(p) = tmp; \ 3200 } \ 3201 } while (0) 3202 3203 #define __gpio_as_output(n) \ 3204 do { \ 3205 unsigned int p, o; \ 3206 p = (n) / 32; \ 3207 o = (n) % 32; \ 3208 __gpio_port_as_output(p, o); \ 3209 } while (0) 3210 3211 #define __gpio_as_input(n) \ 3212 do { \ 3213 unsigned int p, o; \ 3214 p = (n) / 32; \ 3215 o = (n) % 32; \ 3216 __gpio_port_as_input(p, o); \ 3217 } while (0) 3218 3219 #define __gpio_set_pin(n) \ 3220 do { \ 3221 unsigned int p, o; \ 3222 p = (n) / 32; \ 3223 o = (n) % 32; \ 3224 __gpio_port_data(p) |= (1 << o); \ 3225 } while (0) 3226 3227 #define __gpio_clear_pin(n) \ 3228 do { \ 3229 unsigned int p, o; \ 3230 p = (n) / 32; \ 3231 o = (n) % 32; \ 3232 __gpio_port_data(p) &= ~(1 << o); \ 3233 } while (0) 3234 3235 static __inline__ unsigned int __gpio_get_pin(unsigned int n) 3236 { 3237 unsigned int p, o; 3238 p = (n) / 32; 3239 o = (n) % 32; 3240 if (__gpio_port_data(p) & (1 << o)) 3241 return 1; 3242 else 3243 return 0; 3244 } 3245 3246 3247 #define __gpio_set_irq_detect_manner(p, o, m) \ 3248 do { \ 3249 unsigned int tmp; \ 3250 if (o < 16) { \ 3251 tmp = REG_GPIO_GPIDLR(p); \ 3252 tmp &= ~(3 << ((o) << 1)); \ 3253 tmp |= ((m) << ((o) << 1)); \ 3254 REG_GPIO_GPIDLR(p) = tmp; \ 3255 } else { \ 3256 o -= 16; \ 3257 tmp = REG_GPIO_GPIDUR(p); \ 3258 tmp &= ~(3 << ((o) << 1)); \ 3259 tmp |= ((m) << ((o) << 1)); \ 3260 REG_GPIO_GPIDUR(p) = tmp; \ 3261 } \ 3262 } while (0) 3263 3264 #define __gpio_port_as_irq(p, o, m) \ 3265 do { \ 3266 __gpio_set_irq_detect_manner(p, o, m); \ 3267 __gpio_port_as_input(p, o); \ 3268 REG_GPIO_GPIER(p) |= (1 << o); \ 3269 } while (0) 3270 3271 #define __gpio_as_irq(n, m) \ 3272 do { \ 3273 unsigned int p, o; \ 3274 p = (n) / 32; \ 3275 o = (n) % 32; \ 3276 __gpio_port_as_irq(p, o, m); \ 3277 } while (0) 3278 3279 3280 #define __gpio_as_irq_high_level(n) __gpio_as_irq(n, GPIO_IRQ_HILEVEL) 3281 #define __gpio_as_irq_low_level(n) __gpio_as_irq(n, GPIO_IRQ_LOLEVEL) 3282 #define __gpio_as_irq_fall_edge(n) __gpio_as_irq(n, GPIO_IRQ_FALLEDG) 3283 #define __gpio_as_irq_rise_edge(n) __gpio_as_irq(n, GPIO_IRQ_RAISEDG) 3284 3285 3286 #define __gpio_mask_irq(n) \ 3287 do { \ 3288 unsigned int p, o; \ 3289 p = (n) / 32; \ 3290 o = (n) % 32; \ 3291 REG_GPIO_GPIER(p) &= ~(1 << o); \ 3292 } while (0) 3293 3294 #define __gpio_unmask_irq(n) \ 3295 do { \ 3296 unsigned int p, o; \ 3297 p = (n) / 32; \ 3298 o = (n) % 32; \ 3299 REG_GPIO_GPIER(n) |= (1 << o); \ 3300 } while (0) 3301 3302 #define __gpio_ack_irq(n) \ 3303 do { \ 3304 unsigned int p, o; \ 3305 p = (n) / 32; \ 3306 o = (n) % 32; \ 3307 REG_GPIO_GPFR(p) |= (1 << o); \ 3308 } while (0) 3309 3310 3311 static __inline__ unsigned int __gpio_get_irq(void) 3312 { 3313 unsigned int tmp, i; 3314 3315 tmp = REG_GPIO_GPFR(3); 3316 for (i=0; i<32; i++) 3317 if (tmp & (1 << i)) 3318 return 0x60 + i; 3319 tmp = REG_GPIO_GPFR(2); 3320 for (i=0; i<32; i++) 3321 if (tmp & (1 << i)) 3322 return 0x40 + i; 3323 tmp = REG_GPIO_GPFR(1); 3324 for (i=0; i<32; i++) 3325 if (tmp & (1 << i)) 3326 return 0x20 + i; 3327 tmp = REG_GPIO_GPFR(0); 3328 for (i=0; i<32; i++) 3329 if (tmp & (1 << i)) 3330 return i; 3331 return 0; 3332 } 3333 3334 #define __gpio_group_irq(n) \ 3335 ({ \ 3336 register int tmp, i; \ 3337 tmp = REG_GPIO_GPFR((n)); \ 3338 for (i=31;i>=0;i--) \ 3339 if (tmp & (1 << i)) \ 3340 break; \ 3341 i; \ 3342 }) 3343 3344 #define __gpio_enable_pull(n) \ 3345 do { \ 3346 unsigned int p, o; \ 3347 p = (n) / 32; \ 3348 o = (n) % 32; \ 3349 REG_GPIO_GPPUR(p) |= (1 << o); \ 3350 } while (0) 3351 3352 #define __gpio_disable_pull(n) \ 3353 do { \ 3354 unsigned int p, o; \ 3355 p = (n) / 32; \ 3356 o = (n) % 32; \ 3357 REG_GPIO_GPPUR(p) &= ~(1 << o); \ 3358 } while (0) 3359 3360 /* Init the alternate function pins */ 3361 3362 3363 #define __gpio_as_ssi() \ 3364 do { \ 3365 REG_GPIO_GPALR(2) &= 0xFC00FFFF; \ 3366 REG_GPIO_GPALR(2) |= 0x01550000; \ 3367 } while (0) 3368 3369 #define __gpio_as_uart3() \ 3370 do { \ 3371 REG_GPIO_GPAUR(0) &= 0xFFFF0000; \ 3372 REG_GPIO_GPAUR(0) |= 0x00005555; \ 3373 } while (0) 3374 3375 #define __gpio_as_uart2() \ 3376 do { \ 3377 REG_GPIO_GPALR(3) &= 0x3FFFFFFF; \ 3378 REG_GPIO_GPALR(3) |= 0x40000000; \ 3379 REG_GPIO_GPAUR(3) &= 0xF3FFFFFF; \ 3380 REG_GPIO_GPAUR(3) |= 0x04000000; \ 3381 } while (0) 3382 3383 #define __gpio_as_uart1() \ 3384 do { \ 3385 REG_GPIO_GPAUR(0) &= 0xFFF0FFFF; \ 3386 REG_GPIO_GPAUR(0) |= 0x00050000; \ 3387 } while (0) 3388 3389 #define __gpio_as_uart0() \ 3390 do { \ 3391 REG_GPIO_GPAUR(3) &= 0x0FFFFFFF; \ 3392 REG_GPIO_GPAUR(3) |= 0x50000000; \ 3393 } while (0) 3394 3395 3396 #define __gpio_as_scc0() \ 3397 do { \ 3398 REG_GPIO_GPALR(2) &= 0xFFFFFFCC; \ 3399 REG_GPIO_GPALR(2) |= 0x00000011; \ 3400 } while (0) 3401 3402 #define __gpio_as_scc1() \ 3403 do { \ 3404 REG_GPIO_GPALR(2) &= 0xFFFFFF33; \ 3405 REG_GPIO_GPALR(2) |= 0x00000044; \ 3406 } while (0) 3407 3408 #define __gpio_as_scc() \ 3409 do { \ 3410 __gpio_as_scc0(); \ 3411 __gpio_as_scc1(); \ 3412 } while (0) 3413 3414 #define __gpio_as_dma() \ 3415 do { \ 3416 REG_GPIO_GPALR(0) &= 0x00FFFFFF; \ 3417 REG_GPIO_GPALR(0) |= 0x55000000; \ 3418 REG_GPIO_GPAUR(0) &= 0xFF0FFFFF; \ 3419 REG_GPIO_GPAUR(0) |= 0x00500000; \ 3420 } while (0) 3421 3422 #define __gpio_as_msc() \ 3423 do { \ 3424 REG_GPIO_GPALR(1) &= 0xFFFF000F; \ 3425 REG_GPIO_GPALR(1) |= 0x00005550; \ 3426 } while (0) 3427 3428 #define __gpio_as_pcmcia() \ 3429 do { \ 3430 REG_GPIO_GPAUR(2) &= 0xF000FFFF; \ 3431 REG_GPIO_GPAUR(2) |= 0x05550000; \ 3432 } while (0) 3433 3434 #define __gpio_as_emc() \ 3435 do { \ 3436 REG_GPIO_GPALR(2) &= 0x3FFFFFFF; \ 3437 REG_GPIO_GPALR(2) |= 0x40000000; \ 3438 REG_GPIO_GPAUR(2) &= 0xFFFF0000; \ 3439 REG_GPIO_GPAUR(2) |= 0x00005555; \ 3440 } while (0) 3441 3442 #define __gpio_as_lcd_slave() \ 3443 do { \ 3444 REG_GPIO_GPALR(1) &= 0x0000FFFF; \ 3445 REG_GPIO_GPALR(1) |= 0x55550000; \ 3446 REG_GPIO_GPAUR(1) &= 0x00000000; \ 3447 REG_GPIO_GPAUR(1) |= 0x55555555; \ 3448 } while (0) 3449 3450 #define __gpio_as_lcd_master() \ 3451 do { \ 3452 REG_GPIO_GPALR(1) &= 0x0000FFFF; \ 3453 REG_GPIO_GPALR(1) |= 0x55550000; \ 3454 REG_GPIO_GPAUR(1) &= 0x00000000; \ 3455 REG_GPIO_GPAUR(1) |= 0x556A5555; \ 3456 } while (0) 3457 3458 #define __gpio_as_usb() \ 3459 do { \ 3460 REG_GPIO_GPAUR(0) &= 0x00FFFFFF; \ 3461 REG_GPIO_GPAUR(0) |= 0x55000000; \ 3462 } while (0) 3463 3464 #define __gpio_as_ac97() \ 3465 do { \ 3466 REG_GPIO_GPALR(2) &= 0xC3FF03FF; \ 3467 REG_GPIO_GPALR(2) |= 0x24005400; \ 3468 } while (0) 3469 3470 #define __gpio_as_i2s_slave() \ 3471 do { \ 3472 REG_GPIO_GPALR(2) &= 0xC3FF0CFF; \ 3473 REG_GPIO_GPALR(2) |= 0x14005100; \ 3474 } while (0) 3475 3476 #define __gpio_as_i2s_master() \ 3477 do { \ 3478 REG_GPIO_GPALR(2) &= 0xC3FF0CFF; \ 3479 REG_GPIO_GPALR(2) |= 0x28005100; \ 3480 } while (0) 3481 3482 #define __gpio_as_eth() \ 3483 do { \ 3484 REG_GPIO_GPAUR(3) &= 0xFC000000; \ 3485 REG_GPIO_GPAUR(3) |= 0x01555555; \ 3486 } while (0) 3487 3488 #define __gpio_as_pwm() \ 3489 do { \ 3490 REG_GPIO_GPAUR(2) &= 0x0FFFFFFF; \ 3491 REG_GPIO_GPAUR(2) |= 0x50000000; \ 3492 } while (0) 3493 3494 #define __gpio_as_ps2() \ 3495 do { \ 3496 REG_GPIO_GPALR(1) &= 0xFFFFFFF0; \ 3497 REG_GPIO_GPALR(1) |= 0x00000005; \ 3498 } while (0) 3499 3500 #define __gpio_as_uprt() \ 3501 do { \ 3502 REG_GPIO_GPALR(1) &= 0x0000000F; \ 3503 REG_GPIO_GPALR(1) |= 0x55555550; \ 3504 REG_GPIO_GPALR(3) &= 0xC0000000; \ 3505 REG_GPIO_GPALR(3) |= 0x15555555; \ 3506 } while (0) 3507 3508 #define __gpio_as_cim() \ 3509 do { \ 3510 REG_GPIO_GPALR(0) &= 0xFF000000; \ 3511 REG_GPIO_GPALR(0) |= 0x00555555; \ 3512 } while (0) 3513 3514 /*************************************************************************** 3515 * HARB 3516 ***************************************************************************/ 3517 3518 #define __harb_usb0_udc() \ 3519 do { \ 3520 REG_HARB_HAPOR &= ~HARB_HAPOR_UCHSEL; \ 3521 } while (0) 3522 3523 #define __harb_usb0_uhc() \ 3524 do { \ 3525 REG_HARB_HAPOR |= HARB_HAPOR_UCHSEL; \ 3526 } while (0) 3527 3528 #define __harb_set_priority(n) \ 3529 do { \ 3530 REG_HARB_HAPOR = ((REG_HARB_HAPOR & ~HARB_HAPOR_PRIO_MASK) | n); \ 3531 } while (0) 3532 3533 /*************************************************************************** 3534 * I2C 3535 ***************************************************************************/ 3536 3537 #define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE ) 3538 #define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE ) 3539 3540 #define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA ) 3541 #define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO ) 3542 #define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC ) 3543 #define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC ) 3544 3545 #define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF ) 3546 #define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF ) 3547 #define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF ) 3548 3549 #define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) ) 3550 #define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY ) 3551 #define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND ) 3552 3553 #define __i2c_set_clk(dev_clk, i2c_clk) \ 3554 ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) 3555 3556 #define __i2c_read() ( REG_I2C_DR ) 3557 #define __i2c_write(val) ( REG_I2C_DR = (val) ) 3558 3559 /*************************************************************************** 3560 * UDC 3561 ***************************************************************************/ 3562 3563 #define __udc_set_16bit_phy() ( REG_UDC_DevCFGR |= UDC_DevCFGR_PI ) 3564 #define __udc_set_8bit_phy() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_PI ) 3565 3566 #define __udc_enable_sync_frame() ( REG_UDC_DevCFGR |= UDC_DevCFGR_SS ) 3567 #define __udc_disable_sync_frame() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_SS ) 3568 3569 #define __udc_self_powered() ( REG_UDC_DevCFGR |= UDC_DevCFGR_SP ) 3570 #define __udc_bus_powered() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_SP ) 3571 3572 #define __udc_enable_remote_wakeup() ( REG_UDC_DevCFGR |= UDC_DevCFGR_RW ) 3573 #define __udc_disable_remote_wakeup() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_RW ) 3574 3575 #define __udc_set_speed_high() \ 3576 do { \ 3577 REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ 3578 REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_HS; \ 3579 } while (0) 3580 3581 #define __udc_set_speed_full() \ 3582 do { \ 3583 REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ 3584 REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_FS; \ 3585 } while (0) 3586 3587 #define __udc_set_speed_low() \ 3588 do { \ 3589 REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ 3590 REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_LS; \ 3591 } while (0) 3592 3593 3594 #define __udc_set_dma_mode() ( REG_UDC_DevCR |= UDC_DevCR_DM ) 3595 #define __udc_set_slave_mode() ( REG_UDC_DevCR &= ~UDC_DevCR_DM ) 3596 #define __udc_set_big_endian() ( REG_UDC_DevCR |= UDC_DevCR_BE ) 3597 #define __udc_set_little_endian() ( REG_UDC_DevCR &= ~UDC_DevCR_BE ) 3598 #define __udc_generate_resume() ( REG_UDC_DevCR |= UDC_DevCR_RES ) 3599 #define __udc_clear_resume() ( REG_UDC_DevCR &= ~UDC_DevCR_RES ) 3600 3601 3602 #define __udc_get_enumarated_speed() ( REG_UDC_DevSR & UDC_DevSR_ENUMSPD_MASK ) 3603 #define __udc_suspend_detected() ( REG_UDC_DevSR & UDC_DevSR_SUSP ) 3604 #define __udc_get_alternate_setting() ( (REG_UDC_DevSR & UDC_DevSR_ALT_MASK) >> UDC_DevSR_ALT_BIT ) 3605 #define __udc_get_interface_number() ( (REG_UDC_DevSR & UDC_DevSR_INTF_MASK) >> UDC_DevSR_INTF_BIT ) 3606 #define __udc_get_config_number() ( (REG_UDC_DevSR & UDC_DevSR_CFG_MASK) >> UDC_DevSR_CFG_BIT ) 3607 3608 3609 #define __udc_sof_detected(r) ( (r) & UDC_DevIntR_SOF ) 3610 #define __udc_usb_suspend_detected(r) ( (r) & UDC_DevIntR_US ) 3611 #define __udc_usb_reset_detected(r) ( (r) & UDC_DevIntR_UR ) 3612 #define __udc_set_interface_detected(r) ( (r) & UDC_DevIntR_SI ) 3613 #define __udc_set_config_detected(r) ( (r) & UDC_DevIntR_SC ) 3614 3615 #define __udc_clear_sof() ( REG_UDC_DevIntR |= UDC_DevIntR_SOF ) 3616 #define __udc_clear_usb_suspend() ( REG_UDC_DevIntR |= UDC_DevIntR_US ) 3617 #define __udc_clear_usb_reset() ( REG_UDC_DevIntR |= UDC_DevIntR_UR ) 3618 #define __udc_clear_set_interface() ( REG_UDC_DevIntR |= UDC_DevIntR_SI ) 3619 #define __udc_clear_set_config() ( REG_UDC_DevIntR |= UDC_DevIntR_SC ) 3620 3621 #define __udc_mask_sof() ( REG_UDC_DevIntMR |= UDC_DevIntR_SOF ) 3622 #define __udc_mask_usb_suspend() ( REG_UDC_DevIntMR |= UDC_DevIntR_US ) 3623 #define __udc_mask_usb_reset() ( REG_UDC_DevIntMR |= UDC_DevIntR_UR ) 3624 #define __udc_mask_set_interface() ( REG_UDC_DevIntMR |= UDC_DevIntR_SI ) 3625 #define __udc_mask_set_config() ( REG_UDC_DevIntMR |= UDC_DevIntR_SC ) 3626 #define __udc_mask_all_dev_intrs() \ 3627 ( REG_UDC_DevIntMR = UDC_DevIntR_SOF | UDC_DevIntR_US | \ 3628 UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC ) 3629 3630 #define __udc_unmask_sof() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SOF ) 3631 #define __udc_unmask_usb_suspend() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_US ) 3632 #define __udc_unmask_usb_reset() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_UR ) 3633 #define __udc_unmask_set_interface() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SI ) 3634 #define __udc_unmask_set_config() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SC ) 3635 #if 0 3636 #define __udc_unmask_all_dev_intrs() \ 3637 ( REG_UDC_DevIntMR = ~(UDC_DevIntR_SOF | UDC_DevIntR_US | \ 3638 UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC) ) 3639 #else 3640 #define __udc_unmask_all_dev_intrs() \ 3641 ( REG_UDC_DevIntMR = 0x00000000 ) 3642 #endif 3643 3644 3645 #define __udc_ep0out_irq_detected(epintr) \ 3646 ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 0)) & 0x1 ) 3647 #define __udc_ep5out_irq_detected(epintr) \ 3648 ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 5)) & 0x1 ) 3649 #define __udc_ep6out_irq_detected(epintr) \ 3650 ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 6)) & 0x1 ) 3651 #define __udc_ep7out_irq_detected(epintr) \ 3652 ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 7)) & 0x1 ) 3653 3654 #define __udc_ep0in_irq_detected(epintr) \ 3655 ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 0)) & 0x1 ) 3656 #define __udc_ep1in_irq_detected(epintr) \ 3657 ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 1)) & 0x1 ) 3658 #define __udc_ep2in_irq_detected(epintr) \ 3659 ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 2)) & 0x1 ) 3660 #define __udc_ep3in_irq_detected(epintr) \ 3661 ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 3)) & 0x1 ) 3662 #define __udc_ep4in_irq_detected(epintr) \ 3663 ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 4)) & 0x1 ) 3664 3665 3666 #define __udc_mask_ep0out_irq() \ 3667 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 0)) ) 3668 #define __udc_mask_ep5out_irq() \ 3669 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 5)) ) 3670 #define __udc_mask_ep6out_irq() \ 3671 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 6)) ) 3672 #define __udc_mask_ep7out_irq() \ 3673 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 7)) ) 3674 3675 #define __udc_unmask_ep0out_irq() \ 3676 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 0)) ) 3677 #define __udc_unmask_ep5out_irq() \ 3678 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 5)) ) 3679 #define __udc_unmask_ep6out_irq() \ 3680 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 6)) ) 3681 #define __udc_unmask_ep7out_irq() \ 3682 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 7)) ) 3683 3684 #define __udc_mask_ep0in_irq() \ 3685 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 0)) ) 3686 #define __udc_mask_ep1in_irq() \ 3687 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 1)) ) 3688 #define __udc_mask_ep2in_irq() \ 3689 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 2)) ) 3690 #define __udc_mask_ep3in_irq() \ 3691 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 3)) ) 3692 #define __udc_mask_ep4in_irq() \ 3693 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 4)) ) 3694 3695 #define __udc_unmask_ep0in_irq() \ 3696 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 0)) ) 3697 #define __udc_unmask_ep1in_irq() \ 3698 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 1)) ) 3699 #define __udc_unmask_ep2in_irq() \ 3700 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 2)) ) 3701 #define __udc_unmask_ep3in_irq() \ 3702 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 3)) ) 3703 #define __udc_unmask_ep4in_irq() \ 3704 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 4)) ) 3705 3706 #define __udc_mask_all_ep_intrs() \ 3707 ( REG_UDC_EPIntMR = 0xffffffff ) 3708 #define __udc_unmask_all_ep_intrs() \ 3709 ( REG_UDC_EPIntMR = 0x00000000 ) 3710 3711 3712 /* ep0 only CTRL, ep1 only INTR, ep2/3/5/6 only BULK, ep4/7 only ISO */ 3713 #define __udc_config_endpoint_type() \ 3714 do { \ 3715 REG_UDC_EP0InCR = (REG_UDC_EP0InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL; \ 3716 REG_UDC_EP0OutCR = (REG_UDC_EP0OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL; \ 3717 REG_UDC_EP1InCR = (REG_UDC_EP1InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_INTR; \ 3718 REG_UDC_EP2InCR = (REG_UDC_EP2InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ 3719 REG_UDC_EP3InCR = (REG_UDC_EP3InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ 3720 REG_UDC_EP4InCR = (REG_UDC_EP4InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO; \ 3721 REG_UDC_EP5OutCR = (REG_UDC_EP5OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ 3722 REG_UDC_EP6OutCR = (REG_UDC_EP6OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ 3723 REG_UDC_EP7OutCR = (REG_UDC_EP7OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO; \ 3724 } while (0) 3725 3726 #define __udc_enable_ep0out_snoop_mode() ( REG_UDC_EP0OutCR |= UDC_EPCR_SN ) 3727 #define __udc_enable_ep5out_snoop_mode() ( REG_UDC_EP5OutCR |= UDC_EPCR_SN ) 3728 #define __udc_enable_ep6out_snoop_mode() ( REG_UDC_EP6OutCR |= UDC_EPCR_SN ) 3729 #define __udc_enable_ep7out_snoop_mode() ( REG_UDC_EP7OutCR |= UDC_EPCR_SN ) 3730 3731 #define __udc_disable_ep0out_snoop_mode() ( REG_UDC_EP0OutCR &= ~UDC_EPCR_SN ) 3732 #define __udc_disable_ep5out_snoop_mode() ( REG_UDC_EP5OutCR &= ~UDC_EPCR_SN ) 3733 #define __udc_disable_ep6out_snoop_mode() ( REG_UDC_EP6OutCR &= ~UDC_EPCR_SN ) 3734 #define __udc_disable_ep7out_snoop_mode() ( REG_UDC_EP7OutCR &= ~UDC_EPCR_SN ) 3735 3736 #define __udc_flush_ep0in_fifo() ( REG_UDC_EP0InCR |= UDC_EPCR_F ) 3737 #define __udc_flush_ep1in_fifo() ( REG_UDC_EP1InCR |= UDC_EPCR_F ) 3738 #define __udc_flush_ep2in_fifo() ( REG_UDC_EP2InCR |= UDC_EPCR_F ) 3739 #define __udc_flush_ep3in_fifo() ( REG_UDC_EP3InCR |= UDC_EPCR_F ) 3740 #define __udc_flush_ep4in_fifo() ( REG_UDC_EP4InCR |= UDC_EPCR_F ) 3741 3742 #define __udc_unflush_ep0in_fifo() ( REG_UDC_EP0InCR &= ~UDC_EPCR_F ) 3743 #define __udc_unflush_ep1in_fifo() ( REG_UDC_EP1InCR &= ~UDC_EPCR_F ) 3744 #define __udc_unflush_ep2in_fifo() ( REG_UDC_EP2InCR &= ~UDC_EPCR_F ) 3745 #define __udc_unflush_ep3in_fifo() ( REG_UDC_EP3InCR &= ~UDC_EPCR_F ) 3746 #define __udc_unflush_ep4in_fifo() ( REG_UDC_EP4InCR &= ~UDC_EPCR_F ) 3747 3748 #define __udc_enable_ep0in_stall() ( REG_UDC_EP0InCR |= UDC_EPCR_S ) 3749 #define __udc_enable_ep0out_stall() ( REG_UDC_EP0OutCR |= UDC_EPCR_S ) 3750 #define __udc_enable_ep1in_stall() ( REG_UDC_EP1InCR |= UDC_EPCR_S ) 3751 #define __udc_enable_ep2in_stall() ( REG_UDC_EP2InCR |= UDC_EPCR_S ) 3752 #define __udc_enable_ep3in_stall() ( REG_UDC_EP3InCR |= UDC_EPCR_S ) 3753 #define __udc_enable_ep4in_stall() ( REG_UDC_EP4InCR |= UDC_EPCR_S ) 3754 #define __udc_enable_ep5out_stall() ( REG_UDC_EP5OutCR |= UDC_EPCR_S ) 3755 #define __udc_enable_ep6out_stall() ( REG_UDC_EP6OutCR |= UDC_EPCR_S ) 3756 #define __udc_enable_ep7out_stall() ( REG_UDC_EP7OutCR |= UDC_EPCR_S ) 3757 3758 #define __udc_disable_ep0in_stall() ( REG_UDC_EP0InCR &= ~UDC_EPCR_S ) 3759 #define __udc_disable_ep0out_stall() ( REG_UDC_EP0OutCR &= ~UDC_EPCR_S ) 3760 #define __udc_disable_ep1in_stall() ( REG_UDC_EP1InCR &= ~UDC_EPCR_S ) 3761 #define __udc_disable_ep2in_stall() ( REG_UDC_EP2InCR &= ~UDC_EPCR_S ) 3762 #define __udc_disable_ep3in_stall() ( REG_UDC_EP3InCR &= ~UDC_EPCR_S ) 3763 #define __udc_disable_ep4in_stall() ( REG_UDC_EP4InCR &= ~UDC_EPCR_S ) 3764 #define __udc_disable_ep5out_stall() ( REG_UDC_EP5OutCR &= ~UDC_EPCR_S ) 3765 #define __udc_disable_ep6out_stall() ( REG_UDC_EP6OutCR &= ~UDC_EPCR_S ) 3766 #define __udc_disable_ep7out_stall() ( REG_UDC_EP7OutCR &= ~UDC_EPCR_S ) 3767 3768 3769 #define __udc_ep0out_packet_size() \ 3770 ( (REG_UDC_EP0OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) 3771 #define __udc_ep5out_packet_size() \ 3772 ( (REG_UDC_EP5OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) 3773 #define __udc_ep6out_packet_size() \ 3774 ( (REG_UDC_EP6OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) 3775 #define __udc_ep7out_packet_size() \ 3776 ( (REG_UDC_EP7OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) 3777 3778 #define __udc_ep0in_received_intoken() ( (REG_UDC_EP0InSR & UDC_EPSR_IN) ) 3779 #define __udc_ep1in_received_intoken() ( (REG_UDC_EP1InSR & UDC_EPSR_IN) ) 3780 #define __udc_ep2in_received_intoken() ( (REG_UDC_EP2InSR & UDC_EPSR_IN) ) 3781 #define __udc_ep3in_received_intoken() ( (REG_UDC_EP3InSR & UDC_EPSR_IN) ) 3782 #define __udc_ep4in_received_intoken() ( (REG_UDC_EP4InSR & UDC_EPSR_IN) ) 3783 3784 #define __udc_ep0out_received_none() \ 3785 ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) 3786 #define __udc_ep0out_received_data() \ 3787 ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) 3788 #define __udc_ep0out_received_setup() \ 3789 ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) 3790 3791 #define __udc_ep5out_received_none() \ 3792 ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) 3793 #define __udc_ep5out_received_data() \ 3794 ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) 3795 #define __udc_ep5out_received_setup() \ 3796 ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) 3797 3798 #define __udc_ep6out_received_none() \ 3799 ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) 3800 #define __udc_ep6out_received_data() \ 3801 ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) 3802 #define __udc_ep6out_received_setup() \ 3803 ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) 3804 3805 #define __udc_ep7out_received_none() \ 3806 ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) 3807 #define __udc_ep7out_received_data() \ 3808 ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) 3809 #define __udc_ep7out_received_setup() \ 3810 ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) 3811 3812 /* ep7out ISO only */ 3813 #define __udc_ep7out_get_pid() \ 3814 ( (REG_UDC_EP7OutSR & UDC_EPSR_PID_MASK) >> UDC_EPSR_PID_BIT ) 3815 3816 3817 #define __udc_ep0in_set_buffer_size(n) ( REG_UDC_EP0InBSR = (n) ) 3818 #define __udc_ep1in_set_buffer_size(n) ( REG_UDC_EP1InBSR = (n) ) 3819 #define __udc_ep2in_set_buffer_size(n) ( REG_UDC_EP2InBSR = (n) ) 3820 #define __udc_ep3in_set_buffer_size(n) ( REG_UDC_EP3InBSR = (n) ) 3821 #define __udc_ep4in_set_buffer_size(n) ( REG_UDC_EP4InBSR = (n) ) 3822 3823 #define __udc_ep0out_get_frame_number(n) ( UDC_EP0OutPFNR ) 3824 #define __udc_ep5out_get_frame_number(n) ( UDC_EP5OutPFNR ) 3825 #define __udc_ep6out_get_frame_number(n) ( UDC_EP6OutPFNR ) 3826 #define __udc_ep7out_get_frame_number(n) ( UDC_EP7OutPFNR ) 3827 3828 3829 #define __udc_ep0in_set_max_packet_size(n) ( REG_UDC_EP0InMPSR = (n) ) 3830 #define __udc_ep0out_set_max_packet_size(n) ( REG_UDC_EP0OutMPSR = (n) ) 3831 #define __udc_ep1in_set_max_packet_size(n) ( REG_UDC_EP1InMPSR = (n) ) 3832 #define __udc_ep2in_set_max_packet_size(n) ( REG_UDC_EP2InMPSR = (n) ) 3833 #define __udc_ep3in_set_max_packet_size(n) ( REG_UDC_EP3InMPSR = (n) ) 3834 #define __udc_ep4in_set_max_packet_size(n) ( REG_UDC_EP4InMPSR = (n) ) 3835 #define __udc_ep5out_set_max_packet_size(n) ( REG_UDC_EP5OutMPSR = (n) ) 3836 #define __udc_ep6out_set_max_packet_size(n) ( REG_UDC_EP6OutMPSR = (n) ) 3837 #define __udc_ep7out_set_max_packet_size(n) ( REG_UDC_EP7OutMPSR = (n) ) 3838 3839 /* set to 0xFFFF for UDC */ 3840 #define __udc_set_setup_command_address(n) ( REG_UDC_STCMAR = (n) ) 3841 3842 /* Init and configure EPxInfR(x=0,1,2,3,4,5,6,7) 3843 * c: Configuration number to which this endpoint belongs 3844 * i: Interface number to which this endpoint belongs 3845 * a: Alternate setting to which this endpoint belongs 3846 * p: max Packet size of this endpoint 3847 */ 3848 3849 #define __udc_ep0info_init(c,i,a,p) \ 3850 do { \ 3851 REG_UDC_EP0InfR &= ~UDC_EPInfR_MPS_MASK; \ 3852 REG_UDC_EP0InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ 3853 REG_UDC_EP0InfR &= ~UDC_EPInfR_ALTS_MASK; \ 3854 REG_UDC_EP0InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ 3855 REG_UDC_EP0InfR &= ~UDC_EPInfR_IFN_MASK; \ 3856 REG_UDC_EP0InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ 3857 REG_UDC_EP0InfR &= ~UDC_EPInfR_CGN_MASK; \ 3858 REG_UDC_EP0InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ 3859 REG_UDC_EP0InfR &= ~UDC_EPInfR_EPT_MASK; \ 3860 REG_UDC_EP0InfR |= UDC_EPInfR_EPT_CTRL; \ 3861 REG_UDC_EP0InfR &= ~UDC_EPInfR_EPD; \ 3862 REG_UDC_EP0InfR |= UDC_EPInfR_EPD_OUT; \ 3863 REG_UDC_EP0InfR &= ~UDC_EPInfR_EPN_MASK; \ 3864 REG_UDC_EP0InfR |= (0 << UDC_EPInfR_EPN_BIT); \ 3865 } while (0) 3866 3867 #define __udc_ep1info_init(c,i,a,p) \ 3868 do { \ 3869 REG_UDC_EP1InfR &= ~UDC_EPInfR_MPS_MASK; \ 3870 REG_UDC_EP1InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ 3871 REG_UDC_EP1InfR &= ~UDC_EPInfR_ALTS_MASK; \ 3872 REG_UDC_EP1InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ 3873 REG_UDC_EP1InfR &= ~UDC_EPInfR_IFN_MASK; \ 3874 REG_UDC_EP1InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ 3875 REG_UDC_EP1InfR &= ~UDC_EPInfR_CGN_MASK; \ 3876 REG_UDC_EP1InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ 3877 REG_UDC_EP1InfR &= ~UDC_EPInfR_EPT_MASK; \ 3878 REG_UDC_EP1InfR |= UDC_EPInfR_EPT_INTR; \ 3879 REG_UDC_EP1InfR &= ~UDC_EPInfR_EPD; \ 3880 REG_UDC_EP1InfR |= UDC_EPInfR_EPD_IN; \ 3881 REG_UDC_EP1InfR &= ~UDC_EPInfR_EPN_MASK; \ 3882 REG_UDC_EP1InfR |= (1 << UDC_EPInfR_EPN_BIT); \ 3883 } while (0) 3884 3885 #define __udc_ep2info_init(c,i,a,p) \ 3886 do { \ 3887 REG_UDC_EP2InfR &= ~UDC_EPInfR_MPS_MASK; \ 3888 REG_UDC_EP2InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ 3889 REG_UDC_EP2InfR &= ~UDC_EPInfR_ALTS_MASK; \ 3890 REG_UDC_EP2InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ 3891 REG_UDC_EP2InfR &= ~UDC_EPInfR_IFN_MASK; \ 3892 REG_UDC_EP2InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ 3893 REG_UDC_EP2InfR &= ~UDC_EPInfR_CGN_MASK; \ 3894 REG_UDC_EP2InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ 3895 REG_UDC_EP2InfR &= ~UDC_EPInfR_EPT_MASK; \ 3896 REG_UDC_EP2InfR |= UDC_EPInfR_EPT_BULK; \ 3897 REG_UDC_EP2InfR &= ~UDC_EPInfR_EPD; \ 3898 REG_UDC_EP2InfR |= UDC_EPInfR_EPD_IN; \ 3899 REG_UDC_EP2InfR &= ~UDC_EPInfR_EPN_MASK; \ 3900 REG_UDC_EP2InfR |= (2 << UDC_EPInfR_EPN_BIT); \ 3901 } while (0) 3902 3903 #define __udc_ep3info_init(c,i,a,p) \ 3904 do { \ 3905 REG_UDC_EP3InfR &= ~UDC_EPInfR_MPS_MASK; \ 3906 REG_UDC_EP3InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ 3907 REG_UDC_EP3InfR &= ~UDC_EPInfR_ALTS_MASK; \ 3908 REG_UDC_EP3InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ 3909 REG_UDC_EP3InfR &= ~UDC_EPInfR_IFN_MASK; \ 3910 REG_UDC_EP3InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ 3911 REG_UDC_EP3InfR &= ~UDC_EPInfR_CGN_MASK; \ 3912 REG_UDC_EP3InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ 3913 REG_UDC_EP3InfR &= ~UDC_EPInfR_EPT_MASK; \ 3914 REG_UDC_EP3InfR |= UDC_EPInfR_EPT_BULK; \ 3915 REG_UDC_EP3InfR &= ~UDC_EPInfR_EPD; \ 3916 REG_UDC_EP3InfR |= UDC_EPInfR_EPD_IN; \ 3917 REG_UDC_EP3InfR &= ~UDC_EPInfR_EPN_MASK; \ 3918 REG_UDC_EP3InfR |= (3 << UDC_EPInfR_EPN_BIT); \ 3919 } while (0) 3920 3921 #define __udc_ep4info_init(c,i,a,p) \ 3922 do { \ 3923 REG_UDC_EP4InfR &= ~UDC_EPInfR_MPS_MASK; \ 3924 REG_UDC_EP4InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ 3925 REG_UDC_EP4InfR &= ~UDC_EPInfR_ALTS_MASK; \ 3926 REG_UDC_EP4InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ 3927 REG_UDC_EP4InfR &= ~UDC_EPInfR_IFN_MASK; \ 3928 REG_UDC_EP4InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ 3929 REG_UDC_EP4InfR &= ~UDC_EPInfR_CGN_MASK; \ 3930 REG_UDC_EP4InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ 3931 REG_UDC_EP4InfR &= ~UDC_EPInfR_EPT_MASK; \ 3932 REG_UDC_EP4InfR |= UDC_EPInfR_EPT_ISO; \ 3933 REG_UDC_EP4InfR &= ~UDC_EPInfR_EPD; \ 3934 REG_UDC_EP4InfR |= UDC_EPInfR_EPD_IN; \ 3935 REG_UDC_EP4InfR &= ~UDC_EPInfR_EPN_MASK; \ 3936 REG_UDC_EP4InfR |= (4 << UDC_EPInfR_EPN_BIT); \ 3937 } while (0) 3938 3939 #define __udc_ep5info_init(c,i,a,p) \ 3940 do { \ 3941 REG_UDC_EP5InfR &= ~UDC_EPInfR_MPS_MASK; \ 3942 REG_UDC_EP5InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ 3943 REG_UDC_EP5InfR &= ~UDC_EPInfR_ALTS_MASK; \ 3944 REG_UDC_EP5InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ 3945 REG_UDC_EP5InfR &= ~UDC_EPInfR_IFN_MASK; \ 3946 REG_UDC_EP5InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ 3947 REG_UDC_EP5InfR &= ~UDC_EPInfR_CGN_MASK; \ 3948 REG_UDC_EP5InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ 3949 REG_UDC_EP5InfR &= ~UDC_EPInfR_EPT_MASK; \ 3950 REG_UDC_EP5InfR |= UDC_EPInfR_EPT_BULK; \ 3951 REG_UDC_EP5InfR &= ~UDC_EPInfR_EPD; \ 3952 REG_UDC_EP5InfR |= UDC_EPInfR_EPD_OUT; \ 3953 REG_UDC_EP5InfR &= ~UDC_EPInfR_EPN_MASK; \ 3954 REG_UDC_EP5InfR |= (5 << UDC_EPInfR_EPN_BIT); \ 3955 } while (0) 3956 3957 #define __udc_ep6info_init(c,i,a,p) \ 3958 do { \ 3959 REG_UDC_EP6InfR &= ~UDC_EPInfR_MPS_MASK; \ 3960 REG_UDC_EP6InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ 3961 REG_UDC_EP6InfR &= ~UDC_EPInfR_ALTS_MASK; \ 3962 REG_UDC_EP6InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ 3963 REG_UDC_EP6InfR &= ~UDC_EPInfR_IFN_MASK; \ 3964 REG_UDC_EP6InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ 3965 REG_UDC_EP6InfR &= ~UDC_EPInfR_CGN_MASK; \ 3966 REG_UDC_EP6InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ 3967 REG_UDC_EP6InfR &= ~UDC_EPInfR_EPT_MASK; \ 3968 REG_UDC_EP6InfR |= UDC_EPInfR_EPT_BULK; \ 3969 REG_UDC_EP6InfR &= ~UDC_EPInfR_EPD; \ 3970 REG_UDC_EP6InfR |= UDC_EPInfR_EPD_OUT; \ 3971 REG_UDC_EP6InfR &= ~UDC_EPInfR_EPN_MASK; \ 3972 REG_UDC_EP6InfR |= (6 << UDC_EPInfR_EPN_BIT); \ 3973 } while (0) 3974 3975 #define __udc_ep7info_init(c,i,a,p) \ 3976 do { \ 3977 REG_UDC_EP7InfR &= ~UDC_EPInfR_MPS_MASK; \ 3978 REG_UDC_EP7InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ 3979 REG_UDC_EP7InfR &= ~UDC_EPInfR_ALTS_MASK; \ 3980 REG_UDC_EP7InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ 3981 REG_UDC_EP7InfR &= ~UDC_EPInfR_IFN_MASK; \ 3982 REG_UDC_EP7InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ 3983 REG_UDC_EP7InfR &= ~UDC_EPInfR_CGN_MASK; \ 3984 REG_UDC_EP7InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ 3985 REG_UDC_EP7InfR &= ~UDC_EPInfR_EPT_MASK; \ 3986 REG_UDC_EP7InfR |= UDC_EPInfR_EPT_ISO; \ 3987 REG_UDC_EP7InfR &= ~UDC_EPInfR_EPD; \ 3988 REG_UDC_EP7InfR |= UDC_EPInfR_EPD_OUT; \ 3989 REG_UDC_EP7InfR &= ~UDC_EPInfR_EPN_MASK; \ 3990 REG_UDC_EP7InfR |= (7 << UDC_EPInfR_EPN_BIT); \ 3991 } while (0) 3992 3993 3994 /*************************************************************************** 3995 * DMAC 3996 ***************************************************************************/ 3997 3998 /* n is the DMA channel (0 - 7) */ 3999 4000 #define __dmac_enable_all_channels() \ 4001 ( REG_DMAC_DMACR |= DMAC_DMACR_DME | DMAC_DMACR_PR_ROUNDROBIN ) 4002 #define __dmac_disable_all_channels() \ 4003 ( REG_DMAC_DMACR &= ~DMAC_DMACR_DME ) 4004 4005 /* p=0,1,2,3 */ 4006 #define __dmac_set_priority(p) \ 4007 do { \ 4008 REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ 4009 REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ 4010 } while (0) 4011 4012 #define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HTR ) 4013 #define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AER ) 4014 4015 #define __dmac_enable_channel(n) \ 4016 ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_CHDE ) 4017 #define __dmac_disable_channel(n) \ 4018 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_CHDE ) 4019 #define __dmac_channel_enabled(n) \ 4020 ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_CHDE ) 4021 4022 #define __dmac_channel_enable_irq(n) \ 4023 ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_TCIE ) 4024 #define __dmac_channel_disable_irq(n) \ 4025 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TCIE ) 4026 4027 #define __dmac_channel_transmit_halt_detected(n) \ 4028 ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_HLT ) 4029 #define __dmac_channel_transmit_end_detected(n) \ 4030 ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_TC ) 4031 #define __dmac_channel_address_error_detected(n) \ 4032 ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_AR ) 4033 4034 #define __dmac_channel_clear_transmit_halt(n) \ 4035 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) 4036 #define __dmac_channel_clear_transmit_end(n) \ 4037 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TC ) 4038 #define __dmac_channel_clear_address_error(n) \ 4039 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) 4040 4041 #define __dmac_channel_set_single_mode(n) \ 4042 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TM ) 4043 #define __dmac_channel_set_block_mode(n) \ 4044 ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_TM ) 4045 4046 #define __dmac_channel_set_transfer_unit_32bit(n) \ 4047 do { \ 4048 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ 4049 REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_32b; \ 4050 } while (0) 4051 4052 #define __dmac_channel_set_transfer_unit_16bit(n) \ 4053 do { \ 4054 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ 4055 REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_16b; \ 4056 } while (0) 4057 4058 #define __dmac_channel_set_transfer_unit_8bit(n) \ 4059 do { \ 4060 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ 4061 REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_8b; \ 4062 } while (0) 4063 4064 #define __dmac_channel_set_transfer_unit_16byte(n) \ 4065 do { \ 4066 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ 4067 REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_16B; \ 4068 } while (0) 4069 4070 #define __dmac_channel_set_transfer_unit_32byte(n) \ 4071 do { \ 4072 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ 4073 REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_32B; \ 4074 } while (0) 4075 4076 /* w=8,16,32 */ 4077 #define __dmac_channel_set_dest_port_width(n,w) \ 4078 do { \ 4079 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DWDH_MASK; \ 4080 REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DWDH_##w; \ 4081 } while (0) 4082 4083 /* w=8,16,32 */ 4084 #define __dmac_channel_set_src_port_width(n,w) \ 4085 do { \ 4086 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SWDH_MASK; \ 4087 REG_DMAC_DCCSR(n) |= DMAC_DCCSR_SWDH_##w; \ 4088 } while (0) 4089 4090 /* v=0-15 */ 4091 #define __dmac_channel_set_rdil(n,v) \ 4092 do { \ 4093 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_RDIL_MASK; \ 4094 REG_DMAC_DCCSR(n) |= ((v) << DMAC_DCCSR_RDIL_BIT); \ 4095 } while (0) 4096 4097 #define __dmac_channel_dest_addr_fixed(n) \ 4098 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DAM ) 4099 #define __dmac_channel_dest_addr_increment(n) \ 4100 ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DAM ) 4101 4102 #define __dmac_channel_src_addr_fixed(n) \ 4103 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SAM ) 4104 #define __dmac_channel_src_addr_increment(n) \ 4105 ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_SAM ) 4106 4107 #define __dmac_channel_set_eop_high(n) \ 4108 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EOPM ) 4109 #define __dmac_channel_set_eop_low(n) \ 4110 ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EOPM ) 4111 4112 #define __dmac_channel_set_erdm(n,m) \ 4113 do { \ 4114 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SWDH_MASK; \ 4115 REG_DMAC_DCCSR(n) |= ((m) << DMAC_DCCSR_ERDM_BIT); \ 4116 } while (0) 4117 4118 #define __dmac_channel_set_eackm(n) \ 4119 ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EACKM ) 4120 #define __dmac_channel_clear_eackm(n) \ 4121 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKM ) 4122 4123 #define __dmac_channel_set_eacks(n) \ 4124 ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EACKS ) 4125 #define __dmac_channel_clear_eacks(n) \ 4126 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKS ) 4127 4128 4129 #define __dmac_channel_irq_detected(n) \ 4130 ( REG_DMAC_DCCSR(n) & (DMAC_DCCSR_TC | DMAC_DCCSR_AR) ) 4131 4132 static __inline__ int __dmac_get_irq(void) 4133 { 4134 int i; 4135 for (i=0;i<NUM_DMA;i++) 4136 if (__dmac_channel_irq_detected(i)) 4137 return i; 4138 return -1; 4139 } 4140 4141 /*************************************************************************** 4142 * AIC (AC'97 & I2S Controller) 4143 ***************************************************************************/ 4144 4145 #define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) 4146 #define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) 4147 #define __aic_reset() ( REG_AIC_FR |= AIC_FR_RST ) 4148 #define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) 4149 #define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) 4150 4151 #define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) 4152 #define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) 4153 4154 #define __aic_set_transmit_trigger(n) \ 4155 do { \ 4156 REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ 4157 REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \ 4158 } while(0) 4159 4160 #define __aic_set_receive_trigger(n) \ 4161 do { \ 4162 REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ 4163 REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \ 4164 } while(0) 4165 4166 #define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) 4167 #define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) 4168 #define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) 4169 #define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) 4170 #define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) 4171 #define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) 4172 4173 #define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH ) 4174 #define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH ) 4175 4176 #define __aic_enable_transmit_intr() \ 4177 ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) 4178 #define __aic_disable_transmit_intr() \ 4179 ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) 4180 #define __aic_enable_receive_intr() \ 4181 ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) 4182 #define __aic_disable_receive_intr() \ 4183 ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) 4184 4185 #define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) 4186 #define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) 4187 #define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) 4188 #define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) 4189 4190 #define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3 4191 #define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4 4192 #define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6 4193 #define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7 4194 #define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8 4195 #define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9 4196 4197 #define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3 4198 #define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4 4199 #define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6 4200 #define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7 4201 #define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8 4202 #define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9 4203 4204 #define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) 4205 #define __ac97_set_xs_mono() \ 4206 do { \ 4207 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ 4208 REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ 4209 } while(0) 4210 #define __ac97_set_xs_stereo() \ 4211 do { \ 4212 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ 4213 REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ 4214 } while(0) 4215 4216 /* In fact, only stereo is support now. */ 4217 #define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) 4218 #define __ac97_set_rs_mono() \ 4219 do { \ 4220 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ 4221 REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ 4222 } while(0) 4223 #define __ac97_set_rs_stereo() \ 4224 do { \ 4225 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ 4226 REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ 4227 } while(0) 4228 4229 #define __ac97_warm_reset_codec() \ 4230 do { \ 4231 REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ 4232 REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ 4233 udelay(1); \ 4234 REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ 4235 REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ 4236 } while (0) 4237 4238 //#define Jz_AC97_RESET_BUG 1 4239 #ifndef Jz_AC97_RESET_BUG 4240 #define __ac97_cold_reset_codec() \ 4241 do { \ 4242 REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ 4243 REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ 4244 REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ 4245 udelay(1); \ 4246 REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ 4247 REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ 4248 } while (0) 4249 #else 4250 #define __ac97_cold_reset_codec() \ 4251 do { \ 4252 __gpio_as_output(111); /* SDATA_OUT */ \ 4253 __gpio_as_output(110); /* SDATA_IN */ \ 4254 __gpio_as_output(112); /* SYNC */ \ 4255 __gpio_as_output(114); /* RESET# */ \ 4256 __gpio_clear_pin(111); \ 4257 __gpio_clear_pin(110); \ 4258 __gpio_clear_pin(112); \ 4259 __gpio_clear_pin(114); \ 4260 udelay(2); \ 4261 __gpio_set_pin(114); \ 4262 udelay(1); \ 4263 __gpio_as_ac97(); \ 4264 } while (0) 4265 #endif 4266 4267 /* n=8,16,18,20 */ 4268 #define __ac97_set_iass(n) \ 4269 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) 4270 #define __ac97_set_oass(n) \ 4271 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) 4272 4273 #define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) 4274 #define __i2s_select_left_justified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) 4275 4276 /* n=8,16,18,20,24 */ 4277 #define __i2s_set_sample_size(n) \ 4278 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT ) 4279 4280 #define __i2s_stop_clock() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) 4281 #define __i2s_start_clock() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) 4282 4283 #define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) 4284 #define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) 4285 #define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) 4286 #define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) 4287 4288 #define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) 4289 4290 #define __aic_get_transmit_resident() \ 4291 ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT ) 4292 #define __aic_get_receive_count() \ 4293 ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) 4294 4295 #define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) 4296 #define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) 4297 #define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) 4298 #define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) 4299 #define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) 4300 4301 #define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) 4302 4303 #define CODEC_READ_CMD (1 << 19) 4304 #define CODEC_WRITE_CMD (0 << 19) 4305 #define CODEC_REG_INDEX_BIT 12 4306 #define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */ 4307 #define CODEC_REG_DATA_BIT 4 4308 #define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */ 4309 4310 #define __ac97_out_rcmd_addr(reg) \ 4311 do { \ 4312 REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ 4313 } while (0) 4314 4315 #define __ac97_out_wcmd_addr(reg) \ 4316 do { \ 4317 REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ 4318 } while (0) 4319 4320 #define __ac97_out_data(value) \ 4321 do { \ 4322 REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \ 4323 } while (0) 4324 4325 #define __ac97_in_data() \ 4326 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) 4327 4328 #define __ac97_in_status_addr() \ 4329 ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) 4330 4331 #define __i2s_set_sample_rate(i2sclk, sync) \ 4332 ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) 4333 4334 #define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) 4335 #define __aic_read_rfifo() ( REG_AIC_DR ) 4336 4337 // 4338 // Define next ops for AC97 compatible 4339 // 4340 4341 #define AC97_ACSR AIC_ACSR 4342 4343 #define __ac97_enable() __aic_enable(); __aic_select_ac97() 4344 #define __ac97_disable() __aic_disable() 4345 #define __ac97_reset() __aic_reset() 4346 4347 #define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) 4348 #define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) 4349 4350 #define __ac97_enable_record() __aic_enable_record() 4351 #define __ac97_disable_record() __aic_disable_record() 4352 #define __ac97_enable_replay() __aic_enable_replay() 4353 #define __ac97_disable_replay() __aic_disable_replay() 4354 #define __ac97_enable_loopback() __aic_enable_loopback() 4355 #define __ac97_disable_loopback() __aic_disable_loopback() 4356 4357 #define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() 4358 #define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() 4359 #define __ac97_enable_receive_dma() __aic_enable_receive_dma() 4360 #define __ac97_disable_receive_dma() __aic_disable_receive_dma() 4361 4362 #define __ac97_transmit_request() __aic_transmit_request() 4363 #define __ac97_receive_request() __aic_receive_request() 4364 #define __ac97_transmit_underrun() __aic_transmit_underrun() 4365 #define __ac97_receive_overrun() __aic_receive_overrun() 4366 4367 #define __ac97_clear_errors() __aic_clear_errors() 4368 4369 #define __ac97_get_transmit_resident() __aic_get_transmit_resident() 4370 #define __ac97_get_receive_count() __aic_get_receive_count() 4371 4372 #define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() 4373 #define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() 4374 #define __ac97_enable_receive_intr() __aic_enable_receive_intr() 4375 #define __ac97_disable_receive_intr() __aic_disable_receive_intr() 4376 4377 #define __ac97_write_tfifo(v) __aic_write_tfifo(v) 4378 #define __ac97_read_rfifo() __aic_read_rfifo() 4379 4380 // 4381 // Define next ops for I2S compatible 4382 // 4383 4384 #define I2S_ACSR AIC_I2SSR 4385 4386 #define __i2s_enable() __aic_enable(); __aic_select_i2s() 4387 #define __i2s_disable() __aic_disable() 4388 #define __i2s_reset() __aic_reset() 4389 4390 #define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) 4391 #define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) 4392 4393 #define __i2s_enable_record() __aic_enable_record() 4394 #define __i2s_disable_record() __aic_disable_record() 4395 #define __i2s_enable_replay() __aic_enable_replay() 4396 #define __i2s_disable_replay() __aic_disable_replay() 4397 #define __i2s_enable_loopback() __aic_enable_loopback() 4398 #define __i2s_disable_loopback() __aic_disable_loopback() 4399 4400 #define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() 4401 #define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() 4402 #define __i2s_enable_receive_dma() __aic_enable_receive_dma() 4403 #define __i2s_disable_receive_dma() __aic_disable_receive_dma() 4404 4405 #define __i2s_transmit_request() __aic_transmit_request() 4406 #define __i2s_receive_request() __aic_receive_request() 4407 #define __i2s_transmit_underrun() __aic_transmit_underrun() 4408 #define __i2s_receive_overrun() __aic_receive_overrun() 4409 4410 #define __i2s_clear_errors() __aic_clear_errors() 4411 4412 #define __i2s_get_transmit_resident() __aic_get_transmit_resident() 4413 #define __i2s_get_receive_count() __aic_get_receive_count() 4414 4415 #define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() 4416 #define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() 4417 #define __i2s_enable_receive_intr() __aic_enable_receive_intr() 4418 #define __i2s_disable_receive_intr() __aic_disable_receive_intr() 4419 4420 #define __i2s_write_tfifo(v) __aic_write_tfifo(v) 4421 #define __i2s_read_rfifo() __aic_read_rfifo() 4422 4423 #define __i2s_reset_codec() \ 4424 do { \ 4425 __gpio_as_output(111); /* SDATA_OUT */ \ 4426 __gpio_as_input(110); /* SDATA_IN */ \ 4427 __gpio_as_output(112); /* SYNC */ \ 4428 __gpio_as_output(114); /* RESET# */ \ 4429 __gpio_clear_pin(111); \ 4430 __gpio_clear_pin(110); \ 4431 __gpio_clear_pin(112); \ 4432 __gpio_clear_pin(114); \ 4433 __gpio_as_i2s_master(); \ 4434 } while (0) 4435 4436 4437 /*************************************************************************** 4438 * LCD 4439 ***************************************************************************/ 4440 4441 /* Register operations using absolute positioning have been removed. */ 4442 4443 /*************************************************************************** 4444 * DES 4445 ***************************************************************************/ 4446 4447 4448 /*************************************************************************** 4449 * CPM 4450 ***************************************************************************/ 4451 4452 /* Register operations using absolute positioning have been removed. */ 4453 4454 /*************************************************************************** 4455 * SSI 4456 ***************************************************************************/ 4457 4458 #define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE ) 4459 #define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE ) 4460 #define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL ) 4461 4462 #define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) 4463 4464 #define __ssi_select_ce2() \ 4465 do { \ 4466 REG_SSI_CR0 |= SSI_CR0_FSEL; \ 4467 REG_SSI_CR1 &= ~SSI_CR1_MULTS; \ 4468 } while (0) 4469 4470 #define __ssi_select_gpc() \ 4471 do { \ 4472 REG_SSI_CR0 &= ~SSI_CR0_FSEL; \ 4473 REG_SSI_CR1 |= SSI_CR1_MULTS; \ 4474 } while (0) 4475 4476 #define __ssi_enable_tx_intr() \ 4477 ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) 4478 4479 #define __ssi_disable_tx_intr() \ 4480 ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) 4481 4482 #define __ssi_enable_rx_intr() \ 4483 ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) 4484 4485 #define __ssi_disable_rx_intr() \ 4486 ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) 4487 4488 #define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP ) 4489 #define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP ) 4490 4491 #define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV ) 4492 #define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV ) 4493 4494 #define __ssi_finish_receive() \ 4495 ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) 4496 4497 #define __ssi_disable_recvfinish() \ 4498 ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) 4499 4500 #define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH ) 4501 #define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH ) 4502 4503 #define __ssi_flush_fifo() \ 4504 ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) 4505 4506 #define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN ) 4507 4508 /* Motorola's SPI format, set 1 delay */ 4509 #define __ssi_spi_format() \ 4510 do { \ 4511 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ 4512 REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \ 4513 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ 4514 REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ 4515 } while (0) 4516 4517 /* TI's SSP format, must clear SSI_CR1.UNFIN */ 4518 #define __ssi_ssp_format() \ 4519 do { \ 4520 REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ 4521 REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \ 4522 } while (0) 4523 4524 /* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ 4525 #define __ssi_microwire_format() \ 4526 do { \ 4527 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ 4528 REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \ 4529 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ 4530 REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ 4531 REG_SSI_CR0 &= ~SSI_CR0_RFINE; \ 4532 } while (0) 4533 4534 /* CE# level (FRMHL), CE# in interval time (ITFRM), 4535 clock phase and polarity (PHA POL), 4536 interval time (SSIITR), interval characters/frame (SSIICR) */ 4537 4538 /* frmhl,endian,mcom,flen,pha,pol MASK */ 4539 #define SSICR1_MISC_MASK \ 4540 ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ 4541 | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \ 4542 4543 #define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \ 4544 do { \ 4545 REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \ 4546 REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \ 4547 (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ 4548 ((pha) << 1) | (pol); \ 4549 } while(0) 4550 4551 /* Transfer with MSB or LSB first */ 4552 #define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST ) 4553 #define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST ) 4554 4555 /* n = 2 - 17 */ 4556 #define __ssi_set_frame_length(n) \ 4557 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | SSI_CR1_FLEN_##n##BIT) ) 4558 4559 /* n = 1 - 16 */ 4560 #define __ssi_set_microwire_command_length(n) \ 4561 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) 4562 4563 /* Set the clock phase for SPI */ 4564 #define __ssi_set_spi_clock_phase(n) \ 4565 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) ) 4566 4567 /* Set the clock polarity for SPI */ 4568 #define __ssi_set_spi_clock_polarity(n) \ 4569 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) 4570 4571 /* n = 1,4,8,14 */ 4572 #define __ssi_set_tx_trigger(n) \ 4573 do { \ 4574 REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \ 4575 REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \ 4576 } while (0) 4577 4578 /* n = 1,4,8,14 */ 4579 #define __ssi_set_rx_trigger(n) \ 4580 do { \ 4581 REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \ 4582 REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \ 4583 } while (0) 4584 4585 #define __ssi_get_txfifo_count() \ 4586 ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) 4587 4588 #define __ssi_get_rxfifo_count() \ 4589 ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) 4590 4591 #define __ssi_clear_errors() \ 4592 ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) 4593 4594 #define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END ) 4595 #define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY ) 4596 4597 #define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF ) 4598 #define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE ) 4599 #define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF ) 4600 4601 #define __ssi_set_clk(dev_clk, ssi_clk) \ 4602 ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) 4603 4604 #define __ssi_receive_data() REG_SSI_DR 4605 #define __ssi_transmit_data(v) ( REG_SSI_DR = (v) ) 4606 4607 /*************************************************************************** 4608 * WDT 4609 ***************************************************************************/ 4610 4611 #define __wdt_set_count(count) ( REG_WDT_WTCNT = (count) ) 4612 #define __wdt_start() ( REG_WDT_WTCSR |= WDT_WTCSR_START ) 4613 #define __wdt_stop() ( REG_WDT_WTCSR &= ~WDT_WTCSR_START ) 4614 4615 #endif /* !__ASSEMBLY__ */ 4616 4617 #endif /* __JZ4730_H__ */