1 /* 2 * JzRISC lcd controller 3 * 4 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> 5 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include "jz4740_lcd.h" 24 #include "sdram.h" 25 #include "jzlcd.h" 26 #include "board.h" 27 28 #define align2(n) (n)=((((n)+1)>>1)<<1) 29 #define align4(n) (n)=((((n)+3)>>2)<<2) 30 #define align8(n) (n)=((((n)+7)>>3)<<3) 31 32 extern struct jzfb_info jzfb; 33 extern vidinfo_t panel_info; 34 35 unsigned long lcd_get_size(void) 36 { 37 int line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; 38 return line_length * panel_info.vl_row; 39 } 40 41 static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid); 42 static void jz_lcd_desc_init(vidinfo_t *vid); 43 static int jz_lcd_hw_init(vidinfo_t *vid); 44 45 void lcd_ctrl_init (void *lcdbase) 46 { 47 jz_lcd_init_mem(lcdbase, &panel_info); 48 jz_lcd_desc_init(&panel_info); 49 jz_lcd_hw_init(&panel_info); 50 } 51 52 /* 53 * Before enabled lcd controller, lcd registers should be configured correctly. 54 */ 55 void lcd_enable (void) 56 { 57 REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ 58 REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ 59 } 60 61 void lcd_disable (void) 62 { 63 REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ 64 /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */ 65 } 66 67 static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid) 68 { 69 unsigned long palette_mem_size; 70 struct jz_fb_info *fbi = &vid->jz_fb; 71 int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; 72 73 fbi->screen = (unsigned long)lcdbase; 74 fbi->palette_size = 256; 75 palette_mem_size = fbi->palette_size * sizeof(u16); 76 77 /* debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (unsigned long) palette_mem_size); */ 78 /* locate palette and descs at end of page following fb */ 79 fbi->palette = (unsigned long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; 80 81 return 0; 82 } 83 84 static void jz_lcd_desc_init(vidinfo_t *vid) 85 { 86 struct jz_fb_info * fbi; 87 fbi = &vid->jz_fb; 88 fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); 89 fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); 90 fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); 91 92 #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8) 93 94 /* populate descriptors */ 95 fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow); 96 fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL)); 97 fbi->dmadesc_fblow->fidr = 0; 98 fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ; 99 100 fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */ 101 102 fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); 103 fbi->dmadesc_fbhigh->fidr = 0; 104 fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */ 105 106 fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette); 107 fbi->dmadesc_palette->fidr = 0; 108 fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); 109 110 if(NBITS(vid->vl_bpix) < 12) 111 { 112 /* assume any mode with <12 bpp is palette driven */ 113 fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh); 114 fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette); 115 /* flips back and forth between pal and fbhigh */ 116 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette); 117 } else { 118 /* palette shouldn't be loaded in true-color mode */ 119 fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh); 120 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */ 121 } 122 123 flush_cache_all(); 124 } 125 126 static int jz_lcd_hw_init(vidinfo_t *vid) 127 { 128 struct jz_fb_info *fbi = &vid->jz_fb; 129 unsigned int val = 0; 130 unsigned int pclk; 131 unsigned int stnH; 132 int pll_div; 133 134 /* Setting Control register */ 135 switch (jzfb.bpp) { 136 case 1: 137 val |= LCD_CTRL_BPP_1; 138 break; 139 case 2: 140 val |= LCD_CTRL_BPP_2; 141 break; 142 case 4: 143 val |= LCD_CTRL_BPP_4; 144 break; 145 case 8: 146 val |= LCD_CTRL_BPP_8; 147 break; 148 case 15: 149 val |= LCD_CTRL_RGB555; 150 case 16: 151 val |= LCD_CTRL_BPP_16; 152 break; 153 case 17 ... 32: 154 val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ 155 break; 156 157 default: 158 /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */ 159 val |= LCD_CTRL_BPP_16; 160 break; 161 } 162 163 switch (jzfb.cfg & MODE_MASK) { 164 case MODE_STN_MONO_DUAL: 165 case MODE_STN_COLOR_DUAL: 166 case MODE_STN_MONO_SINGLE: 167 case MODE_STN_COLOR_SINGLE: 168 switch (jzfb.bpp) { 169 case 1: 170 /* val |= LCD_CTRL_PEDN; */ 171 case 2: 172 val |= LCD_CTRL_FRC_2; 173 break; 174 case 4: 175 val |= LCD_CTRL_FRC_4; 176 break; 177 case 8: 178 default: 179 val |= LCD_CTRL_FRC_16; 180 break; 181 } 182 break; 183 } 184 185 val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ 186 val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ 187 188 switch (jzfb.cfg & MODE_MASK) { 189 case MODE_STN_MONO_DUAL: 190 case MODE_STN_COLOR_DUAL: 191 case MODE_STN_MONO_SINGLE: 192 case MODE_STN_COLOR_SINGLE: 193 switch (jzfb.cfg & STN_DAT_PINMASK) { 194 case STN_DAT_PIN1: 195 /* Do not adjust the hori-param value. */ 196 break; 197 case STN_DAT_PIN2: 198 align2(jzfb.hsw); 199 align2(jzfb.elw); 200 align2(jzfb.blw); 201 break; 202 case STN_DAT_PIN4: 203 align4(jzfb.hsw); 204 align4(jzfb.elw); 205 align4(jzfb.blw); 206 break; 207 case STN_DAT_PIN8: 208 align8(jzfb.hsw); 209 align8(jzfb.elw); 210 align8(jzfb.blw); 211 break; 212 } 213 break; 214 } 215 216 REG_LCD_CTRL = val; 217 218 switch (jzfb.cfg & MODE_MASK) { 219 case MODE_STN_MONO_DUAL: 220 case MODE_STN_COLOR_DUAL: 221 case MODE_STN_MONO_SINGLE: 222 case MODE_STN_COLOR_SINGLE: 223 if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || 224 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 225 stnH = jzfb.h >> 1; 226 else 227 stnH = jzfb.h; 228 229 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 230 REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); 231 232 /* Screen setting */ 233 REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); 234 REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); 235 REG_LCD_DAV = (0 << 16) | (stnH); 236 237 /* AC BIAs signal */ 238 REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); 239 240 break; 241 242 case MODE_TFT_GEN: 243 case MODE_TFT_SHARP: 244 case MODE_TFT_CASIO: 245 case MODE_TFT_SAMSUNG: 246 case MODE_8BIT_SERIAL_TFT: 247 case MODE_TFT_18BIT: 248 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 249 REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; 250 REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); 251 REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); 252 REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ 253 | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); 254 break; 255 } 256 257 switch (jzfb.cfg & MODE_MASK) { 258 case MODE_TFT_SAMSUNG: 259 { 260 unsigned int total, tp_s, tp_e, ckv_s, ckv_e; 261 unsigned int rev_s, rev_e, inv_s, inv_e; 262 263 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 264 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 265 266 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 267 tp_s = jzfb.blw + jzfb.w + 1; 268 tp_e = tp_s + 1; 269 /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ 270 ckv_s = tp_s - pclk/(1000000000/4100); 271 ckv_e = tp_s + total; 272 rev_s = tp_s - 11; /* -11.5 clk */ 273 rev_e = rev_s + total; 274 inv_s = tp_s; 275 inv_e = inv_s + total; 276 REG_LCD_CLS = (tp_s << 16) | tp_e; 277 REG_LCD_PS = (ckv_s << 16) | ckv_e; 278 REG_LCD_SPL = (rev_s << 16) | rev_e; 279 REG_LCD_REV = (inv_s << 16) | inv_e; 280 jzfb.cfg |= STFT_REVHI | STFT_SPLHI; 281 break; 282 } 283 case MODE_TFT_SHARP: 284 { 285 unsigned int total, cls_s, cls_e, ps_s, ps_e; 286 unsigned int spl_s, spl_e, rev_s, rev_e; 287 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 288 spl_s = 1; 289 spl_e = spl_s + 1; 290 cls_s = 0; 291 cls_e = total - 60; /* > 4us (pclk = 80ns) */ 292 ps_s = cls_s; 293 ps_e = cls_e; 294 rev_s = total - 40; /* > 3us (pclk = 80ns) */ 295 rev_e = rev_s + total; 296 jzfb.cfg |= STFT_PSHI; 297 REG_LCD_SPL = (spl_s << 16) | spl_e; 298 REG_LCD_CLS = (cls_s << 16) | cls_e; 299 REG_LCD_PS = (ps_s << 16) | ps_e; 300 REG_LCD_REV = (rev_s << 16) | rev_e; 301 break; 302 } 303 case MODE_TFT_CASIO: 304 break; 305 } 306 307 /* Configure the LCD panel */ 308 REG_LCD_CFG = jzfb.cfg; 309 310 /* Timing setting */ 311 __cpm_stop_lcd(); 312 313 val = jzfb.fclk; /* frame clk */ 314 if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { 315 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 316 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 317 } else { 318 /* serial mode: Hsync period = 3*Width_Pixel */ 319 pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * 320 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 321 } 322 323 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 324 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 325 pclk = (pclk * 3); 326 327 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 328 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 329 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || 330 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 331 pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); 332 333 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 334 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 335 pclk >>= 1; 336 337 #ifdef CONFIG_CPU_JZ4730 338 val = __cpm_get_pllout() / pclk; 339 REG_CPM_CFCR2 = val - 1; 340 val = pclk * 4 ; 341 if ( val > 150000000 ) { 342 val = 150000000; 343 } 344 val = __cpm_get_pllout() / val; 345 val--; 346 if ( val > 0xF ) 347 val = 0xF; 348 __cpm_set_lcdclk_div(val); 349 REG_CPM_CFCR |= CPM_CFCR_UPE; 350 #else 351 pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ 352 pll_div = pll_div ? 1 : 2 ; 353 val = ( __cpm_get_pllout()/pll_div ) / pclk; 354 val--; 355 if ( val > 0x1ff ) { 356 val = 0x1ff; 357 } 358 __cpm_set_pixdiv(val); 359 360 val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ 361 if ( val > 150000000 ) { 362 val = 150000000; 363 } 364 val = ( __cpm_get_pllout()/pll_div ) / val; 365 val--; 366 if ( val > 0x1f ) { 367 val = 0x1f; 368 } 369 __cpm_set_ldiv( val ); 370 REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ 371 #endif 372 __cpm_start_lcd(); 373 udelay(1000); 374 375 REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/ 376 377 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 378 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 379 REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/ 380 381 return 0; 382 } 383 384 void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue) 385 { 386 } 387 388 void lcd_initcolregs (void) 389 { 390 }