1 /* 2 * Include file for Ingenic Semiconductor's JZ4740 CPU. 3 * 4 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc. 5 * Copyright (C) 2009 Qi Hardware Inc. 6 * Author: Xiangfu Liu <xiangfu@sharism.cc> 7 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 22 * Boston, MA 02110-1301, USA 23 */ 24 #ifndef __JZ4740_H__ 25 #define __JZ4740_H__ 26 27 #include "xburst_types.h" 28 29 /* NOTE: Independent of usbboot parameters. */ 30 31 #define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ 32 #define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */ 33 #define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */ 34 35 /* Boot ROM Specification */ 36 /* NOR Boot config */ 37 #define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */ 38 #define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ 39 #define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ 40 41 /* NAND Boot config */ 42 #define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */ 43 #define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ 44 #define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ 45 #define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */ 46 47 48 /* Register Definitions */ 49 #define CPM_BASE 0xB0000000 50 #define INTC_BASE 0xB0001000 51 #define TCU_BASE 0xB0002000 52 #define WDT_BASE 0xB0002000 53 #define RTC_BASE 0xB0003000 54 #define GPIO_BASE 0xB0010000 55 #define AIC_BASE 0xB0020000 56 #define ICDC_BASE 0xB0020000 57 #define MSC_BASE 0xB0021000 58 #define UART0_BASE 0xB0030000 59 #define I2C_BASE 0xB0042000 60 #define SSI_BASE 0xB0043000 61 #define SADC_BASE 0xB0070000 62 #define EMC_BASE 0xB3010000 63 #define DMAC_BASE 0xB3020000 64 #define UHC_BASE 0xB3030000 65 #define UDC_BASE 0xB3040000 66 #define LCD_BASE 0xB3050000 67 #define SLCD_BASE 0xB3050000 68 #define CIM_BASE 0xB3060000 69 #define ETH_BASE 0xB3100000 70 71 72 /* 73 * INTC (Interrupt Controller) 74 */ 75 #define INTC_ISR (INTC_BASE + 0x00) 76 #define INTC_IMR (INTC_BASE + 0x04) 77 #define INTC_IMSR (INTC_BASE + 0x08) 78 #define INTC_IMCR (INTC_BASE + 0x0c) 79 #define INTC_IPR (INTC_BASE + 0x10) 80 81 #define REG_INTC_ISR REG32(INTC_ISR) 82 #define REG_INTC_IMR REG32(INTC_IMR) 83 #define REG_INTC_IMSR REG32(INTC_IMSR) 84 #define REG_INTC_IMCR REG32(INTC_IMCR) 85 #define REG_INTC_IPR REG32(INTC_IPR) 86 87 /* 1st-level interrupts */ 88 #define IRQ_I2C 1 89 #define IRQ_UHC 3 90 #define IRQ_UART0 9 91 #define IRQ_SADC 12 92 #define IRQ_MSC 14 93 #define IRQ_RTC 15 94 #define IRQ_SSI 16 95 #define IRQ_CIM 17 96 #define IRQ_AIC 18 97 #define IRQ_ETH 19 98 #define IRQ_DMAC 20 99 #define IRQ_TCU2 21 100 #define IRQ_TCU1 22 101 #define IRQ_TCU0 23 102 #define IRQ_UDC 24 103 #define IRQ_GPIO3 25 104 #define IRQ_GPIO2 26 105 #define IRQ_GPIO1 27 106 #define IRQ_GPIO0 28 107 #define IRQ_IPU 29 108 #define IRQ_LCD 30 109 110 /* 2nd-level interrupts */ 111 #define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ 112 #define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ 113 114 115 /* 116 * RTC 117 */ 118 #define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */ 119 #define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */ 120 #define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */ 121 #define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */ 122 123 #define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */ 124 #define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */ 125 #define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */ 126 #define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ 127 #define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ 128 #define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */ 129 130 #define REG_RTC_RCR REG32(RTC_RCR) 131 #define REG_RTC_RSR REG32(RTC_RSR) 132 #define REG_RTC_RSAR REG32(RTC_RSAR) 133 #define REG_RTC_RGR REG32(RTC_RGR) 134 #define REG_RTC_HCR REG32(RTC_HCR) 135 #define REG_RTC_HWFCR REG32(RTC_HWFCR) 136 #define REG_RTC_HRCR REG32(RTC_HRCR) 137 #define REG_RTC_HWCR REG32(RTC_HWCR) 138 #define REG_RTC_HWRSR REG32(RTC_HWRSR) 139 #define REG_RTC_HSPR REG32(RTC_HSPR) 140 141 /* RTC Control Register */ 142 #define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ 143 #define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */ 144 #define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */ 145 #define RTC_RCR_AF (1 << 4) /* Alarm Flag */ 146 #define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */ 147 #define RTC_RCR_AE (1 << 2) /* Alarm Enable */ 148 #define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ 149 150 /* RTC Regulator Register */ 151 #define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ 152 #define RTC_RGR_ADJC_BIT 16 153 #define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) 154 #define RTC_RGR_NC1HZ_BIT 0 155 #define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) 156 157 /* Hibernate Control Register */ 158 #define RTC_HCR_PD (1 << 0) /* Power Down */ 159 160 /* Hibernate Wakeup Filter Counter Register */ 161 #define RTC_HWFCR_BIT 5 162 #define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT) 163 164 /* Hibernate Reset Counter Register */ 165 #define RTC_HRCR_BIT 5 166 #define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) 167 168 /* Hibernate Wakeup Control Register */ 169 #define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */ 170 171 /* Hibernate Wakeup Status Register */ 172 #define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */ 173 #define RTC_HWRSR_PPR (1 << 4) /* PPR reset */ 174 #define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */ 175 #define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */ 176 177 /************************************************************************* 178 * CPM (Clock reset and Power control Management) 179 *************************************************************************/ 180 #define CPM_CPCCR (CPM_BASE+0x00) 181 #define CPM_CPPCR (CPM_BASE+0x10) 182 #define CPM_I2SCDR (CPM_BASE+0x60) 183 #define CPM_LPCDR (CPM_BASE+0x64) 184 #define CPM_MSCCDR (CPM_BASE+0x68) 185 #define CPM_UHCCDR (CPM_BASE+0x6C) 186 187 #define CPM_LCR (CPM_BASE+0x04) 188 #define CPM_CLKGR (CPM_BASE+0x20) 189 #define CPM_SCR (CPM_BASE+0x24) 190 191 #define CPM_HCR (CPM_BASE+0x30) 192 #define CPM_HWFCR (CPM_BASE+0x34) 193 #define CPM_HRCR (CPM_BASE+0x38) 194 #define CPM_HWCR (CPM_BASE+0x3c) 195 #define CPM_HWSR (CPM_BASE+0x40) 196 #define CPM_HSPR (CPM_BASE+0x44) 197 198 #define CPM_RSR (CPM_BASE+0x08) 199 200 201 #define REG_CPM_CPCCR REG32(CPM_CPCCR) 202 #define REG_CPM_CPPCR REG32(CPM_CPPCR) 203 #define REG_CPM_I2SCDR REG32(CPM_I2SCDR) 204 #define REG_CPM_LPCDR REG32(CPM_LPCDR) 205 #define REG_CPM_MSCCDR REG32(CPM_MSCCDR) 206 #define REG_CPM_UHCCDR REG32(CPM_UHCCDR) 207 208 #define REG_CPM_LCR REG32(CPM_LCR) 209 #define REG_CPM_CLKGR REG32(CPM_CLKGR) 210 #define REG_CPM_SCR REG32(CPM_SCR) 211 #define REG_CPM_HCR REG32(CPM_HCR) 212 #define REG_CPM_HWFCR REG32(CPM_HWFCR) 213 #define REG_CPM_HRCR REG32(CPM_HRCR) 214 #define REG_CPM_HWCR REG32(CPM_HWCR) 215 #define REG_CPM_HWSR REG32(CPM_HWSR) 216 #define REG_CPM_HSPR REG32(CPM_HSPR) 217 218 #define REG_CPM_RSR REG32(CPM_RSR) 219 220 221 /* Clock Control Register */ 222 #define CPM_CPCCR_I2CS (1 << 31) 223 #define CPM_CPCCR_CLKOEN (1 << 30) 224 #define CPM_CPCCR_UCS (1 << 29) 225 #define CPM_CPCCR_UDIV_BIT 23 226 #define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT) 227 #define CPM_CPCCR_CE (1 << 22) 228 #define CPM_CPCCR_PCS (1 << 21) 229 #define CPM_CPCCR_LDIV_BIT 16 230 #define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT) 231 #define CPM_CPCCR_MDIV_BIT 12 232 #define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT) 233 #define CPM_CPCCR_PDIV_BIT 8 234 #define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT) 235 #define CPM_CPCCR_HDIV_BIT 4 236 #define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT) 237 #define CPM_CPCCR_CDIV_BIT 0 238 #define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) 239 240 /* I2S Clock Divider Register */ 241 #define CPM_I2SCDR_I2SDIV_BIT 0 242 #define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) 243 244 /* LCD Pixel Clock Divider Register */ 245 #define CPM_LPCDR_PIXDIV_BIT 0 246 #define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT) 247 248 /* MSC Clock Divider Register */ 249 #define CPM_MSCCDR_MSCDIV_BIT 0 250 #define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT) 251 252 /* PLL Control Register */ 253 #define CPM_CPPCR_PLLM_BIT 23 254 #define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT) 255 #define CPM_CPPCR_PLLN_BIT 18 256 #define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT) 257 #define CPM_CPPCR_PLLOD_BIT 16 258 #define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) 259 #define CPM_CPPCR_PLLS (1 << 10) 260 #define CPM_CPPCR_PLLBP (1 << 9) 261 #define CPM_CPPCR_PLLEN (1 << 8) 262 #define CPM_CPPCR_PLLST_BIT 0 263 #define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) 264 265 /* Low Power Control Register */ 266 #define CPM_LCR_DOZE_DUTY_BIT 3 267 #define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) 268 #define CPM_LCR_DOZE_ON (1 << 2) 269 #define CPM_LCR_LPM_BIT 0 270 #define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) 271 #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) 272 #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) 273 274 /* Clock Gate Register */ 275 #define CPM_CLKGR_UART1 (1 << 15) 276 #define CPM_CLKGR_UHC (1 << 14) 277 #define CPM_CLKGR_IPU (1 << 13) 278 #define CPM_CLKGR_DMAC (1 << 12) 279 #define CPM_CLKGR_UDC (1 << 11) 280 #define CPM_CLKGR_LCD (1 << 10) 281 #define CPM_CLKGR_CIM (1 << 9) 282 #define CPM_CLKGR_SADC (1 << 8) 283 #define CPM_CLKGR_MSC (1 << 7) 284 #define CPM_CLKGR_AIC1 (1 << 6) 285 #define CPM_CLKGR_AIC2 (1 << 5) 286 #define CPM_CLKGR_SSI (1 << 4) 287 #define CPM_CLKGR_I2C (1 << 3) 288 #define CPM_CLKGR_RTC (1 << 2) 289 #define CPM_CLKGR_TCU (1 << 1) 290 #define CPM_CLKGR_UART0 (1 << 0) 291 292 /* Sleep Control Register */ 293 #define CPM_SCR_O1ST_BIT 8 294 #define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) 295 #define CPM_SCR_UDCPHY_ENABLE (1 << 6) 296 #define CPM_SCR_USBPHY_DISABLE (1 << 7) 297 #define CPM_SCR_OSC_ENABLE (1 << 4) 298 299 /* Hibernate Control Register */ 300 #define CPM_HCR_PD (1 << 0) 301 302 /* Wakeup Filter Counter Register in Hibernate Mode */ 303 #define CPM_HWFCR_TIME_BIT 0 304 #define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT) 305 306 /* Reset Counter Register in Hibernate Mode */ 307 #define CPM_HRCR_TIME_BIT 0 308 #define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT) 309 310 /* Wakeup Control Register in Hibernate Mode */ 311 #define CPM_HWCR_WLE_LOW (0 << 2) 312 #define CPM_HWCR_WLE_HIGH (1 << 2) 313 #define CPM_HWCR_PIN_WAKEUP (1 << 1) 314 #define CPM_HWCR_RTC_WAKEUP (1 << 0) 315 316 /* Wakeup Status Register in Hibernate Mode */ 317 #define CPM_HWSR_WSR_PIN (1 << 1) 318 #define CPM_HWSR_WSR_RTC (1 << 0) 319 320 /* Reset Status Register */ 321 #define CPM_RSR_HR (1 << 2) 322 #define CPM_RSR_WR (1 << 1) 323 #define CPM_RSR_PR (1 << 0) 324 325 326 /************************************************************************* 327 * TCU (Timer Counter Unit) 328 *************************************************************************/ 329 #define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */ 330 #define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */ 331 #define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */ 332 #define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */ 333 #define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */ 334 #define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */ 335 #define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */ 336 #define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */ 337 #define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */ 338 #define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */ 339 #define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */ 340 #define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */ 341 #define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */ 342 #define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */ 343 #define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */ 344 #define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */ 345 #define TCU_TDFR1 (TCU_BASE + 0x50) 346 #define TCU_TDHR1 (TCU_BASE + 0x54) 347 #define TCU_TCNT1 (TCU_BASE + 0x58) 348 #define TCU_TCSR1 (TCU_BASE + 0x5C) 349 #define TCU_TDFR2 (TCU_BASE + 0x60) 350 #define TCU_TDHR2 (TCU_BASE + 0x64) 351 #define TCU_TCNT2 (TCU_BASE + 0x68) 352 #define TCU_TCSR2 (TCU_BASE + 0x6C) 353 #define TCU_TDFR3 (TCU_BASE + 0x70) 354 #define TCU_TDHR3 (TCU_BASE + 0x74) 355 #define TCU_TCNT3 (TCU_BASE + 0x78) 356 #define TCU_TCSR3 (TCU_BASE + 0x7C) 357 #define TCU_TDFR4 (TCU_BASE + 0x80) 358 #define TCU_TDHR4 (TCU_BASE + 0x84) 359 #define TCU_TCNT4 (TCU_BASE + 0x88) 360 #define TCU_TCSR4 (TCU_BASE + 0x8C) 361 #define TCU_TDFR5 (TCU_BASE + 0x90) 362 #define TCU_TDHR5 (TCU_BASE + 0x94) 363 #define TCU_TCNT5 (TCU_BASE + 0x98) 364 #define TCU_TCSR5 (TCU_BASE + 0x9C) 365 366 #define REG_TCU_TSR REG32(TCU_TSR) 367 #define REG_TCU_TSSR REG32(TCU_TSSR) 368 #define REG_TCU_TSCR REG32(TCU_TSCR) 369 #define REG_TCU_TER REG8(TCU_TER) 370 #define REG_TCU_TESR REG8(TCU_TESR) 371 #define REG_TCU_TECR REG8(TCU_TECR) 372 #define REG_TCU_TFR REG32(TCU_TFR) 373 #define REG_TCU_TFSR REG32(TCU_TFSR) 374 #define REG_TCU_TFCR REG32(TCU_TFCR) 375 #define REG_TCU_TMR REG32(TCU_TMR) 376 #define REG_TCU_TMSR REG32(TCU_TMSR) 377 #define REG_TCU_TMCR REG32(TCU_TMCR) 378 #define REG_TCU_TDFR0 REG16(TCU_TDFR0) 379 #define REG_TCU_TDHR0 REG16(TCU_TDHR0) 380 #define REG_TCU_TCNT0 REG16(TCU_TCNT0) 381 #define REG_TCU_TCSR0 REG16(TCU_TCSR0) 382 #define REG_TCU_TDFR1 REG16(TCU_TDFR1) 383 #define REG_TCU_TDHR1 REG16(TCU_TDHR1) 384 #define REG_TCU_TCNT1 REG16(TCU_TCNT1) 385 #define REG_TCU_TCSR1 REG16(TCU_TCSR1) 386 #define REG_TCU_TDFR2 REG16(TCU_TDFR2) 387 #define REG_TCU_TDHR2 REG16(TCU_TDHR2) 388 #define REG_TCU_TCNT2 REG16(TCU_TCNT2) 389 #define REG_TCU_TCSR2 REG16(TCU_TCSR2) 390 #define REG_TCU_TDFR3 REG16(TCU_TDFR3) 391 #define REG_TCU_TDHR3 REG16(TCU_TDHR3) 392 #define REG_TCU_TCNT3 REG16(TCU_TCNT3) 393 #define REG_TCU_TCSR3 REG16(TCU_TCSR3) 394 #define REG_TCU_TDFR4 REG16(TCU_TDFR4) 395 #define REG_TCU_TDHR4 REG16(TCU_TDHR4) 396 #define REG_TCU_TCNT4 REG16(TCU_TCNT4) 397 #define REG_TCU_TCSR4 REG16(TCU_TCSR4) 398 399 /* n = 0,1,2,3,4,5 */ 400 #define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */ 401 #define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */ 402 #define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */ 403 #define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */ 404 405 #define REG_TCU_TDFR(n) REG16(TCU_TDFR((n))) 406 #define REG_TCU_TDHR(n) REG16(TCU_TDHR((n))) 407 #define REG_TCU_TCNT(n) REG16(TCU_TCNT((n))) 408 #define REG_TCU_TCSR(n) REG16(TCU_TCSR((n))) 409 410 /* Register definitions */ 411 #define TCU_TCSR_PWM_SD (1 << 9) 412 #define TCU_TCSR_PWM_INITL_HIGH (1 << 8) 413 #define TCU_TCSR_PWM_EN (1 << 7) 414 #define TCU_TCSR_PRESCALE_BIT 3 415 #define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) 416 #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) 417 #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) 418 #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) 419 #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) 420 #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) 421 #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) 422 #define TCU_TCSR_EXT_EN (1 << 2) 423 #define TCU_TCSR_RTC_EN (1 << 1) 424 #define TCU_TCSR_PCK_EN (1 << 0) 425 426 #define TCU_TER_TCEN5 (1 << 5) 427 #define TCU_TER_TCEN4 (1 << 4) 428 #define TCU_TER_TCEN3 (1 << 3) 429 #define TCU_TER_TCEN2 (1 << 2) 430 #define TCU_TER_TCEN1 (1 << 1) 431 #define TCU_TER_TCEN0 (1 << 0) 432 433 #define TCU_TESR_TCST5 (1 << 5) 434 #define TCU_TESR_TCST4 (1 << 4) 435 #define TCU_TESR_TCST3 (1 << 3) 436 #define TCU_TESR_TCST2 (1 << 2) 437 #define TCU_TESR_TCST1 (1 << 1) 438 #define TCU_TESR_TCST0 (1 << 0) 439 440 #define TCU_TECR_TCCL5 (1 << 5) 441 #define TCU_TECR_TCCL4 (1 << 4) 442 #define TCU_TECR_TCCL3 (1 << 3) 443 #define TCU_TECR_TCCL2 (1 << 2) 444 #define TCU_TECR_TCCL1 (1 << 1) 445 #define TCU_TECR_TCCL0 (1 << 0) 446 447 #define TCU_TFR_HFLAG5 (1 << 21) 448 #define TCU_TFR_HFLAG4 (1 << 20) 449 #define TCU_TFR_HFLAG3 (1 << 19) 450 #define TCU_TFR_HFLAG2 (1 << 18) 451 #define TCU_TFR_HFLAG1 (1 << 17) 452 #define TCU_TFR_HFLAG0 (1 << 16) 453 #define TCU_TFR_FFLAG5 (1 << 5) 454 #define TCU_TFR_FFLAG4 (1 << 4) 455 #define TCU_TFR_FFLAG3 (1 << 3) 456 #define TCU_TFR_FFLAG2 (1 << 2) 457 #define TCU_TFR_FFLAG1 (1 << 1) 458 #define TCU_TFR_FFLAG0 (1 << 0) 459 460 #define TCU_TFSR_HFLAG5 (1 << 21) 461 #define TCU_TFSR_HFLAG4 (1 << 20) 462 #define TCU_TFSR_HFLAG3 (1 << 19) 463 #define TCU_TFSR_HFLAG2 (1 << 18) 464 #define TCU_TFSR_HFLAG1 (1 << 17) 465 #define TCU_TFSR_HFLAG0 (1 << 16) 466 #define TCU_TFSR_FFLAG5 (1 << 5) 467 #define TCU_TFSR_FFLAG4 (1 << 4) 468 #define TCU_TFSR_FFLAG3 (1 << 3) 469 #define TCU_TFSR_FFLAG2 (1 << 2) 470 #define TCU_TFSR_FFLAG1 (1 << 1) 471 #define TCU_TFSR_FFLAG0 (1 << 0) 472 473 #define TCU_TFCR_HFLAG5 (1 << 21) 474 #define TCU_TFCR_HFLAG4 (1 << 20) 475 #define TCU_TFCR_HFLAG3 (1 << 19) 476 #define TCU_TFCR_HFLAG2 (1 << 18) 477 #define TCU_TFCR_HFLAG1 (1 << 17) 478 #define TCU_TFCR_HFLAG0 (1 << 16) 479 #define TCU_TFCR_FFLAG5 (1 << 5) 480 #define TCU_TFCR_FFLAG4 (1 << 4) 481 #define TCU_TFCR_FFLAG3 (1 << 3) 482 #define TCU_TFCR_FFLAG2 (1 << 2) 483 #define TCU_TFCR_FFLAG1 (1 << 1) 484 #define TCU_TFCR_FFLAG0 (1 << 0) 485 486 #define TCU_TMR_HMASK5 (1 << 21) 487 #define TCU_TMR_HMASK4 (1 << 20) 488 #define TCU_TMR_HMASK3 (1 << 19) 489 #define TCU_TMR_HMASK2 (1 << 18) 490 #define TCU_TMR_HMASK1 (1 << 17) 491 #define TCU_TMR_HMASK0 (1 << 16) 492 #define TCU_TMR_FMASK5 (1 << 5) 493 #define TCU_TMR_FMASK4 (1 << 4) 494 #define TCU_TMR_FMASK3 (1 << 3) 495 #define TCU_TMR_FMASK2 (1 << 2) 496 #define TCU_TMR_FMASK1 (1 << 1) 497 #define TCU_TMR_FMASK0 (1 << 0) 498 499 #define TCU_TMSR_HMST5 (1 << 21) 500 #define TCU_TMSR_HMST4 (1 << 20) 501 #define TCU_TMSR_HMST3 (1 << 19) 502 #define TCU_TMSR_HMST2 (1 << 18) 503 #define TCU_TMSR_HMST1 (1 << 17) 504 #define TCU_TMSR_HMST0 (1 << 16) 505 #define TCU_TMSR_FMST5 (1 << 5) 506 #define TCU_TMSR_FMST4 (1 << 4) 507 #define TCU_TMSR_FMST3 (1 << 3) 508 #define TCU_TMSR_FMST2 (1 << 2) 509 #define TCU_TMSR_FMST1 (1 << 1) 510 #define TCU_TMSR_FMST0 (1 << 0) 511 512 #define TCU_TMCR_HMCL5 (1 << 21) 513 #define TCU_TMCR_HMCL4 (1 << 20) 514 #define TCU_TMCR_HMCL3 (1 << 19) 515 #define TCU_TMCR_HMCL2 (1 << 18) 516 #define TCU_TMCR_HMCL1 (1 << 17) 517 #define TCU_TMCR_HMCL0 (1 << 16) 518 #define TCU_TMCR_FMCL5 (1 << 5) 519 #define TCU_TMCR_FMCL4 (1 << 4) 520 #define TCU_TMCR_FMCL3 (1 << 3) 521 #define TCU_TMCR_FMCL2 (1 << 2) 522 #define TCU_TMCR_FMCL1 (1 << 1) 523 #define TCU_TMCR_FMCL0 (1 << 0) 524 525 #define TCU_TSR_WDTS (1 << 16) 526 #define TCU_TSR_STOP5 (1 << 5) 527 #define TCU_TSR_STOP4 (1 << 4) 528 #define TCU_TSR_STOP3 (1 << 3) 529 #define TCU_TSR_STOP2 (1 << 2) 530 #define TCU_TSR_STOP1 (1 << 1) 531 #define TCU_TSR_STOP0 (1 << 0) 532 533 #define TCU_TSSR_WDTSS (1 << 16) 534 #define TCU_TSSR_STPS5 (1 << 5) 535 #define TCU_TSSR_STPS4 (1 << 4) 536 #define TCU_TSSR_STPS3 (1 << 3) 537 #define TCU_TSSR_STPS2 (1 << 2) 538 #define TCU_TSSR_STPS1 (1 << 1) 539 #define TCU_TSSR_STPS0 (1 << 0) 540 541 #define TCU_TSSR_WDTSC (1 << 16) 542 #define TCU_TSSR_STPC5 (1 << 5) 543 #define TCU_TSSR_STPC4 (1 << 4) 544 #define TCU_TSSR_STPC3 (1 << 3) 545 #define TCU_TSSR_STPC2 (1 << 2) 546 #define TCU_TSSR_STPC1 (1 << 1) 547 #define TCU_TSSR_STPC0 (1 << 0) 548 549 550 /* 551 * WDT (WatchDog Timer) 552 */ 553 #define WDT_TDR (WDT_BASE + 0x00) 554 #define WDT_TCER (WDT_BASE + 0x04) 555 #define WDT_TCNT (WDT_BASE + 0x08) 556 #define WDT_TCSR (WDT_BASE + 0x0C) 557 558 #define REG_WDT_TDR REG16(WDT_TDR) 559 #define REG_WDT_TCER REG8(WDT_TCER) 560 #define REG_WDT_TCNT REG16(WDT_TCNT) 561 #define REG_WDT_TCSR REG16(WDT_TCSR) 562 563 /* Register definition */ 564 #define WDT_TCSR_PRESCALE_BIT 3 565 #define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) 566 #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) 567 #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) 568 #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) 569 #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) 570 #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) 571 #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) 572 #define WDT_TCSR_EXT_EN (1 << 2) 573 #define WDT_TCSR_RTC_EN (1 << 1) 574 #define WDT_TCSR_PCK_EN (1 << 0) 575 576 #define WDT_TCER_TCEN (1 << 0) 577 578 579 /* 580 * DMAC (DMA Controller) 581 */ 582 583 #define MAX_DMA_NUM 6 /* max 6 channels */ 584 585 #define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */ 586 #define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */ 587 #define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */ 588 #define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */ 589 #define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */ 590 #define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */ 591 #define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */ 592 #define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */ 593 #define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */ 594 #define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */ 595 #define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */ 596 597 /* channel 0 */ 598 #define DMAC_DSAR0 DMAC_DSAR(0) 599 #define DMAC_DTAR0 DMAC_DTAR(0) 600 #define DMAC_DTCR0 DMAC_DTCR(0) 601 #define DMAC_DRSR0 DMAC_DRSR(0) 602 #define DMAC_DCCSR0 DMAC_DCCSR(0) 603 #define DMAC_DCMD0 DMAC_DCMD(0) 604 #define DMAC_DDA0 DMAC_DDA(0) 605 606 /* channel 1 */ 607 #define DMAC_DSAR1 DMAC_DSAR(1) 608 #define DMAC_DTAR1 DMAC_DTAR(1) 609 #define DMAC_DTCR1 DMAC_DTCR(1) 610 #define DMAC_DRSR1 DMAC_DRSR(1) 611 #define DMAC_DCCSR1 DMAC_DCCSR(1) 612 #define DMAC_DCMD1 DMAC_DCMD(1) 613 #define DMAC_DDA1 DMAC_DDA(1) 614 615 /* channel 2 */ 616 #define DMAC_DSAR2 DMAC_DSAR(2) 617 #define DMAC_DTAR2 DMAC_DTAR(2) 618 #define DMAC_DTCR2 DMAC_DTCR(2) 619 #define DMAC_DRSR2 DMAC_DRSR(2) 620 #define DMAC_DCCSR2 DMAC_DCCSR(2) 621 #define DMAC_DCMD2 DMAC_DCMD(2) 622 #define DMAC_DDA2 DMAC_DDA(2) 623 624 /* channel 3 */ 625 #define DMAC_DSAR3 DMAC_DSAR(3) 626 #define DMAC_DTAR3 DMAC_DTAR(3) 627 #define DMAC_DTCR3 DMAC_DTCR(3) 628 #define DMAC_DRSR3 DMAC_DRSR(3) 629 #define DMAC_DCCSR3 DMAC_DCCSR(3) 630 #define DMAC_DCMD3 DMAC_DCMD(3) 631 #define DMAC_DDA3 DMAC_DDA(3) 632 633 /* channel 4 */ 634 #define DMAC_DSAR4 DMAC_DSAR(4) 635 #define DMAC_DTAR4 DMAC_DTAR(4) 636 #define DMAC_DTCR4 DMAC_DTCR(4) 637 #define DMAC_DRSR4 DMAC_DRSR(4) 638 #define DMAC_DCCSR4 DMAC_DCCSR(4) 639 #define DMAC_DCMD4 DMAC_DCMD(4) 640 #define DMAC_DDA4 DMAC_DDA(4) 641 642 /* channel 5 */ 643 #define DMAC_DSAR5 DMAC_DSAR(5) 644 #define DMAC_DTAR5 DMAC_DTAR(5) 645 #define DMAC_DTCR5 DMAC_DTCR(5) 646 #define DMAC_DRSR5 DMAC_DRSR(5) 647 #define DMAC_DCCSR5 DMAC_DCCSR(5) 648 #define DMAC_DCMD5 DMAC_DCMD(5) 649 #define DMAC_DDA5 DMAC_DDA(5) 650 651 #define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) 652 #define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n))) 653 #define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) 654 #define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) 655 #define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) 656 #define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n))) 657 #define REG_DMAC_DDA(n) REG32(DMAC_DDA((n))) 658 #define REG_DMAC_DMACR REG32(DMAC_DMACR) 659 #define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR) 660 #define REG_DMAC_DMADBR REG32(DMAC_DMADBR) 661 #define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR) 662 663 /* DMA request source register */ 664 #define DMAC_DRSR_RS_BIT 0 665 #define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) 666 #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) 667 #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) 668 #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) 669 #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) 670 #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) 671 #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) 672 #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) 673 #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) 674 #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) 675 #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT) 676 #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT) 677 #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT) 678 679 /* DMA channel control/status register */ 680 #define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */ 681 #define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */ 682 #define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT) 683 #define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */ 684 #define DMAC_DCCSR_AR (1 << 4) /* address error */ 685 #define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */ 686 #define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */ 687 #define DMAC_DCCSR_CT (1 << 1) /* count terminated */ 688 #define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */ 689 690 /* DMA channel command register */ 691 #define DMAC_DCMD_SAI (1 << 23) /* source address increment */ 692 #define DMAC_DCMD_DAI (1 << 22) /* dest address increment */ 693 #define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */ 694 #define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT) 695 #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT) 696 #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT) 697 #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT) 698 #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT) 699 #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT) 700 #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT) 701 #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT) 702 #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT) 703 #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT) 704 #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT) 705 #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT) 706 #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT) 707 #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT) 708 #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT) 709 #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT) 710 #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT) 711 #define DMAC_DCMD_SWDH_BIT 14 /* source port width */ 712 #define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT) 713 #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT) 714 #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT) 715 #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT) 716 #define DMAC_DCMD_DWDH_BIT 12 /* dest port width */ 717 #define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT) 718 #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT) 719 #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT) 720 #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT) 721 #define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */ 722 #define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT) 723 #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT) 724 #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT) 725 #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT) 726 #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT) 727 #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT) 728 #define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */ 729 #define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */ 730 #define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */ 731 #define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */ 732 #define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */ 733 #define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */ 734 735 /* DMA descriptor address register */ 736 #define DMAC_DDA_BASE_BIT 12 /* descriptor base address */ 737 #define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT) 738 #define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */ 739 #define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT) 740 741 /* DMA control register */ 742 #define DMAC_DMACR_PR_BIT 8 /* channel priority mode */ 743 #define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) 744 #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT) 745 #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT) 746 #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT) 747 #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */ 748 #define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */ 749 #define DMAC_DMACR_AR (1 << 2) /* address error flag */ 750 #define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */ 751 752 /* DMA doorbell register */ 753 #define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */ 754 #define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */ 755 #define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */ 756 #define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */ 757 #define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */ 758 #define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */ 759 760 /* DMA doorbell set register */ 761 #define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */ 762 #define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */ 763 #define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */ 764 #define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */ 765 #define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */ 766 #define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */ 767 768 /* DMA interrupt pending register */ 769 #define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */ 770 #define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */ 771 #define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */ 772 #define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */ 773 #define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */ 774 #define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */ 775 776 777 /************************************************************************* 778 * GPIO (General-Purpose I/O Ports) 779 *************************************************************************/ 780 #define MAX_GPIO_NUM 128 781 782 /* = 0,1,2,3 */ 783 #define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */ 784 #define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */ 785 #define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */ 786 #define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */ 787 #define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */ 788 #define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */ 789 #define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */ 790 #define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */ 791 #define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */ 792 #define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */ 793 #define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */ 794 #define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */ 795 #define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */ 796 #define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */ 797 #define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */ 798 #define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */ 799 #define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */ 800 #define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */ 801 #define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */ 802 #define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */ 803 #define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */ 804 #define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */ 805 #define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */ 806 #define GPIO_PXFLGC(n) (GPIO_BASE + (0x84 + (n)*0x100)) /* Port Flag clear Register */ 807 808 #define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */ 809 #define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */ 810 #define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n))) 811 #define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n))) 812 #define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */ 813 #define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n))) 814 #define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n))) 815 #define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */ 816 #define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n))) 817 #define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n))) 818 #define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */ 819 #define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n))) 820 #define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n))) 821 #define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/ 822 #define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n))) 823 #define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n))) 824 #define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */ 825 #define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n))) 826 #define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n))) 827 #define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */ 828 #define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n))) 829 #define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n))) 830 #define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */ 831 #define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */ 832 833 834 /************************************************************************* 835 * UART 836 *************************************************************************/ 837 838 #define IRDA_BASE UART0_BASE 839 /* #define UART_BASE UART0_BASE */ 840 #define UART_OFF 0x1000 841 842 /* Register Offset */ 843 #define OFF_RDR (0x00) /* R 8b H'xx */ 844 #define OFF_TDR (0x00) /* W 8b H'xx */ 845 #define OFF_DLLR (0x00) /* RW 8b H'00 */ 846 #define OFF_DLHR (0x04) /* RW 8b H'00 */ 847 #define OFF_IER (0x04) /* RW 8b H'00 */ 848 #define OFF_ISR (0x08) /* R 8b H'01 */ 849 #define OFF_FCR (0x08) /* W 8b H'00 */ 850 #define OFF_LCR (0x0C) /* RW 8b H'00 */ 851 #define OFF_MCR (0x10) /* RW 8b H'00 */ 852 #define OFF_LSR (0x14) /* R 8b H'00 */ 853 #define OFF_MSR (0x18) /* R 8b H'00 */ 854 #define OFF_SPR (0x1C) /* RW 8b H'00 */ 855 #define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ 856 #define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */ 857 #define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */ 858 859 /* Register Address */ 860 #define UART0_RDR (UART0_BASE + OFF_RDR) 861 #define UART0_TDR (UART0_BASE + OFF_TDR) 862 #define UART0_DLLR (UART0_BASE + OFF_DLLR) 863 #define UART0_DLHR (UART0_BASE + OFF_DLHR) 864 #define UART0_IER (UART0_BASE + OFF_IER) 865 #define UART0_ISR (UART0_BASE + OFF_ISR) 866 #define UART0_FCR (UART0_BASE + OFF_FCR) 867 #define UART0_LCR (UART0_BASE + OFF_LCR) 868 #define UART0_MCR (UART0_BASE + OFF_MCR) 869 #define UART0_LSR (UART0_BASE + OFF_LSR) 870 #define UART0_MSR (UART0_BASE + OFF_MSR) 871 #define UART0_SPR (UART0_BASE + OFF_SPR) 872 #define UART0_SIRCR (UART0_BASE + OFF_SIRCR) 873 #define UART0_UMR (UART0_BASE + OFF_UMR) 874 #define UART0_UACR (UART0_BASE + OFF_UACR) 875 876 /* 877 * Define macros for UART_IER 878 * UART Interrupt Enable Register 879 */ 880 #define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ 881 #define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ 882 #define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ 883 #define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ 884 #define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ 885 886 /* 887 * Define macros for UART_ISR 888 * UART Interrupt Status Register 889 */ 890 #define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ 891 #define UART_ISR_IID (7 << 1) /* Source of Interrupt */ 892 #define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ 893 #define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ 894 #define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ 895 #define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ 896 #define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */ 897 #define UART_ISR_FFMS_NO_FIFO (0 << 6) 898 #define UART_ISR_FFMS_FIFO_MODE (3 << 6) 899 900 /* 901 * Define macros for UART_FCR 902 * UART FIFO Control Register 903 */ 904 #define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ 905 #define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ 906 #define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ 907 #define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ 908 #define UART_FCR_UUE (1 << 4) /* 0: disable UART */ 909 #define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ 910 #define UART_FCR_RTRG_1 (0 << 6) 911 #define UART_FCR_RTRG_4 (1 << 6) 912 #define UART_FCR_RTRG_8 (2 << 6) 913 #define UART_FCR_RTRG_15 (3 << 6) 914 915 /* 916 * Define macros for UART_LCR 917 * UART Line Control Register 918 */ 919 #define UART_LCR_WLEN (3 << 0) /* word length */ 920 #define UART_LCR_WLEN_5 (0 << 0) 921 #define UART_LCR_WLEN_6 (1 << 0) 922 #define UART_LCR_WLEN_7 (2 << 0) 923 #define UART_LCR_WLEN_8 (3 << 0) 924 #define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 925 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 926 #define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 927 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 928 #define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 929 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 930 931 #define UART_LCR_PE (1 << 3) /* 0: parity disable */ 932 #define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ 933 #define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ 934 #define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ 935 #define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ 936 937 /* 938 * Define macros for UART_LSR 939 * UART Line Status Register 940 */ 941 #define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ 942 #define UART_LSR_ORER (1 << 1) /* 0: no overrun error */ 943 #define UART_LSR_PER (1 << 2) /* 0: no parity error */ 944 #define UART_LSR_FER (1 << 3) /* 0; no framing error */ 945 #define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ 946 #define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ 947 #define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ 948 #define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ 949 950 /* 951 * Define macros for UART_MCR 952 * UART Modem Control Register 953 */ 954 #define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ 955 #define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ 956 #define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */ 957 #define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ 958 #define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ 959 #define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ 960 961 /* 962 * Define macros for UART_MSR 963 * UART Modem Status Register 964 */ 965 #define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */ 966 #define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */ 967 #define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */ 968 #define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */ 969 #define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ 970 #define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ 971 #define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ 972 #define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ 973 974 /* 975 * Define macros for SIRCR 976 * Slow IrDA Control Register 977 */ 978 #define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ 979 #define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ 980 #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length 981 1: 0 pulse width is 1.6us for 115.2Kbps */ 982 #define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ 983 #define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ 984 985 986 /************************************************************************* 987 * AIC (AC97/I2S Controller) 988 *************************************************************************/ 989 #define AIC_FR (AIC_BASE + 0x000) 990 #define AIC_CR (AIC_BASE + 0x004) 991 #define AIC_ACCR1 (AIC_BASE + 0x008) 992 #define AIC_ACCR2 (AIC_BASE + 0x00C) 993 #define AIC_I2SCR (AIC_BASE + 0x010) 994 #define AIC_SR (AIC_BASE + 0x014) 995 #define AIC_ACSR (AIC_BASE + 0x018) 996 #define AIC_I2SSR (AIC_BASE + 0x01C) 997 #define AIC_ACCAR (AIC_BASE + 0x020) 998 #define AIC_ACCDR (AIC_BASE + 0x024) 999 #define AIC_ACSAR (AIC_BASE + 0x028) 1000 #define AIC_ACSDR (AIC_BASE + 0x02C) 1001 #define AIC_I2SDIV (AIC_BASE + 0x030) 1002 #define AIC_DR (AIC_BASE + 0x034) 1003 1004 #define REG_AIC_FR REG32(AIC_FR) 1005 #define REG_AIC_CR REG32(AIC_CR) 1006 #define REG_AIC_ACCR1 REG32(AIC_ACCR1) 1007 #define REG_AIC_ACCR2 REG32(AIC_ACCR2) 1008 #define REG_AIC_I2SCR REG32(AIC_I2SCR) 1009 #define REG_AIC_SR REG32(AIC_SR) 1010 #define REG_AIC_ACSR REG32(AIC_ACSR) 1011 #define REG_AIC_I2SSR REG32(AIC_I2SSR) 1012 #define REG_AIC_ACCAR REG32(AIC_ACCAR) 1013 #define REG_AIC_ACCDR REG32(AIC_ACCDR) 1014 #define REG_AIC_ACSAR REG32(AIC_ACSAR) 1015 #define REG_AIC_ACSDR REG32(AIC_ACSDR) 1016 #define REG_AIC_I2SDIV REG32(AIC_I2SDIV) 1017 #define REG_AIC_DR REG32(AIC_DR) 1018 1019 /* AIC Controller Configuration Register (AIC_FR) */ 1020 1021 #define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */ 1022 #define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) 1023 #define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */ 1024 #define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) 1025 #define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */ 1026 #define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */ 1027 #define AIC_FR_RST (1 << 3) /* AIC registers reset */ 1028 #define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */ 1029 #define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */ 1030 #define AIC_FR_ENB (1 << 0) /* AIC enable bit */ 1031 1032 /* AIC Controller Common Control Register (AIC_CR) */ 1033 1034 #define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */ 1035 #define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT) 1036 #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT) 1037 #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT) 1038 #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT) 1039 #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT) 1040 #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT) 1041 #define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */ 1042 #define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT) 1043 #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT) 1044 #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT) 1045 #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT) 1046 #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT) 1047 #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT) 1048 #define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */ 1049 #define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */ 1050 #define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */ 1051 #define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */ 1052 #define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */ 1053 #define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */ 1054 #define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */ 1055 #define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */ 1056 #define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */ 1057 #define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */ 1058 #define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */ 1059 #define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */ 1060 #define AIC_CR_EREC (1 << 0) /* Enable Record Function */ 1061 1062 /* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ 1063 1064 #define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */ 1065 #define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) 1066 #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ 1067 #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ 1068 #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ 1069 #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */ 1070 #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */ 1071 #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */ 1072 #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */ 1073 #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ 1074 #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */ 1075 #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */ 1076 #define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */ 1077 #define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) 1078 #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ 1079 #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ 1080 #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ 1081 #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */ 1082 #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */ 1083 #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */ 1084 #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */ 1085 #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ 1086 #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */ 1087 #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */ 1088 1089 /* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ 1090 1091 #define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */ 1092 #define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */ 1093 #define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */ 1094 #define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */ 1095 #define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) 1096 #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ 1097 #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ 1098 #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ 1099 #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ 1100 #define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */ 1101 #define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) 1102 #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ 1103 #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ 1104 #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ 1105 #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ 1106 #define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */ 1107 #define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */ 1108 #define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */ 1109 #define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */ 1110 1111 /* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ 1112 1113 #define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */ 1114 #define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */ 1115 #define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) 1116 #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ 1117 #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ 1118 #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ 1119 #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ 1120 #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ 1121 #define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */ 1122 1123 /* AIC Controller FIFO Status Register (AIC_SR) */ 1124 1125 #define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */ 1126 #define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT) 1127 #define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */ 1128 #define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT) 1129 #define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */ 1130 #define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */ 1131 #define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */ 1132 #define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */ 1133 1134 /* AIC Controller AC-link Status Register (AIC_ACSR) */ 1135 1136 #define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */ 1137 #define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */ 1138 #define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */ 1139 #define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */ 1140 #define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */ 1141 #define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */ 1142 1143 /* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ 1144 1145 #define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */ 1146 1147 /* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ 1148 1149 #define AIC_ACCAR_CAR_BIT 0 1150 #define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) 1151 1152 /* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ 1153 1154 #define AIC_ACCDR_CDR_BIT 0 1155 #define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) 1156 1157 /* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ 1158 1159 #define AIC_ACSAR_SAR_BIT 0 1160 #define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) 1161 1162 /* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ 1163 1164 #define AIC_ACSDR_SDR_BIT 0 1165 #define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) 1166 1167 /* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ 1168 1169 #define AIC_I2SDIV_DIV_BIT 0 1170 #define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) 1171 #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ 1172 #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ 1173 #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ 1174 #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ 1175 #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ 1176 #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ 1177 1178 1179 /************************************************************************* 1180 * ICDC (Internal CODEC) 1181 *************************************************************************/ 1182 #define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */ 1183 #define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */ 1184 #define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */ 1185 #define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */ 1186 #define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */ 1187 #define ICDC_CDCCR1 (ICDC_BASE + 0x0080) 1188 #define ICDC_CDCCR2 (ICDC_BASE + 0x0084) 1189 1190 #define REG_ICDC_CR REG32(ICDC_CR) 1191 #define REG_ICDC_APWAIT REG32(ICDC_APWAIT) 1192 #define REG_ICDC_APPRE REG32(ICDC_APPRE) 1193 #define REG_ICDC_APHPEN REG32(ICDC_APHPEN) 1194 #define REG_ICDC_APSR REG32(ICDC_APSR) 1195 #define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1) 1196 #define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2) 1197 1198 /* ICDC Control Register */ 1199 #define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */ 1200 #define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT) 1201 #define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */ 1202 #define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT) 1203 #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT) 1204 #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT) 1205 #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT) 1206 #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT) 1207 #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT) 1208 #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT) 1209 #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT) 1210 #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT) 1211 #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT) 1212 #define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */ 1213 #define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT) 1214 #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT) 1215 #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT) 1216 #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT) 1217 #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT) 1218 #define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */ 1219 #define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT) 1220 #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT) 1221 #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT) 1222 #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT) 1223 #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT) 1224 #define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */ 1225 #define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */ 1226 #define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */ 1227 #define ICDC_CR_EADC (1 << 10) /* Enable ADC */ 1228 #define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */ 1229 #define ICDC_CR_EDAC (1 << 8) /* Enable DAC */ 1230 #define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */ 1231 #define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */ 1232 #define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */ 1233 #define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */ 1234 #define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */ 1235 #define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */ 1236 1237 /* Anti-Pop WAIT Stage Timing Control Register */ 1238 #define ICDC_APWAIT_WAITSN_BIT 0 1239 #define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT) 1240 1241 /* Anti-Pop HPEN-PRE Stage Timing Control Register */ 1242 #define ICDC_APPRE_PRESN_BIT 0 1243 #define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT) 1244 1245 /* Anti-Pop HPEN Stage Timing Control Register */ 1246 #define ICDC_APHPEN_HPENSN_BIT 0 1247 #define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT) 1248 1249 /* Anti-Pop Status Register */ 1250 #define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */ 1251 #define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT) 1252 #define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */ 1253 #define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */ 1254 #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */ 1255 #define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */ 1256 #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */ 1257 #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */ 1258 #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */ 1259 #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */ 1260 #define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */ 1261 #define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT) 1262 1263 1264 /************************************************************************* 1265 * I2C 1266 *************************************************************************/ 1267 #define I2C_DR (I2C_BASE + 0x000) 1268 #define I2C_CR (I2C_BASE + 0x004) 1269 #define I2C_SR (I2C_BASE + 0x008) 1270 #define I2C_GR (I2C_BASE + 0x00C) 1271 1272 #define REG_I2C_DR REG8(I2C_DR) 1273 #define REG_I2C_CR REG8(I2C_CR) 1274 #define REG_I2C_SR REG8(I2C_SR) 1275 #define REG_I2C_GR REG16(I2C_GR) 1276 1277 /* I2C Control Register (I2C_CR) */ 1278 1279 #define I2C_CR_IEN (1 << 4) 1280 #define I2C_CR_STA (1 << 3) 1281 #define I2C_CR_STO (1 << 2) 1282 #define I2C_CR_AC (1 << 1) 1283 #define I2C_CR_I2CE (1 << 0) 1284 1285 /* I2C Status Register (I2C_SR) */ 1286 1287 #define I2C_SR_STX (1 << 4) 1288 #define I2C_SR_BUSY (1 << 3) 1289 #define I2C_SR_TEND (1 << 2) 1290 #define I2C_SR_DRF (1 << 1) 1291 #define I2C_SR_ACKF (1 << 0) 1292 1293 1294 /************************************************************************* 1295 * SSI 1296 *************************************************************************/ 1297 #define SSI_DR (SSI_BASE + 0x000) 1298 #define SSI_CR0 (SSI_BASE + 0x004) 1299 #define SSI_CR1 (SSI_BASE + 0x008) 1300 #define SSI_SR (SSI_BASE + 0x00C) 1301 #define SSI_ITR (SSI_BASE + 0x010) 1302 #define SSI_ICR (SSI_BASE + 0x014) 1303 #define SSI_GR (SSI_BASE + 0x018) 1304 1305 #define REG_SSI_DR REG32(SSI_DR) 1306 #define REG_SSI_CR0 REG16(SSI_CR0) 1307 #define REG_SSI_CR1 REG32(SSI_CR1) 1308 #define REG_SSI_SR REG32(SSI_SR) 1309 #define REG_SSI_ITR REG16(SSI_ITR) 1310 #define REG_SSI_ICR REG8(SSI_ICR) 1311 #define REG_SSI_GR REG16(SSI_GR) 1312 1313 /* SSI Data Register (SSI_DR) */ 1314 1315 #define SSI_DR_GPC_BIT 0 1316 #define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) 1317 1318 /* SSI Control Register 0 (SSI_CR0) */ 1319 1320 #define SSI_CR0_SSIE (1 << 15) 1321 #define SSI_CR0_TIE (1 << 14) 1322 #define SSI_CR0_RIE (1 << 13) 1323 #define SSI_CR0_TEIE (1 << 12) 1324 #define SSI_CR0_REIE (1 << 11) 1325 #define SSI_CR0_LOOP (1 << 10) 1326 #define SSI_CR0_RFINE (1 << 9) 1327 #define SSI_CR0_RFINC (1 << 8) 1328 #define SSI_CR0_FSEL (1 << 6) 1329 #define SSI_CR0_TFLUSH (1 << 2) 1330 #define SSI_CR0_RFLUSH (1 << 1) 1331 #define SSI_CR0_DISREV (1 << 0) 1332 1333 /* SSI Control Register 1 (SSI_CR1) */ 1334 1335 #define SSI_CR1_FRMHL_BIT 30 1336 #define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) 1337 #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ 1338 #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ 1339 #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ 1340 #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ 1341 #define SSI_CR1_TFVCK_BIT 28 1342 #define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) 1343 #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) 1344 #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) 1345 #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) 1346 #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) 1347 #define SSI_CR1_TCKFI_BIT 26 1348 #define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) 1349 #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) 1350 #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) 1351 #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) 1352 #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) 1353 #define SSI_CR1_LFST (1 << 25) 1354 #define SSI_CR1_ITFRM (1 << 24) 1355 #define SSI_CR1_UNFIN (1 << 23) 1356 #define SSI_CR1_MULTS (1 << 22) 1357 #define SSI_CR1_FMAT_BIT 20 1358 #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) 1359 #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola????s SPI format */ 1360 #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ 1361 #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ 1362 #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ 1363 #define SSI_CR1_TTRG_BIT 16 1364 #define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT) 1365 #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT) 1366 #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT) 1367 #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT) 1368 #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT) 1369 #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT) 1370 #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT) 1371 #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT) 1372 #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT) 1373 #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT) 1374 #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT) 1375 #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT) 1376 #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT) 1377 #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT) 1378 #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT) 1379 #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT) 1380 #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT) 1381 #define SSI_CR1_MCOM_BIT 12 1382 #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) 1383 #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ 1384 #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ 1385 #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ 1386 #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ 1387 #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ 1388 #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ 1389 #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ 1390 #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ 1391 #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ 1392 #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ 1393 #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ 1394 #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ 1395 #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ 1396 #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ 1397 #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ 1398 #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ 1399 #define SSI_CR1_RTRG_BIT 8 1400 #define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT) 1401 #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) 1402 #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT) 1403 #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT) 1404 #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT) 1405 #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT) 1406 #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT) 1407 #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT) 1408 #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT) 1409 #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT) 1410 #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT) 1411 #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT) 1412 #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT) 1413 #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT) 1414 #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT) 1415 #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT) 1416 #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT) 1417 #define SSI_CR1_FLEN_BIT 4 1418 #define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) 1419 #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) 1420 #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) 1421 #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) 1422 #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) 1423 #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) 1424 #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) 1425 #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) 1426 #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) 1427 #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) 1428 #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) 1429 #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) 1430 #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) 1431 #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) 1432 #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) 1433 #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) 1434 #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) 1435 #define SSI_CR1_PHA (1 << 1) 1436 #define SSI_CR1_POL (1 << 0) 1437 1438 /* SSI Status Register (SSI_SR) */ 1439 1440 #define SSI_SR_TFIFONUM_BIT 16 1441 #define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT) 1442 #define SSI_SR_RFIFONUM_BIT 8 1443 #define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT) 1444 #define SSI_SR_END (1 << 7) 1445 #define SSI_SR_BUSY (1 << 6) 1446 #define SSI_SR_TFF (1 << 5) 1447 #define SSI_SR_RFE (1 << 4) 1448 #define SSI_SR_TFHE (1 << 3) 1449 #define SSI_SR_RFHF (1 << 2) 1450 #define SSI_SR_UNDR (1 << 1) 1451 #define SSI_SR_OVER (1 << 0) 1452 1453 /* SSI Interval Time Control Register (SSI_ITR) */ 1454 1455 #define SSI_ITR_CNTCLK (1 << 15) 1456 #define SSI_ITR_IVLTM_BIT 0 1457 #define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) 1458 1459 1460 /************************************************************************* 1461 * MSC 1462 *************************************************************************/ 1463 #define MSC_STRPCL (MSC_BASE + 0x000) 1464 #define MSC_STAT (MSC_BASE + 0x004) 1465 #define MSC_CLKRT (MSC_BASE + 0x008) 1466 #define MSC_CMDAT (MSC_BASE + 0x00C) 1467 #define MSC_RESTO (MSC_BASE + 0x010) 1468 #define MSC_RDTO (MSC_BASE + 0x014) 1469 #define MSC_BLKLEN (MSC_BASE + 0x018) 1470 #define MSC_NOB (MSC_BASE + 0x01C) 1471 #define MSC_SNOB (MSC_BASE + 0x020) 1472 #define MSC_IMASK (MSC_BASE + 0x024) 1473 #define MSC_IREG (MSC_BASE + 0x028) 1474 #define MSC_CMD (MSC_BASE + 0x02C) 1475 #define MSC_ARG (MSC_BASE + 0x030) 1476 #define MSC_RES (MSC_BASE + 0x034) 1477 #define MSC_RXFIFO (MSC_BASE + 0x038) 1478 #define MSC_TXFIFO (MSC_BASE + 0x03C) 1479 1480 #define REG_MSC_STRPCL REG16(MSC_STRPCL) 1481 #define REG_MSC_STAT REG32(MSC_STAT) 1482 #define REG_MSC_CLKRT REG16(MSC_CLKRT) 1483 #define REG_MSC_CMDAT REG32(MSC_CMDAT) 1484 #define REG_MSC_RESTO REG16(MSC_RESTO) 1485 #define REG_MSC_RDTO REG16(MSC_RDTO) 1486 #define REG_MSC_BLKLEN REG16(MSC_BLKLEN) 1487 #define REG_MSC_NOB REG16(MSC_NOB) 1488 #define REG_MSC_SNOB REG16(MSC_SNOB) 1489 #define REG_MSC_IMASK REG16(MSC_IMASK) 1490 #define REG_MSC_IREG REG16(MSC_IREG) 1491 #define REG_MSC_CMD REG8(MSC_CMD) 1492 #define REG_MSC_ARG REG32(MSC_ARG) 1493 #define REG_MSC_RES REG16(MSC_RES) 1494 #define REG_MSC_RXFIFO REG32(MSC_RXFIFO) 1495 #define REG_MSC_TXFIFO REG32(MSC_TXFIFO) 1496 1497 /* MSC Clock and Control Register (MSC_STRPCL) */ 1498 1499 #define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) 1500 #define MSC_STRPCL_EXIT_TRANSFER (1 << 6) 1501 #define MSC_STRPCL_START_READWAIT (1 << 5) 1502 #define MSC_STRPCL_STOP_READWAIT (1 << 4) 1503 #define MSC_STRPCL_RESET (1 << 3) 1504 #define MSC_STRPCL_START_OP (1 << 2) 1505 #define MSC_STRPCL_CLOCK_CONTROL_BIT 0 1506 #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) 1507 #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ 1508 #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ 1509 1510 /* MSC Status Register (MSC_STAT) */ 1511 1512 #define MSC_STAT_IS_RESETTING (1 << 15) 1513 #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) 1514 #define MSC_STAT_PRG_DONE (1 << 13) 1515 #define MSC_STAT_DATA_TRAN_DONE (1 << 12) 1516 #define MSC_STAT_END_CMD_RES (1 << 11) 1517 #define MSC_STAT_DATA_FIFO_AFULL (1 << 10) 1518 #define MSC_STAT_IS_READWAIT (1 << 9) 1519 #define MSC_STAT_CLK_EN (1 << 8) 1520 #define MSC_STAT_DATA_FIFO_FULL (1 << 7) 1521 #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) 1522 #define MSC_STAT_CRC_RES_ERR (1 << 5) 1523 #define MSC_STAT_CRC_READ_ERROR (1 << 4) 1524 #define MSC_STAT_CRC_WRITE_ERROR_BIT 2 1525 #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) 1526 #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ 1527 #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ 1528 #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ 1529 #define MSC_STAT_TIME_OUT_RES (1 << 1) 1530 #define MSC_STAT_TIME_OUT_READ (1 << 0) 1531 1532 /* MSC Bus Clock Control Register (MSC_CLKRT) */ 1533 1534 #define MSC_CLKRT_CLK_RATE_BIT 0 1535 #define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) 1536 #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ 1537 #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ 1538 #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ 1539 #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ 1540 #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ 1541 #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ 1542 #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ 1543 #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ 1544 1545 /* MSC Command Sequence Control Register (MSC_CMDAT) */ 1546 1547 #define MSC_CMDAT_IO_ABORT (1 << 11) 1548 #define MSC_CMDAT_BUS_WIDTH_BIT 9 1549 #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) 1550 #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) 1551 #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) 1552 #define MSC_CMDAT_DMA_EN (1 << 8) 1553 #define MSC_CMDAT_INIT (1 << 7) 1554 #define MSC_CMDAT_BUSY (1 << 6) 1555 #define MSC_CMDAT_STREAM_BLOCK (1 << 5) 1556 #define MSC_CMDAT_WRITE (1 << 4) 1557 #define MSC_CMDAT_READ (0 << 4) 1558 #define MSC_CMDAT_DATA_EN (1 << 3) 1559 #define MSC_CMDAT_RESPONSE_BIT 0 1560 #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) 1561 #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) 1562 #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) 1563 #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) 1564 #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) 1565 #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) 1566 #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) 1567 #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) 1568 1569 /* MSC Interrupts Mask Register (MSC_IMASK) */ 1570 #define MSC_IMASK_SDIO (1 << 7) 1571 #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) 1572 #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) 1573 #define MSC_IMASK_END_CMD_RES (1 << 2) 1574 #define MSC_IMASK_PRG_DONE (1 << 1) 1575 #define MSC_IMASK_DATA_TRAN_DONE (1 << 0) 1576 1577 1578 /* MSC Interrupts Status Register (MSC_IREG) */ 1579 #define MSC_IREG_SDIO (1 << 7) 1580 #define MSC_IREG_TXFIFO_WR_REQ (1 << 6) 1581 #define MSC_IREG_RXFIFO_RD_REQ (1 << 5) 1582 #define MSC_IREG_END_CMD_RES (1 << 2) 1583 #define MSC_IREG_PRG_DONE (1 << 1) 1584 #define MSC_IREG_DATA_TRAN_DONE (1 << 0) 1585 1586 1587 /* 1588 * EMC (External Memory Controller) 1589 */ 1590 #define EMC_BCR (EMC_BASE + 0x0) /* BCR */ 1591 1592 #define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */ 1593 #define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */ 1594 #define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */ 1595 #define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */ 1596 #define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */ 1597 #define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */ 1598 #define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */ 1599 #define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */ 1600 #define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */ 1601 #define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */ 1602 1603 #define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */ 1604 #define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */ 1605 #define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */ 1606 #define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */ 1607 #define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */ 1608 #define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */ 1609 #define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */ 1610 #define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */ 1611 #define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */ 1612 #define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */ 1613 #define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */ 1614 #define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */ 1615 1616 #define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */ 1617 #define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */ 1618 #define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */ 1619 #define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */ 1620 #define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */ 1621 #define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */ 1622 1623 #define REG_EMC_BCR REG32(EMC_BCR) 1624 1625 #define REG_EMC_SMCR0 REG32(EMC_SMCR0) 1626 #define REG_EMC_SMCR1 REG32(EMC_SMCR1) 1627 #define REG_EMC_SMCR2 REG32(EMC_SMCR2) 1628 #define REG_EMC_SMCR3 REG32(EMC_SMCR3) 1629 #define REG_EMC_SMCR4 REG32(EMC_SMCR4) 1630 #define REG_EMC_SACR0 REG32(EMC_SACR0) 1631 #define REG_EMC_SACR1 REG32(EMC_SACR1) 1632 #define REG_EMC_SACR2 REG32(EMC_SACR2) 1633 #define REG_EMC_SACR3 REG32(EMC_SACR3) 1634 #define REG_EMC_SACR4 REG32(EMC_SACR4) 1635 1636 #define REG_EMC_NFCSR REG32(EMC_NFCSR) 1637 #define REG_EMC_NFECR REG32(EMC_NFECR) 1638 #define REG_EMC_NFECC REG32(EMC_NFECC) 1639 #define REG_EMC_NFPAR0 REG32(EMC_NFPAR0) 1640 #define REG_EMC_NFPAR1 REG32(EMC_NFPAR1) 1641 #define REG_EMC_NFPAR2 REG32(EMC_NFPAR2) 1642 #define REG_EMC_NFINTS REG32(EMC_NFINTS) 1643 #define REG_EMC_NFINTE REG32(EMC_NFINTE) 1644 #define REG_EMC_NFERR0 REG32(EMC_NFERR0) 1645 #define REG_EMC_NFERR1 REG32(EMC_NFERR1) 1646 #define REG_EMC_NFERR2 REG32(EMC_NFERR2) 1647 #define REG_EMC_NFERR3 REG32(EMC_NFERR3) 1648 1649 #define REG_EMC_DMCR REG32(EMC_DMCR) 1650 #define REG_EMC_RTCSR REG16(EMC_RTCSR) 1651 #define REG_EMC_RTCNT REG16(EMC_RTCNT) 1652 #define REG_EMC_RTCOR REG16(EMC_RTCOR) 1653 #define REG_EMC_DMAR0 REG32(EMC_DMAR0) 1654 1655 /* Static Memory Control Register */ 1656 #define EMC_SMCR_STRV_BIT 24 1657 #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) 1658 #define EMC_SMCR_TAW_BIT 20 1659 #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) 1660 #define EMC_SMCR_TBP_BIT 16 1661 #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) 1662 #define EMC_SMCR_TAH_BIT 12 1663 #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) 1664 #define EMC_SMCR_TAS_BIT 8 1665 #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) 1666 #define EMC_SMCR_BW_BIT 6 1667 #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) 1668 #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) 1669 #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) 1670 #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) 1671 #define EMC_SMCR_BCM (1 << 3) 1672 #define EMC_SMCR_BL_BIT 1 1673 #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) 1674 #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) 1675 #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) 1676 #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) 1677 #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) 1678 #define EMC_SMCR_SMT (1 << 0) 1679 1680 /* Static Memory Bank Addr Config Reg */ 1681 #define EMC_SACR_BASE_BIT 8 1682 #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) 1683 #define EMC_SACR_MASK_BIT 0 1684 #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) 1685 1686 /* NAND Flash Control/Status Register */ 1687 #define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ 1688 #define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ 1689 #define EMC_NFCSR_NFCE3 (1 << 5) 1690 #define EMC_NFCSR_NFE3 (1 << 4) 1691 #define EMC_NFCSR_NFCE2 (1 << 3) 1692 #define EMC_NFCSR_NFE2 (1 << 2) 1693 #define EMC_NFCSR_NFCE1 (1 << 1) 1694 #define EMC_NFCSR_NFE1 (1 << 0) 1695 1696 /* NAND Flash ECC Control Register */ 1697 #define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */ 1698 #define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */ 1699 #define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */ 1700 #define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */ 1701 #define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */ 1702 #define EMC_NFECR_ERST (1 << 1) /* ECC Reset */ 1703 #define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */ 1704 1705 /* NAND Flash ECC Data Register */ 1706 #define EMC_NFECC_ECC2_BIT 16 1707 #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) 1708 #define EMC_NFECC_ECC1_BIT 8 1709 #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) 1710 #define EMC_NFECC_ECC0_BIT 0 1711 #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) 1712 1713 /* NAND Flash Interrupt Status Register */ 1714 #define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */ 1715 #define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) 1716 #define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */ 1717 #define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */ 1718 #define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */ 1719 #define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */ 1720 #define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */ 1721 1722 /* NAND Flash Interrupt Enable Register */ 1723 #define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */ 1724 #define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */ 1725 #define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */ 1726 #define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */ 1727 #define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */ 1728 1729 /* NAND Flash RS Error Report Register */ 1730 #define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */ 1731 #define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT) 1732 #define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */ 1733 #define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT) 1734 1735 1736 /* DRAM Control Register */ 1737 #define EMC_DMCR_BW_BIT 31 1738 #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) 1739 #define EMC_DMCR_CA_BIT 26 1740 #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) 1741 #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) 1742 #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) 1743 #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) 1744 #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) 1745 #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) 1746 #define EMC_DMCR_RMODE (1 << 25) 1747 #define EMC_DMCR_RFSH (1 << 24) 1748 #define EMC_DMCR_MRSET (1 << 23) 1749 #define EMC_DMCR_RA_BIT 20 1750 #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) 1751 #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) 1752 #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) 1753 #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) 1754 #define EMC_DMCR_BA_BIT 19 1755 #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) 1756 #define EMC_DMCR_PDM (1 << 18) 1757 #define EMC_DMCR_EPIN (1 << 17) 1758 #define EMC_DMCR_TRAS_BIT 13 1759 #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) 1760 #define EMC_DMCR_RCD_BIT 11 1761 #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) 1762 #define EMC_DMCR_TPC_BIT 8 1763 #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) 1764 #define EMC_DMCR_TRWL_BIT 5 1765 #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) 1766 #define EMC_DMCR_TRC_BIT 2 1767 #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) 1768 #define EMC_DMCR_TCL_BIT 0 1769 #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) 1770 1771 /* Refresh Time Control/Status Register */ 1772 #define EMC_RTCSR_CMF (1 << 7) 1773 #define EMC_RTCSR_CKS_BIT 0 1774 #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) 1775 #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) 1776 #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) 1777 #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) 1778 #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) 1779 #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) 1780 #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) 1781 #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) 1782 #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) 1783 1784 /* SDRAM Bank Address Configuration Register */ 1785 #define EMC_DMAR_BASE_BIT 8 1786 #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) 1787 #define EMC_DMAR_MASK_BIT 0 1788 #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) 1789 1790 /* Mode Register of SDRAM bank 0 */ 1791 #define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ 1792 #define EMC_SDMR_OM_BIT 7 /* Operating Mode */ 1793 #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) 1794 #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) 1795 #define EMC_SDMR_CAS_BIT 4 /* CAS Latency */ 1796 #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) 1797 #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) 1798 #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) 1799 #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) 1800 #define EMC_SDMR_BT_BIT 3 /* Burst Type */ 1801 #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) 1802 #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */ 1803 #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */ 1804 #define EMC_SDMR_BL_BIT 0 /* Burst Length */ 1805 #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) 1806 #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) 1807 #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) 1808 #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) 1809 #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) 1810 1811 #define EMC_SDMR_CAS2_16BIT \ 1812 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) 1813 #define EMC_SDMR_CAS2_32BIT \ 1814 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) 1815 #define EMC_SDMR_CAS3_16BIT \ 1816 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) 1817 #define EMC_SDMR_CAS3_32BIT \ 1818 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) 1819 1820 /************************************************************************* 1821 * CIM 1822 *************************************************************************/ 1823 #define CIM_CFG (CIM_BASE + 0x0000) 1824 #define CIM_CTRL (CIM_BASE + 0x0004) 1825 #define CIM_STATE (CIM_BASE + 0x0008) 1826 #define CIM_IID (CIM_BASE + 0x000C) 1827 #define CIM_RXFIFO (CIM_BASE + 0x0010) 1828 #define CIM_DA (CIM_BASE + 0x0020) 1829 #define CIM_FA (CIM_BASE + 0x0024) 1830 #define CIM_FID (CIM_BASE + 0x0028) 1831 #define CIM_CMD (CIM_BASE + 0x002C) 1832 1833 #define REG_CIM_CFG REG32(CIM_CFG) 1834 #define REG_CIM_CTRL REG32(CIM_CTRL) 1835 #define REG_CIM_STATE REG32(CIM_STATE) 1836 #define REG_CIM_IID REG32(CIM_IID) 1837 #define REG_CIM_RXFIFO REG32(CIM_RXFIFO) 1838 #define REG_CIM_DA REG32(CIM_DA) 1839 #define REG_CIM_FA REG32(CIM_FA) 1840 #define REG_CIM_FID REG32(CIM_FID) 1841 #define REG_CIM_CMD REG32(CIM_CMD) 1842 1843 /* CIM Configuration Register (CIM_CFG) */ 1844 1845 #define CIM_CFG_INV_DAT (1 << 15) 1846 #define CIM_CFG_VSP (1 << 14) 1847 #define CIM_CFG_HSP (1 << 13) 1848 #define CIM_CFG_PCP (1 << 12) 1849 #define CIM_CFG_DUMMY_ZERO (1 << 9) 1850 #define CIM_CFG_EXT_VSYNC (1 << 8) 1851 #define CIM_CFG_PACK_BIT 4 1852 #define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) 1853 #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) 1854 #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) 1855 #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) 1856 #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) 1857 #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) 1858 #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) 1859 #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) 1860 #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) 1861 #define CIM_CFG_DSM_BIT 0 1862 #define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) 1863 #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ 1864 #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ 1865 #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ 1866 #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ 1867 1868 /* CIM Control Register (CIM_CTRL) */ 1869 1870 #define CIM_CTRL_MCLKDIV_BIT 24 1871 #define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) 1872 #define CIM_CTRL_FRC_BIT 16 1873 #define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) 1874 #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ 1875 #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ 1876 #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ 1877 #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ 1878 #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ 1879 #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ 1880 #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ 1881 #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ 1882 #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ 1883 #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ 1884 #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ 1885 #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ 1886 #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ 1887 #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ 1888 #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ 1889 #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ 1890 #define CIM_CTRL_VDDM (1 << 13) 1891 #define CIM_CTRL_DMA_SOFM (1 << 12) 1892 #define CIM_CTRL_DMA_EOFM (1 << 11) 1893 #define CIM_CTRL_DMA_STOPM (1 << 10) 1894 #define CIM_CTRL_RXF_TRIGM (1 << 9) 1895 #define CIM_CTRL_RXF_OFM (1 << 8) 1896 #define CIM_CTRL_RXF_TRIG_BIT 4 1897 #define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) 1898 #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ 1899 #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ 1900 #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ 1901 #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ 1902 #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ 1903 #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ 1904 #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ 1905 #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ 1906 #define CIM_CTRL_DMA_EN (1 << 2) 1907 #define CIM_CTRL_RXF_RST (1 << 1) 1908 #define CIM_CTRL_ENA (1 << 0) 1909 1910 /* CIM State Register (CIM_STATE) */ 1911 1912 #define CIM_STATE_DMA_SOF (1 << 6) 1913 #define CIM_STATE_DMA_EOF (1 << 5) 1914 #define CIM_STATE_DMA_STOP (1 << 4) 1915 #define CIM_STATE_RXF_OF (1 << 3) 1916 #define CIM_STATE_RXF_TRIG (1 << 2) 1917 #define CIM_STATE_RXF_EMPTY (1 << 1) 1918 #define CIM_STATE_VDD (1 << 0) 1919 1920 /* CIM DMA Command Register (CIM_CMD) */ 1921 1922 #define CIM_CMD_SOFINT (1 << 31) 1923 #define CIM_CMD_EOFINT (1 << 30) 1924 #define CIM_CMD_STOP (1 << 28) 1925 #define CIM_CMD_LEN_BIT 0 1926 #define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) 1927 1928 1929 /************************************************************************* 1930 * SADC (Smart A/D Controller) 1931 *************************************************************************/ 1932 1933 #define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */ 1934 #define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */ 1935 #define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */ 1936 #define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/ 1937 #define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */ 1938 #define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */ 1939 #define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */ 1940 #define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */ 1941 #define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */ 1942 1943 #define REG_SADC_ENA REG8(SADC_ENA) 1944 #define REG_SADC_CFG REG32(SADC_CFG) 1945 #define REG_SADC_CTRL REG8(SADC_CTRL) 1946 #define REG_SADC_STATE REG8(SADC_STATE) 1947 #define REG_SADC_SAMETIME REG16(SADC_SAMETIME) 1948 #define REG_SADC_WAITTIME REG16(SADC_WAITTIME) 1949 #define REG_SADC_TSDAT REG32(SADC_TSDAT) 1950 #define REG_SADC_BATDAT REG16(SADC_BATDAT) 1951 #define REG_SADC_SADDAT REG16(SADC_SADDAT) 1952 1953 /* ADC Enable Register */ 1954 #define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */ 1955 #define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */ 1956 #define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */ 1957 #define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */ 1958 1959 /* ADC Configure Register */ 1960 #define SADC_CFG_CLKOUT_NUM_BIT 16 1961 #define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT) 1962 #define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */ 1963 #define SADC_CFG_XYZ_BIT 13 /* XYZ selection */ 1964 #define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT) 1965 #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT) 1966 #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT) 1967 #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT) 1968 #define SADC_CFG_SNUM_BIT 10 /* Sample Number */ 1969 #define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT) 1970 #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT) 1971 #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT) 1972 #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT) 1973 #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT) 1974 #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT) 1975 #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT) 1976 #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT) 1977 #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT) 1978 #define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */ 1979 #define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT) 1980 #define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */ 1981 #define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */ 1982 #define SADC_CFG_CMD_BIT 0 /* ADC Command */ 1983 #define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT) 1984 #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */ 1985 #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */ 1986 #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */ 1987 #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */ 1988 #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */ 1989 #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */ 1990 #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */ 1991 #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */ 1992 #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */ 1993 #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */ 1994 #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */ 1995 #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */ 1996 #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */ 1997 1998 /* ADC Control Register */ 1999 #define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */ 2000 #define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */ 2001 #define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */ 2002 #define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */ 2003 #define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */ 2004 2005 /* ADC Status Register */ 2006 #define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */ 2007 #define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */ 2008 #define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */ 2009 #define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */ 2010 #define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */ 2011 #define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */ 2012 #define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */ 2013 #define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */ 2014 2015 /* ADC Touch Screen Data Register */ 2016 #define SADC_TSDAT_DATA0_BIT 0 2017 #define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT) 2018 #define SADC_TSDAT_TYPE0 (1 << 15) 2019 #define SADC_TSDAT_DATA1_BIT 16 2020 #define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT) 2021 #define SADC_TSDAT_TYPE1 (1 << 31) 2022 2023 2024 /************************************************************************* 2025 * SLCD (Smart LCD Controller) 2026 *************************************************************************/ 2027 2028 #define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */ 2029 #define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */ 2030 #define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */ 2031 #define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */ 2032 #define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */ 2033 2034 #define REG_SLCD_CFG REG32(SLCD_CFG) 2035 #define REG_SLCD_CTRL REG8(SLCD_CTRL) 2036 #define REG_SLCD_STATE REG8(SLCD_STATE) 2037 #define REG_SLCD_DATA REG32(SLCD_DATA) 2038 #define REG_SLCD_FIFO REG32(SLCD_FIFO) 2039 2040 /* SLCD Configure Register */ 2041 #define SLCD_CFG_BURST_BIT 14 2042 #define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT) 2043 #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT) 2044 #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT) 2045 #define SLCD_CFG_DWIDTH_BIT 10 2046 #define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT) 2047 #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT) 2048 #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT) 2049 #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT) 2050 #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT) 2051 #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT) 2052 #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT) 2053 #define SLCD_CFG_CWIDTH_16BIT (0 << 8) 2054 #define SLCD_CFG_CWIDTH_8BIT (1 << 8) 2055 #define SLCD_CFG_CWIDTH_18BIT (2 << 8) 2056 #define SLCD_CFG_CS_ACTIVE_LOW (0 << 4) 2057 #define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4) 2058 #define SLCD_CFG_RS_CMD_LOW (0 << 3) 2059 #define SLCD_CFG_RS_CMD_HIGH (1 << 3) 2060 #define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1) 2061 #define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1) 2062 #define SLCD_CFG_TYPE_PARALLEL (0 << 0) 2063 #define SLCD_CFG_TYPE_SERIAL (1 << 0) 2064 2065 /* SLCD Control Register */ 2066 #define SLCD_CTRL_DMA_EN (1 << 0) 2067 2068 /* SLCD Status Register */ 2069 #define SLCD_STATE_BUSY (1 << 0) 2070 2071 /* SLCD Data Register */ 2072 #define SLCD_DATA_RS_DATA (0 << 31) 2073 #define SLCD_DATA_RS_COMMAND (1 << 31) 2074 2075 /* SLCD FIFO Register */ 2076 #define SLCD_FIFO_RS_DATA (0 << 31) 2077 #define SLCD_FIFO_RS_COMMAND (1 << 31) 2078 2079 2080 /************************************************************************* 2081 * LCD (LCD Controller) 2082 *************************************************************************/ 2083 2084 /* Register definitions with absolute positioning have been removed. */ 2085 2086 /* LCD Configure Register */ 2087 #define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */ 2088 #define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT) 2089 #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT) 2090 #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT) 2091 #define LCD_CFG_PSM (1 << 23) /* PS signal mode */ 2092 #define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */ 2093 #define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */ 2094 #define LCD_CFG_REVM (1 << 20) /* REV signal mode */ 2095 #define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */ 2096 #define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */ 2097 #define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */ 2098 #define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */ 2099 #define LCD_CFG_PSP (1 << 15) /* PS pin reset state */ 2100 #define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */ 2101 #define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */ 2102 #define LCD_CFG_REVP (1 << 12) /* REV pin reset state */ 2103 #define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */ 2104 #define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */ 2105 #define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */ 2106 #define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */ 2107 #define LCD_CFG_PDW_BIT 4 /* STN pins utilization */ 2108 #define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT) 2109 #define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */ 2110 #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */ 2111 #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */ 2112 #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */ 2113 #define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */ 2114 #define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT) 2115 #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */ 2116 #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT) 2117 #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT) 2118 #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT) 2119 #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT) 2120 #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT) 2121 #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT) 2122 #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT) 2123 #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT) 2124 #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT) 2125 #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT) 2126 #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT) 2127 /* JZ47XX defines */ 2128 #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT) 2129 #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT) 2130 #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT) 2131 2132 2133 2134 /* Vertical Synchronize Register */ 2135 #define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */ 2136 #define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) 2137 #define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */ 2138 #define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) 2139 2140 /* Horizontal Synchronize Register */ 2141 #define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */ 2142 #define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) 2143 #define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */ 2144 #define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) 2145 2146 /* Virtual Area Setting Register */ 2147 #define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */ 2148 #define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) 2149 #define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */ 2150 #define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) 2151 2152 /* Display Area Horizontal Start/End Point Register */ 2153 #define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */ 2154 #define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) 2155 #define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */ 2156 #define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) 2157 2158 /* Display Area Vertical Start/End Point Register */ 2159 #define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */ 2160 #define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) 2161 #define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */ 2162 #define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) 2163 2164 /* PS Signal Setting */ 2165 #define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */ 2166 #define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT) 2167 #define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */ 2168 #define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT) 2169 2170 /* CLS Signal Setting */ 2171 #define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */ 2172 #define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT) 2173 #define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */ 2174 #define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT) 2175 2176 /* SPL Signal Setting */ 2177 #define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */ 2178 #define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT) 2179 #define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */ 2180 #define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT) 2181 2182 /* REV Signal Setting */ 2183 #define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */ 2184 #define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT) 2185 2186 /* LCD Control Register */ 2187 #define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */ 2188 #define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) 2189 #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */ 2190 #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */ 2191 #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */ 2192 #define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */ 2193 #define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */ 2194 #define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */ 2195 #define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */ 2196 #define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) 2197 #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */ 2198 #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */ 2199 #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */ 2200 #define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */ 2201 #define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) 2202 #define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */ 2203 #define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */ 2204 #define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */ 2205 #define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */ 2206 #define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */ 2207 #define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */ 2208 #define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */ 2209 #define LCD_CTRL_BEDN (1 << 6) /* Endian selection */ 2210 #define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */ 2211 #define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */ 2212 #define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */ 2213 #define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */ 2214 #define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) 2215 #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */ 2216 #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */ 2217 #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */ 2218 #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */ 2219 #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */ 2220 #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */ 2221 2222 /* LCD Status Register */ 2223 #define LCD_STATE_QD (1 << 7) /* Quick Disable Done */ 2224 #define LCD_STATE_EOF (1 << 5) /* EOF Flag */ 2225 #define LCD_STATE_SOF (1 << 4) /* SOF Flag */ 2226 #define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */ 2227 #define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */ 2228 #define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */ 2229 #define LCD_STATE_LDD (1 << 0) /* LCD Disabled */ 2230 2231 /* DMA Command Register */ 2232 #define LCD_CMD_SOFINT (1 << 31) 2233 #define LCD_CMD_EOFINT (1 << 30) 2234 #define LCD_CMD_PAL (1 << 28) 2235 #define LCD_CMD_LEN_BIT 0 2236 #define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) 2237 2238 2239 /************************************************************************* 2240 * USB Device 2241 *************************************************************************/ 2242 #define USB_BASE UDC_BASE 2243 2244 #define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */ 2245 #define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */ 2246 #define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */ 2247 #define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */ 2248 #define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */ 2249 #define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */ 2250 #define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */ 2251 #define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */ 2252 #define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */ 2253 #define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */ 2254 #define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */ 2255 2256 #define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */ 2257 #define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */ 2258 #define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */ 2259 #define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */ 2260 #define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */ 2261 #define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */ 2262 #define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */ 2263 #define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */ 2264 2265 #define USB_FIFO_EP0 (USB_BASE + 0x20) 2266 #define USB_FIFO_EP1 (USB_BASE + 0x24) 2267 #define USB_FIFO_EP2 (USB_BASE + 0x28) 2268 2269 #define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */ 2270 #define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */ 2271 2272 #define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */ 2273 #define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */ 2274 #define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */ 2275 #define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */ 2276 #define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */ 2277 #define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */ 2278 #define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */ 2279 2280 2281 /* Power register bit masks */ 2282 #define USB_POWER_SUSPENDM 0x01 2283 #define USB_POWER_RESUME 0x04 2284 #define USB_POWER_HSMODE 0x10 2285 #define USB_POWER_HSENAB 0x20 2286 #define USB_POWER_SOFTCONN 0x40 2287 2288 /* Interrupt register bit masks */ 2289 #define USB_INTR_SUSPEND 0x01 2290 #define USB_INTR_RESUME 0x02 2291 #define USB_INTR_RESET 0x04 2292 2293 #define USB_INTR_EP0 0x0001 2294 #define USB_INTR_INEP1 0x0002 2295 #define USB_INTR_INEP2 0x0004 2296 #define USB_INTR_OUTEP1 0x0002 2297 2298 /* CSR0 bit masks */ 2299 #define USB_CSR0_OUTPKTRDY 0x01 2300 #define USB_CSR0_INPKTRDY 0x02 2301 #define USB_CSR0_SENTSTALL 0x04 2302 #define USB_CSR0_DATAEND 0x08 2303 #define USB_CSR0_SETUPEND 0x10 2304 #define USB_CSR0_SENDSTALL 0x20 2305 #define USB_CSR0_SVDOUTPKTRDY 0x40 2306 #define USB_CSR0_SVDSETUPEND 0x80 2307 2308 /* Endpoint CSR register bits */ 2309 #define USB_INCSRH_AUTOSET 0x80 2310 #define USB_INCSRH_ISO 0x40 2311 #define USB_INCSRH_MODE 0x20 2312 #define USB_INCSRH_DMAREQENAB 0x10 2313 #define USB_INCSRH_DMAREQMODE 0x04 2314 #define USB_INCSR_CDT 0x40 2315 #define USB_INCSR_SENTSTALL 0x20 2316 #define USB_INCSR_SENDSTALL 0x10 2317 #define USB_INCSR_FF 0x08 2318 #define USB_INCSR_UNDERRUN 0x04 2319 #define USB_INCSR_FFNOTEMPT 0x02 2320 #define USB_INCSR_INPKTRDY 0x01 2321 #define USB_OUTCSRH_AUTOCLR 0x80 2322 #define USB_OUTCSRH_ISO 0x40 2323 #define USB_OUTCSRH_DMAREQENAB 0x20 2324 #define USB_OUTCSRH_DNYT 0x10 2325 #define USB_OUTCSRH_DMAREQMODE 0x08 2326 #define USB_OUTCSR_CDT 0x80 2327 #define USB_OUTCSR_SENTSTALL 0x40 2328 #define USB_OUTCSR_SENDSTALL 0x20 2329 #define USB_OUTCSR_FF 0x10 2330 #define USB_OUTCSR_DATAERR 0x08 2331 #define USB_OUTCSR_OVERRUN 0x04 2332 #define USB_OUTCSR_FFFULL 0x02 2333 #define USB_OUTCSR_OUTPKTRDY 0x01 2334 2335 /* Testmode register bits */ 2336 #define USB_TEST_SE0NAK 0x01 2337 #define USB_TEST_J 0x02 2338 #define USB_TEST_K 0x04 2339 #define USB_TEST_PACKET 0x08 2340 2341 /* DMA control bits */ 2342 #define USB_CNTL_ENA 0x01 2343 #define USB_CNTL_DIR_IN 0x02 2344 #define USB_CNTL_MODE_1 0x04 2345 #define USB_CNTL_INTR_EN 0x08 2346 #define USB_CNTL_EP(n) ((n) << 4) 2347 #define USB_CNTL_BURST_0 (0 << 9) 2348 #define USB_CNTL_BURST_4 (1 << 9) 2349 #define USB_CNTL_BURST_8 (2 << 9) 2350 #define USB_CNTL_BURST_16 (3 << 9) 2351 2352 2353 2354 /* Module Operation Definitions */ 2355 #ifndef __ASSEMBLY__ 2356 2357 2358 /* GPIO Pins Description */ 2359 /* PORT 0: */ 2360 /* PIN/BIT N FUNC0 FUNC1 */ 2361 /* 0 D0 - */ 2362 /* 1 D1 - */ 2363 /* 2 D2 - */ 2364 /* 3 D3 - */ 2365 /* 4 D4 - */ 2366 /* 5 D5 - */ 2367 /* 6 D6 - */ 2368 /* 7 D7 - */ 2369 /* 8 D8 - */ 2370 /* 9 D9 - */ 2371 /* 10 D10 - */ 2372 /* 11 D11 - */ 2373 /* 12 D12 - */ 2374 /* 13 D13 - */ 2375 /* 14 D14 - */ 2376 /* 15 D15 - */ 2377 /* 16 D16 - */ 2378 /* 17 D17 - */ 2379 /* 18 D18 - */ 2380 /* 19 D19 - */ 2381 /* 20 D20 - */ 2382 /* 21 D21 - */ 2383 /* 22 D22 - */ 2384 /* 23 D23 - */ 2385 /* 24 D24 - */ 2386 /* 25 D25 - */ 2387 /* 26 D26 - */ 2388 /* 27 D27 - */ 2389 /* 28 D28 - */ 2390 /* 29 D29 - */ 2391 /* 30 D30 - */ 2392 /* 31 D31 - */ 2393 /*------------------------------------------------------ */ 2394 /* PORT 1: */ 2395 /* */ 2396 /* PIN/BIT N FUNC0 FUNC1 */ 2397 /* 0 A0 - */ 2398 /* 1 A1 - */ 2399 /* 2 A2 - */ 2400 /* 3 A3 - */ 2401 /* 4 A4 - */ 2402 /* 5 A5 - */ 2403 /* 6 A6 - */ 2404 /* 7 A7 - */ 2405 /* 8 A8 - */ 2406 /* 9 A9 - */ 2407 /* 10 A10 - */ 2408 /* 11 A11 - */ 2409 /* 12 A12 - */ 2410 /* 13 A13 - */ 2411 /* 14 A14 - */ 2412 /* 15 A15/CL - */ 2413 /* 16 A16/AL - */ 2414 /* 17 LCD_CLS A21 */ 2415 /* 18 LCD_SPL A22 */ 2416 /* 19 DCS# - */ 2417 /* 20 RAS# - */ 2418 /* 21 CAS# - */ 2419 /* 22 RDWE#/BUFD# - */ 2420 /* 23 CKE - */ 2421 /* 24 CKO - */ 2422 /* 25 CS1# - */ 2423 /* 26 CS2# - */ 2424 /* 27 CS3# - */ 2425 /* 28 CS4# - */ 2426 /* 29 RD# - */ 2427 /* 30 WR# - */ 2428 /* 31 WE0# - */ 2429 /* Note: PIN15&16 are CL&AL when connecting to NAND flash. */ 2430 /*------------------------------------------------------ */ 2431 /* PORT 2: */ 2432 /* */ 2433 /* PIN/BIT N FUNC0 FUNC1 */ 2434 /* 0 LCD_D0 - */ 2435 /* 1 LCD_D1 - */ 2436 /* 2 LCD_D2 - */ 2437 /* 3 LCD_D3 - */ 2438 /* 4 LCD_D4 - */ 2439 /* 5 LCD_D5 - */ 2440 /* 6 LCD_D6 - */ 2441 /* 7 LCD_D7 - */ 2442 /* 8 LCD_D8 - */ 2443 /* 9 LCD_D9 - */ 2444 /* 10 LCD_D10 - */ 2445 /* 11 LCD_D11 - */ 2446 /* 12 LCD_D12 - */ 2447 /* 13 LCD_D13 - */ 2448 /* 14 LCD_D14 - */ 2449 /* 15 LCD_D15 - */ 2450 /* 16 LCD_D16 - */ 2451 /* 17 LCD_D17 - */ 2452 /* 18 LCD_PCLK - */ 2453 /* 19 LCD_HSYNC - */ 2454 /* 20 LCD_VSYNC - */ 2455 /* 21 LCD_DE - */ 2456 /* 22 LCD_PS A19 */ 2457 /* 23 LCD_REV A20 */ 2458 /* 24 WE1# - */ 2459 /* 25 WE2# - */ 2460 /* 26 WE3# - */ 2461 /* 27 WAIT# - */ 2462 /* 28 FRE# - */ 2463 /* 29 FWE# - */ 2464 /* 30(NOTE:FRB#) - - */ 2465 /* 31 - - */ 2466 /* NOTE(1): PIN30 is used for FRB# when connecting to NAND flash. */ 2467 /*------------------------------------------------------ */ 2468 /* PORT 3: */ 2469 /* */ 2470 /* PIN/BIT N FUNC0 FUNC1 */ 2471 /* 0 CIM_D0 - */ 2472 /* 1 CIM_D1 - */ 2473 /* 2 CIM_D2 - */ 2474 /* 3 CIM_D3 - */ 2475 /* 4 CIM_D4 - */ 2476 /* 5 CIM_D5 - */ 2477 /* 6 CIM_D6 - */ 2478 /* 7 CIM_D7 - */ 2479 /* 8 MSC_CMD - */ 2480 /* 9 MSC_CLK - */ 2481 /* 10 MSC_D0 - */ 2482 /* 11 MSC_D1 - */ 2483 /* 12 MSC_D2 - */ 2484 /* 13 MSC_D3 - */ 2485 /* 14 CIM_MCLK - */ 2486 /* 15 CIM_PCLK - */ 2487 /* 16 CIM_VSYNC - */ 2488 /* 17 CIM_HSYNC - */ 2489 /* 18 SSI_CLK SCLK_RSTN */ 2490 /* 19 SSI_CE0# BIT_CLK(AIC) */ 2491 /* 20 SSI_DT SDATA_OUT(AIC) */ 2492 /* 21 SSI_DR SDATA_IN(AIC) */ 2493 /* 22 SSI_CE1#&GPC SYNC(AIC) */ 2494 /* 23 PWM0 I2C_SDA */ 2495 /* 24 PWM1 I2C_SCK */ 2496 /* 25 PWM2 UART0_TxD */ 2497 /* 26 PWM3 UART0_RxD */ 2498 /* 27 PWM4 A17 */ 2499 /* 28 PWM5 A18 */ 2500 /* 29 - - */ 2501 /* 30 PWM6 UART0_CTS/UART1_RxD */ 2502 /* 31 PWM7 UART0_RTS/UART1_TxD */ 2503 /* 2504 * p is the port number (0,1,2,3) 2505 * o is the pin offset (0-31) inside the port 2506 * n is the absolute number of a pin (0-127), regardless of the port 2507 */ 2508 2509 /* Function Pins Mode */ 2510 2511 #define __gpio_as_func0(n) \ 2512 do { \ 2513 unsigned int p, o; \ 2514 p = (n) / 32; \ 2515 o = (n) % 32; \ 2516 REG_GPIO_PXFUNS(p) = (1 << o); \ 2517 REG_GPIO_PXSELC(p) = (1 << o); \ 2518 } while (0) 2519 2520 #define __gpio_as_func1(n) \ 2521 do { \ 2522 unsigned int p, o; \ 2523 p = (n) / 32; \ 2524 o = (n) % 32; \ 2525 REG_GPIO_PXFUNS(p) = (1 << o); \ 2526 REG_GPIO_PXSELS(p) = (1 << o); \ 2527 } while (0) 2528 2529 /* 2530 * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, 2531 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# 2532 */ 2533 #define __gpio_as_sdram_32bit() \ 2534 do { \ 2535 REG_GPIO_PXFUNS(0) = 0xffffffff; \ 2536 REG_GPIO_PXSELC(0) = 0xffffffff; \ 2537 REG_GPIO_PXPES(0) = 0xffffffff; \ 2538 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ 2539 REG_GPIO_PXSELC(1) = 0x81f9ffff; \ 2540 REG_GPIO_PXPES(1) = 0x81f9ffff; \ 2541 REG_GPIO_PXFUNS(2) = 0x07000000; \ 2542 REG_GPIO_PXSELC(2) = 0x07000000; \ 2543 REG_GPIO_PXPES(2) = 0x07000000; \ 2544 } while (0) 2545 2546 /* 2547 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, 2548 * RDWE#, CKO#, WE0#, WE1# 2549 */ 2550 #define __gpio_as_sdram_16bit_4720() \ 2551 do { \ 2552 REG_GPIO_PXFUNS(0) = 0x5442bfaa; \ 2553 REG_GPIO_PXSELC(0) = 0x5442bfaa; \ 2554 REG_GPIO_PXPES(0) = 0x5442bfaa; \ 2555 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ 2556 REG_GPIO_PXSELC(1) = 0x81f9ffff; \ 2557 REG_GPIO_PXPES(1) = 0x81f9ffff; \ 2558 REG_GPIO_PXFUNS(2) = 0x01000000; \ 2559 REG_GPIO_PXSELC(2) = 0x01000000; \ 2560 REG_GPIO_PXPES(2) = 0x01000000; \ 2561 } while (0) 2562 2563 /* 2564 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, 2565 * RDWE#, CKO#, WE0#, WE1# 2566 */ 2567 #define __gpio_as_sdram_16bit_4725() \ 2568 do { \ 2569 REG_GPIO_PXFUNS(0) = 0x0000ffff; \ 2570 REG_GPIO_PXSELC(0) = 0x0000ffff; \ 2571 REG_GPIO_PXPES(0) = 0x0000ffff; \ 2572 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ 2573 REG_GPIO_PXSELC(1) = 0x81f9ffff; \ 2574 REG_GPIO_PXPES(1) = 0x81f9ffff; \ 2575 REG_GPIO_PXFUNS(2) = 0x01000000; \ 2576 REG_GPIO_PXSELC(2) = 0x01000000; \ 2577 REG_GPIO_PXPES(2) = 0x01000000; \ 2578 } while (0) 2579 2580 2581 /* 2582 * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD# 2583 */ 2584 #define __gpio_as_nand() \ 2585 do { \ 2586 REG_GPIO_PXFUNS(1) = 0x02018000; \ 2587 REG_GPIO_PXSELC(1) = 0x02018000; \ 2588 REG_GPIO_PXPES(1) = 0x02018000; \ 2589 REG_GPIO_PXFUNS(2) = 0x30000000; \ 2590 REG_GPIO_PXSELC(2) = 0x30000000; \ 2591 REG_GPIO_PXPES(2) = 0x30000000; \ 2592 REG_GPIO_PXFUNC(2) = 0x40000000; \ 2593 REG_GPIO_PXSELC(2) = 0x40000000; \ 2594 REG_GPIO_PXDIRC(2) = 0x40000000; \ 2595 REG_GPIO_PXPES(2) = 0x40000000; \ 2596 REG_GPIO_PXFUNS(1) = 0x00400000; \ 2597 REG_GPIO_PXSELC(1) = 0x00400000; \ 2598 } while (0) 2599 2600 /* 2601 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7 2602 */ 2603 #define __gpio_as_nor_8bit() \ 2604 do { \ 2605 REG_GPIO_PXFUNS(0) = 0x000000ff; \ 2606 REG_GPIO_PXSELC(0) = 0x000000ff; \ 2607 REG_GPIO_PXPES(0) = 0x000000ff; \ 2608 REG_GPIO_PXFUNS(1) = 0x7041ffff; \ 2609 REG_GPIO_PXSELC(1) = 0x7041ffff; \ 2610 REG_GPIO_PXPES(1) = 0x7041ffff; \ 2611 REG_GPIO_PXFUNS(1) = 0x00060000; \ 2612 REG_GPIO_PXSELS(1) = 0x00060000; \ 2613 REG_GPIO_PXPES(1) = 0x00060000; \ 2614 REG_GPIO_PXFUNS(2) = 0x08000000; \ 2615 REG_GPIO_PXSELC(2) = 0x08000000; \ 2616 REG_GPIO_PXPES(2) = 0x08000000; \ 2617 REG_GPIO_PXFUNS(2) = 0x00c00000; \ 2618 REG_GPIO_PXSELS(2) = 0x00c00000; \ 2619 REG_GPIO_PXPES(2) = 0x00c00000; \ 2620 REG_GPIO_PXFUNS(3) = 0x18000000; \ 2621 REG_GPIO_PXSELS(3) = 0x18000000; \ 2622 REG_GPIO_PXPES(3) = 0x18000000; \ 2623 } while (0) 2624 2625 /* 2626 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15 2627 */ 2628 #define __gpio_as_nor_16bit() \ 2629 do { \ 2630 REG_GPIO_PXFUNS(0) = 0x0000ffff; \ 2631 REG_GPIO_PXSELC(0) = 0x0000ffff; \ 2632 REG_GPIO_PXPES(0) = 0x0000ffff; \ 2633 REG_GPIO_PXFUNS(1) = 0x7041ffff; \ 2634 REG_GPIO_PXSELC(1) = 0x7041ffff; \ 2635 REG_GPIO_PXPES(1) = 0x7041ffff; \ 2636 REG_GPIO_PXFUNS(1) = 0x00060000; \ 2637 REG_GPIO_PXSELS(1) = 0x00060000; \ 2638 REG_GPIO_PXPES(1) = 0x00060000; \ 2639 REG_GPIO_PXFUNS(2) = 0x08000000; \ 2640 REG_GPIO_PXSELC(2) = 0x08000000; \ 2641 REG_GPIO_PXPES(2) = 0x08000000; \ 2642 REG_GPIO_PXFUNS(2) = 0x00c00000; \ 2643 REG_GPIO_PXSELS(2) = 0x00c00000; \ 2644 REG_GPIO_PXPES(2) = 0x00c00000; \ 2645 REG_GPIO_PXFUNS(3) = 0x18000000; \ 2646 REG_GPIO_PXSELS(3) = 0x18000000; \ 2647 REG_GPIO_PXPES(3) = 0x18000000; \ 2648 } while (0) 2649 2650 /* 2651 * UART0_TxD, UART_RxD0 2652 */ 2653 #define __gpio_as_uart0() \ 2654 do { \ 2655 REG_GPIO_PXFUNS(3) = 0x06000000; \ 2656 REG_GPIO_PXSELS(3) = 0x06000000; \ 2657 REG_GPIO_PXPES(3) = 0x06000000; \ 2658 } while (0) 2659 2660 #define __gpio_jtag_to_uart0() \ 2661 do { \ 2662 REG_GPIO_PXSELS(2) = 0x80000000; \ 2663 } while (0) 2664 2665 /* 2666 * UART0_CTS, UART0_RTS 2667 */ 2668 #define __gpio_as_ctsrts() \ 2669 do { \ 2670 REG_GPIO_PXFUNS(3) = 0xc0000000; \ 2671 REG_GPIO_PXSELS(3) = 0xc0000000; \ 2672 REG_GPIO_PXTRGC(3) = 0xc0000000; \ 2673 REG_GPIO_PXPES(3) = 0xc0000000; \ 2674 } while (0) 2675 2676 /* 2677 * UART1_TxD, UART1_RxD1 2678 */ 2679 #define __gpio_as_uart1() \ 2680 do { \ 2681 REG_GPIO_PXFUNS(3) = 0xc0000000; \ 2682 REG_GPIO_PXSELC(3) = 0xc0000000; \ 2683 REG_GPIO_PXTRGS(3) = 0xc0000000; \ 2684 REG_GPIO_PXPES(3) = 0xc0000000; \ 2685 } while (0) 2686 2687 /* 2688 * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE 2689 */ 2690 #define __gpio_as_lcd_16bit() \ 2691 do { \ 2692 REG_GPIO_PXFUNS(2) = 0x003cffff; \ 2693 REG_GPIO_PXSELC(2) = 0x003cffff; \ 2694 REG_GPIO_PXPES(2) = 0x003cffff; \ 2695 } while (0) 2696 2697 /* 2698 * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE 2699 */ 2700 #define __gpio_as_lcd_18bit() \ 2701 do { \ 2702 REG_GPIO_PXFUNS(2) = 0x003fffff; \ 2703 REG_GPIO_PXSELC(2) = 0x003fffff; \ 2704 REG_GPIO_PXPES(2) = 0x003fffff; \ 2705 } while (0) 2706 2707 2708 /* LCD_D0~LCD_D7, SLCD_CLK, SLCD_RS, SLCD_CS, LCD_DE */ 2709 #define __gpio_as_slcd_8bit() \ 2710 do { \ 2711 REG_GPIO_PXFUNS(2) = 0x003c00ff; \ 2712 REG_GPIO_PXSELC(2) = 0x003c00ff; \ 2713 } while (0) 2714 2715 /* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */ 2716 #define __gpio_as_slcd_9bit() \ 2717 do { \ 2718 REG_GPIO_PXFUNS(2) = 0x001801ff; \ 2719 REG_GPIO_PXSELC(2) = 0x001801ff; \ 2720 } while (0) 2721 2722 /* LCD_D0~LCD_D15, SLCD_RS, SLCD_CS */ 2723 #define __gpio_as_slcd_16bit() \ 2724 do { \ 2725 REG_GPIO_PXFUNS(2) = 0x0018ffff; \ 2726 REG_GPIO_PXSELC(2) = 0x0018ffff; \ 2727 } while (0) 2728 2729 /* LCD_D0~LCD_D17, SLCD_RS, SLCD_CS */ 2730 #define __gpio_as_slcd_18bit() \ 2731 do { \ 2732 REG_GPIO_PXFUNS(2) = 0x001bffff; \ 2733 REG_GPIO_PXSELC(2) = 0x001bffff; \ 2734 } while (0) 2735 /* 2736 * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC 2737 */ 2738 #define __gpio_as_cim() \ 2739 do { \ 2740 REG_GPIO_PXFUNS(3) = 0x0003c0ff; \ 2741 REG_GPIO_PXSELC(3) = 0x0003c0ff; \ 2742 REG_GPIO_PXPES(3) = 0x0003c0ff; \ 2743 } while (0) 2744 2745 /* 2746 * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET 2747 */ 2748 #define __gpio_as_aic() \ 2749 do { \ 2750 REG_GPIO_PXFUNS(3) = 0x007c0000; \ 2751 REG_GPIO_PXSELS(3) = 0x007c0000; \ 2752 REG_GPIO_PXPES(3) = 0x007c0000; \ 2753 } while (0) 2754 2755 /* 2756 * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 2757 */ 2758 #define __gpio_as_msc() \ 2759 do { \ 2760 REG_GPIO_PXFUNS(3) = 0x00003f00; \ 2761 REG_GPIO_PXSELC(3) = 0x00003f00; \ 2762 REG_GPIO_PXPES(3) = 0x00003f00; \ 2763 } while (0) 2764 2765 /* 2766 * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR 2767 */ 2768 #define __gpio_as_ssi() \ 2769 do { \ 2770 REG_GPIO_PXFUNS(3) = 0x003c0000; \ 2771 REG_GPIO_PXSELC(3) = 0x003c0000; \ 2772 REG_GPIO_PXPES(3) = 0x003c0000; \ 2773 } while (0) 2774 2775 /* 2776 * I2C_SCK, I2C_SDA 2777 */ 2778 #define __gpio_as_i2c() \ 2779 do { \ 2780 REG_GPIO_PXFUNS(3) = 0x01800000; \ 2781 REG_GPIO_PXSELS(3) = 0x01800000; \ 2782 REG_GPIO_PXPES(3) = 0x01800000; \ 2783 } while (0) 2784 2785 /* 2786 * PWM0 2787 */ 2788 #define __gpio_as_pwm0() \ 2789 do { \ 2790 REG_GPIO_PXFUNS(3) = 0x00800000; \ 2791 REG_GPIO_PXSELC(3) = 0x00800000; \ 2792 REG_GPIO_PXPES(3) = 0x00800000; \ 2793 } while (0) 2794 2795 /* 2796 * PWM1 2797 */ 2798 #define __gpio_as_pwm1() \ 2799 do { \ 2800 REG_GPIO_PXFUNS(3) = 0x01000000; \ 2801 REG_GPIO_PXSELC(3) = 0x01000000; \ 2802 REG_GPIO_PXPES(3) = 0x01000000; \ 2803 } while (0) 2804 2805 /* 2806 * PWM2 2807 */ 2808 #define __gpio_as_pwm2() \ 2809 do { \ 2810 REG_GPIO_PXFUNS(3) = 0x02000000; \ 2811 REG_GPIO_PXSELC(3) = 0x02000000; \ 2812 REG_GPIO_PXPES(3) = 0x02000000; \ 2813 } while (0) 2814 2815 /* 2816 * PWM3 2817 */ 2818 #define __gpio_as_pwm3() \ 2819 do { \ 2820 REG_GPIO_PXFUNS(3) = 0x04000000; \ 2821 REG_GPIO_PXSELC(3) = 0x04000000; \ 2822 REG_GPIO_PXPES(3) = 0x04000000; \ 2823 } while (0) 2824 2825 /* 2826 * PWM4 2827 */ 2828 #define __gpio_as_pwm4() \ 2829 do { \ 2830 REG_GPIO_PXFUNS(3) = 0x08000000; \ 2831 REG_GPIO_PXSELC(3) = 0x08000000; \ 2832 REG_GPIO_PXPES(3) = 0x08000000; \ 2833 } while (0) 2834 2835 /* 2836 * PWM5 2837 */ 2838 #define __gpio_as_pwm5() \ 2839 do { \ 2840 REG_GPIO_PXFUNS(3) = 0x10000000; \ 2841 REG_GPIO_PXSELC(3) = 0x10000000; \ 2842 REG_GPIO_PXPES(3) = 0x10000000; \ 2843 } while (0) 2844 2845 /* 2846 * PWM6 2847 */ 2848 #define __gpio_as_pwm6() \ 2849 do { \ 2850 REG_GPIO_PXFUNS(3) = 0x40000000; \ 2851 REG_GPIO_PXSELC(3) = 0x40000000; \ 2852 REG_GPIO_PXPES(3) = 0x40000000; \ 2853 } while (0) 2854 2855 /* 2856 * PWM7 2857 */ 2858 #define __gpio_as_pwm7() \ 2859 do { \ 2860 REG_GPIO_PXFUNS(3) = 0x80000000; \ 2861 REG_GPIO_PXSELC(3) = 0x80000000; \ 2862 REG_GPIO_PXPES(3) = 0x80000000; \ 2863 } while (0) 2864 2865 /* 2866 * n = 0 ~ 7 2867 */ 2868 #define __gpio_as_pwm(n) __gpio_as_pwm##n() 2869 2870 /* GPIO or Interrupt Mode */ 2871 2872 #define __gpio_get_port(p) (REG_GPIO_PXPIN(p)) 2873 2874 #define __gpio_port_as_output(p, o) \ 2875 do { \ 2876 REG_GPIO_PXFUNC(p) = (1 << (o)); \ 2877 REG_GPIO_PXSELC(p) = (1 << (o)); \ 2878 REG_GPIO_PXDIRS(p) = (1 << (o)); \ 2879 } while (0) 2880 2881 #define __gpio_port_as_input(p, o) \ 2882 do { \ 2883 REG_GPIO_PXFUNC(p) = (1 << (o)); \ 2884 REG_GPIO_PXSELC(p) = (1 << (o)); \ 2885 REG_GPIO_PXDIRC(p) = (1 << (o)); \ 2886 } while (0) 2887 2888 #define __gpio_as_output(n) \ 2889 do { \ 2890 unsigned int p, o; \ 2891 p = (n) / 32; \ 2892 o = (n) % 32; \ 2893 __gpio_port_as_output(p, o); \ 2894 } while (0) 2895 2896 #define __gpio_as_input(n) \ 2897 do { \ 2898 unsigned int p, o; \ 2899 p = (n) / 32; \ 2900 o = (n) % 32; \ 2901 __gpio_port_as_input(p, o); \ 2902 } while (0) 2903 2904 #define __gpio_set_pin(n) \ 2905 do { \ 2906 unsigned int p, o; \ 2907 p = (n) / 32; \ 2908 o = (n) % 32; \ 2909 REG_GPIO_PXDATS(p) = (1 << o); \ 2910 } while (0) 2911 2912 #define __gpio_clear_pin(n) \ 2913 do { \ 2914 unsigned int p, o; \ 2915 p = (n) / 32; \ 2916 o = (n) % 32; \ 2917 REG_GPIO_PXDATC(p) = (1 << o); \ 2918 } while (0) 2919 2920 #define __gpio_get_pin(n) \ 2921 ({ \ 2922 unsigned int p, o, v; \ 2923 p = (n) / 32; \ 2924 o = (n) % 32; \ 2925 if (__gpio_get_port(p) & (1 << o)) \ 2926 v = 1; \ 2927 else \ 2928 v = 0; \ 2929 v; \ 2930 }) 2931 2932 #define __gpio_as_irq_high_level(n) \ 2933 do { \ 2934 unsigned int p, o; \ 2935 p = (n) / 32; \ 2936 o = (n) % 32; \ 2937 REG_GPIO_PXIMS(p) = (1 << o); \ 2938 REG_GPIO_PXTRGC(p) = (1 << o); \ 2939 REG_GPIO_PXFUNC(p) = (1 << o); \ 2940 REG_GPIO_PXSELS(p) = (1 << o); \ 2941 REG_GPIO_PXDIRS(p) = (1 << o); \ 2942 REG_GPIO_PXFLGC(p) = (1 << o); \ 2943 REG_GPIO_PXIMC(p) = (1 << o); \ 2944 } while (0) 2945 2946 #define __gpio_as_irq_low_level(n) \ 2947 do { \ 2948 unsigned int p, o; \ 2949 p = (n) / 32; \ 2950 o = (n) % 32; \ 2951 REG_GPIO_PXIMS(p) = (1 << o); \ 2952 REG_GPIO_PXTRGC(p) = (1 << o); \ 2953 REG_GPIO_PXFUNC(p) = (1 << o); \ 2954 REG_GPIO_PXSELS(p) = (1 << o); \ 2955 REG_GPIO_PXDIRC(p) = (1 << o); \ 2956 REG_GPIO_PXFLGC(p) = (1 << o); \ 2957 REG_GPIO_PXIMC(p) = (1 << o); \ 2958 } while (0) 2959 2960 #define __gpio_as_irq_rise_edge(n) \ 2961 do { \ 2962 unsigned int p, o; \ 2963 p = (n) / 32; \ 2964 o = (n) % 32; \ 2965 REG_GPIO_PXIMS(p) = (1 << o); \ 2966 REG_GPIO_PXTRGS(p) = (1 << o); \ 2967 REG_GPIO_PXFUNC(p) = (1 << o); \ 2968 REG_GPIO_PXSELS(p) = (1 << o); \ 2969 REG_GPIO_PXDIRS(p) = (1 << o); \ 2970 REG_GPIO_PXFLGC(p) = (1 << o); \ 2971 REG_GPIO_PXIMC(p) = (1 << o); \ 2972 } while (0) 2973 2974 #define __gpio_as_irq_fall_edge(n) \ 2975 do { \ 2976 unsigned int p, o; \ 2977 p = (n) / 32; \ 2978 o = (n) % 32; \ 2979 REG_GPIO_PXIMS(p) = (1 << o); \ 2980 REG_GPIO_PXTRGS(p) = (1 << o); \ 2981 REG_GPIO_PXFUNC(p) = (1 << o); \ 2982 REG_GPIO_PXSELS(p) = (1 << o); \ 2983 REG_GPIO_PXDIRC(p) = (1 << o); \ 2984 REG_GPIO_PXFLGC(p) = (1 << o); \ 2985 REG_GPIO_PXIMC(p) = (1 << o); \ 2986 } while (0) 2987 2988 #define __gpio_mask_irq(n) \ 2989 do { \ 2990 unsigned int p, o; \ 2991 p = (n) / 32; \ 2992 o = (n) % 32; \ 2993 REG_GPIO_PXIMS(p) = (1 << o); \ 2994 } while (0) 2995 2996 #define __gpio_unmask_irq(n) \ 2997 do { \ 2998 unsigned int p, o; \ 2999 p = (n) / 32; \ 3000 o = (n) % 32; \ 3001 REG_GPIO_PXIMC(p) = (1 << o); \ 3002 } while (0) 3003 3004 #define __gpio_ack_irq(n) \ 3005 do { \ 3006 unsigned int p, o; \ 3007 p = (n) / 32; \ 3008 o = (n) % 32; \ 3009 REG_GPIO_PXFLGC(p) = (1 << o); \ 3010 } while (0) 3011 3012 #define __gpio_get_irq() \ 3013 ({ \ 3014 unsigned int p, i, tmp, v = 0; \ 3015 for (p = 3; p >= 0; p--) { \ 3016 tmp = REG_GPIO_PXFLG(p); \ 3017 for (i = 0; i < 32; i++) \ 3018 if (tmp & (1 << i)) \ 3019 v = (32*p + i); \ 3020 } \ 3021 v; \ 3022 }) 3023 3024 #define __gpio_group_irq(n) \ 3025 ({ \ 3026 register int tmp, i; \ 3027 tmp = REG_GPIO_PXFLG((n)); \ 3028 for (i=31;i>=0;i--) \ 3029 if (tmp & (1 << i)) \ 3030 break; \ 3031 i; \ 3032 }) 3033 3034 #define __gpio_enable_pull(n) \ 3035 do { \ 3036 unsigned int p, o; \ 3037 p = (n) / 32; \ 3038 o = (n) % 32; \ 3039 REG_GPIO_PXPEC(p) = (1 << o); \ 3040 } while (0) 3041 3042 #define __gpio_disable_pull(n) \ 3043 do { \ 3044 unsigned int p, o; \ 3045 p = (n) / 32; \ 3046 o = (n) % 32; \ 3047 REG_GPIO_PXPES(p) = (1 << o); \ 3048 } while (0) 3049 3050 3051 /*************************************************************************** 3052 * CPM 3053 ***************************************************************************/ 3054 #define __cpm_get_pllm() \ 3055 ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT) 3056 #define __cpm_get_plln() \ 3057 ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT) 3058 #define __cpm_get_pllod() \ 3059 ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT) 3060 3061 #define __cpm_get_cdiv() \ 3062 ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT) 3063 #define __cpm_get_hdiv() \ 3064 ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT) 3065 #define __cpm_get_pdiv() \ 3066 ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT) 3067 #define __cpm_get_mdiv() \ 3068 ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT) 3069 #define __cpm_get_ldiv() \ 3070 ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT) 3071 #define __cpm_get_udiv() \ 3072 ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT) 3073 #define __cpm_get_i2sdiv() \ 3074 ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT) 3075 #define __cpm_get_pixdiv() \ 3076 ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT) 3077 #define __cpm_get_mscdiv() \ 3078 ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT) 3079 3080 #define __cpm_set_cdiv(v) \ 3081 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT))) 3082 #define __cpm_set_hdiv(v) \ 3083 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT))) 3084 #define __cpm_set_pdiv(v) \ 3085 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT))) 3086 #define __cpm_set_mdiv(v) \ 3087 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT))) 3088 #define __cpm_set_ldiv(v) \ 3089 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT))) 3090 #define __cpm_set_udiv(v) \ 3091 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT))) 3092 #define __cpm_set_i2sdiv(v) \ 3093 (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT))) 3094 #define __cpm_set_pixdiv(v) \ 3095 (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT))) 3096 #define __cpm_set_mscdiv(v) \ 3097 (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT))) 3098 3099 #define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS) 3100 #define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS) 3101 #define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN) 3102 #define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS) 3103 #define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS) 3104 #define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE) 3105 #define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS) 3106 #define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS) 3107 3108 #define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS) 3109 #define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP) 3110 #define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN) 3111 3112 #define __cpm_get_cclk_doze_duty() \ 3113 ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT) 3114 #define __cpm_set_cclk_doze_duty(v) \ 3115 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT))) 3116 3117 #define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON) 3118 #define __cpm_idle_mode() \ 3119 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE) 3120 #define __cpm_sleep_mode() \ 3121 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP) 3122 3123 #define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff) 3124 #define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1) 3125 #define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC) 3126 #define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU) 3127 #define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC) 3128 #define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC) 3129 #define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD) 3130 #define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM) 3131 #define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC) 3132 #define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC) 3133 #define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1) 3134 #define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2) 3135 #define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI) 3136 #define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C) 3137 #define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC) 3138 #define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU) 3139 #define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0) 3140 3141 #define __cpm_start_all() (REG_CPM_CLKGR = 0x0) 3142 #define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1) 3143 #define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC) 3144 #define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU) 3145 #define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC) 3146 #define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC) 3147 #define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD) 3148 #define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM) 3149 #define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC) 3150 #define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC) 3151 #define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1) 3152 #define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2) 3153 #define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI) 3154 #define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C) 3155 #define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC) 3156 #define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU) 3157 #define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0) 3158 3159 #define __cpm_get_o1st() \ 3160 ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT) 3161 #define __cpm_set_o1st(v) \ 3162 (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT))) 3163 #define __cpm_suspend_udcphy() (REG_CPM_SCR &= ~CPM_SCR_UDCPHY_ENABLE) 3164 #define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_DISABLE) 3165 #define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE) 3166 3167 #define JZ_EXTAL CONFIG_SYS_EXTAL 3168 #define JZ_EXTAL2 32768 /* RTC clock */ 3169 3170 /* PLL output frequency */ 3171 static __inline__ unsigned int __cpm_get_pllout(void) 3172 { 3173 unsigned long m, n, no, pllout; 3174 unsigned long cppcr = REG_CPM_CPPCR; 3175 unsigned long od[4] = {1, 2, 2, 4}; 3176 if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) { 3177 m = __cpm_get_pllm() + 2; 3178 n = __cpm_get_plln() + 2; 3179 no = od[__cpm_get_pllod()]; 3180 pllout = ((JZ_EXTAL) / (n * no)) * m; 3181 } else 3182 pllout = JZ_EXTAL; 3183 return pllout; 3184 } 3185 3186 /* PLL output frequency for MSC/I2S/LCD/USB */ 3187 static __inline__ unsigned int __cpm_get_pllout2(void) 3188 { 3189 if (REG_CPM_CPCCR & CPM_CPCCR_PCS) 3190 return __cpm_get_pllout(); 3191 else 3192 return __cpm_get_pllout()/2; 3193 } 3194 3195 /* CPU core clock */ 3196 static __inline__ unsigned int __cpm_get_cclk(void) 3197 { 3198 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 3199 3200 return __cpm_get_pllout() / div[__cpm_get_cdiv()]; 3201 } 3202 3203 /* AHB system bus clock */ 3204 static __inline__ unsigned int __cpm_get_hclk(void) 3205 { 3206 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 3207 3208 return __cpm_get_pllout() / div[__cpm_get_hdiv()]; 3209 } 3210 3211 /* Memory bus clock */ 3212 static __inline__ unsigned int __cpm_get_mclk(void) 3213 { 3214 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 3215 3216 return __cpm_get_pllout() / div[__cpm_get_mdiv()]; 3217 } 3218 3219 /* APB peripheral bus clock */ 3220 static __inline__ unsigned int __cpm_get_pclk(void) 3221 { 3222 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 3223 3224 return __cpm_get_pllout() / div[__cpm_get_pdiv()]; 3225 } 3226 3227 /* LCDC module clock */ 3228 static __inline__ unsigned int __cpm_get_lcdclk(void) 3229 { 3230 return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1); 3231 } 3232 3233 /* LCD pixel clock */ 3234 static __inline__ unsigned int __cpm_get_pixclk(void) 3235 { 3236 return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1); 3237 } 3238 3239 /* I2S clock */ 3240 static __inline__ unsigned int __cpm_get_i2sclk(void) 3241 { 3242 if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) { 3243 return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1); 3244 } 3245 else { 3246 return JZ_EXTAL; 3247 } 3248 } 3249 3250 /* USB clock */ 3251 static __inline__ unsigned int __cpm_get_usbclk(void) 3252 { 3253 if (REG_CPM_CPCCR & CPM_CPCCR_UCS) { 3254 return __cpm_get_pllout2() / (__cpm_get_udiv() + 1); 3255 } 3256 else { 3257 return JZ_EXTAL; 3258 } 3259 } 3260 3261 /* MSC clock */ 3262 static __inline__ unsigned int __cpm_get_mscclk(void) 3263 { 3264 return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1); 3265 } 3266 3267 /* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */ 3268 static __inline__ unsigned int __cpm_get_extalclk(void) 3269 { 3270 return JZ_EXTAL; 3271 } 3272 3273 /* RTC clock for CPM,INTC,RTC,TCU,WDT */ 3274 static __inline__ unsigned int __cpm_get_rtcclk(void) 3275 { 3276 return JZ_EXTAL2; 3277 } 3278 3279 /* 3280 * Output 24MHz for SD and 16MHz for MMC. 3281 */ 3282 static inline void __cpm_select_msc_clk(int sd) 3283 { 3284 unsigned int pllout2 = __cpm_get_pllout2(); 3285 unsigned int div = 0; 3286 3287 if (sd) { 3288 div = pllout2 / 24000000; 3289 } 3290 else { 3291 div = pllout2 / 16000000; 3292 } 3293 3294 REG_CPM_MSCCDR = div - 1; 3295 } 3296 3297 /* 3298 * TCU 3299 */ 3300 /* where 'n' is the TCU channel */ 3301 #define __tcu_select_extalclk(n) \ 3302 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN) 3303 #define __tcu_select_rtcclk(n) \ 3304 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN) 3305 #define __tcu_select_pclk(n) \ 3306 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN) 3307 3308 #define __tcu_select_clk_div1(n) \ 3309 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1) 3310 #define __tcu_select_clk_div4(n) \ 3311 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4) 3312 #define __tcu_select_clk_div16(n) \ 3313 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16) 3314 #define __tcu_select_clk_div64(n) \ 3315 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64) 3316 #define __tcu_select_clk_div256(n) \ 3317 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256) 3318 #define __tcu_select_clk_div1024(n) \ 3319 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024) 3320 3321 #define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN ) 3322 #define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN ) 3323 3324 #define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH ) 3325 #define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH ) 3326 3327 #define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD ) 3328 #define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD ) 3329 3330 #define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) ) 3331 #define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) ) 3332 3333 #define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) ) 3334 #define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) ) 3335 #define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) ) 3336 #define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) ) 3337 #define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) ) 3338 #define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) ) 3339 #define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) ) 3340 #define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) ) 3341 #define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) ) 3342 #define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) ) 3343 3344 #define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC ) 3345 #define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) ) 3346 3347 #define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC ) 3348 #define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) ) 3349 3350 #define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC ) 3351 #define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) ) 3352 3353 #define __tcu_get_count(n) ( REG_TCU_TCNT((n)) ) 3354 #define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) ) 3355 #define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) ) 3356 #define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) ) 3357 3358 3359 /*************************************************************************** 3360 * WDT 3361 ***************************************************************************/ 3362 #define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN ) 3363 #define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN ) 3364 #define __wdt_set_count(v) ( REG_WDT_TCNT = (v) ) 3365 #define __wdt_set_data(v) ( REG_WDT_TDR = (v) ) 3366 3367 #define __wdt_select_extalclk() \ 3368 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN) 3369 #define __wdt_select_rtcclk() \ 3370 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN) 3371 #define __wdt_select_pclk() \ 3372 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN) 3373 3374 #define __wdt_select_clk_div1() \ 3375 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1) 3376 #define __wdt_select_clk_div4() \ 3377 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4) 3378 #define __wdt_select_clk_div16() \ 3379 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16) 3380 #define __wdt_select_clk_div64() \ 3381 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64) 3382 #define __wdt_select_clk_div256() \ 3383 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256) 3384 #define __wdt_select_clk_div1024() \ 3385 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024) 3386 3387 3388 /*************************************************************************** 3389 * UART 3390 ***************************************************************************/ 3391 3392 #define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE ) 3393 #define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE ) 3394 3395 #define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE ) 3396 #define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE ) 3397 3398 #define __uart_enable_receive_irq() \ 3399 ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) 3400 #define __uart_disable_receive_irq() \ 3401 ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) 3402 3403 #define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP ) 3404 #define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP ) 3405 3406 #define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 ) 3407 3408 #define __uart_set_baud(devclk, baud) \ 3409 do { \ 3410 REG8(UART0_LCR) |= UARTLCR_DLAB; \ 3411 REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \ 3412 REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ 3413 REG8(UART0_LCR) &= ~UARTLCR_DLAB; \ 3414 } while (0) 3415 3416 #define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 ) 3417 #define __uart_clear_errors() \ 3418 ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) ) 3419 3420 #define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 ) 3421 #define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 ) 3422 #define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) ) 3423 #define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) 3424 #define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) 3425 #define __uart_receive_char() REG8(UART0_RDR) 3426 #define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) 3427 #define __uart_enable_irda() \ 3428 /* Tx high pulse as 0, Rx low pulse as 0 */ \ 3429 ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) 3430 3431 3432 /*************************************************************************** 3433 * DMAC 3434 ***************************************************************************/ 3435 3436 /* n is the DMA channel (0 - 5) */ 3437 3438 #define __dmac_enable_module() \ 3439 ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR ) 3440 #define __dmac_disable_module() \ 3441 ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE ) 3442 3443 /* p=0,1,2,3 */ 3444 #define __dmac_set_priority(p) \ 3445 do { \ 3446 REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ 3447 REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ 3448 } while (0) 3449 3450 #define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT ) 3451 #define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR ) 3452 3453 #define __dmac_enable_descriptor(n) \ 3454 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES ) 3455 #define __dmac_disable_descriptor(n) \ 3456 ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES ) 3457 3458 #define __dmac_enable_channel(n) \ 3459 ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN ) 3460 #define __dmac_disable_channel(n) \ 3461 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN ) 3462 #define __dmac_channel_enabled(n) \ 3463 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN ) 3464 3465 #define __dmac_channel_enable_irq(n) \ 3466 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE ) 3467 #define __dmac_channel_disable_irq(n) \ 3468 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE ) 3469 3470 #define __dmac_channel_transmit_halt_detected(n) \ 3471 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT ) 3472 #define __dmac_channel_transmit_end_detected(n) \ 3473 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT ) 3474 #define __dmac_channel_address_error_detected(n) \ 3475 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR ) 3476 #define __dmac_channel_count_terminated_detected(n) \ 3477 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT ) 3478 #define __dmac_channel_descriptor_invalid_detected(n) \ 3479 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV ) 3480 3481 #define __dmac_channel_clear_transmit_halt(n) \ 3482 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) 3483 #define __dmac_channel_clear_transmit_end(n) \ 3484 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT ) 3485 #define __dmac_channel_clear_address_error(n) \ 3486 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) 3487 #define __dmac_channel_clear_count_terminated(n) \ 3488 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT ) 3489 #define __dmac_channel_clear_descriptor_invalid(n) \ 3490 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV ) 3491 3492 #define __dmac_channel_set_single_mode(n) \ 3493 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM ) 3494 #define __dmac_channel_set_block_mode(n) \ 3495 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM ) 3496 3497 #define __dmac_channel_set_transfer_unit_32bit(n) \ 3498 do { \ 3499 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3500 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \ 3501 } while (0) 3502 3503 #define __dmac_channel_set_transfer_unit_16bit(n) \ 3504 do { \ 3505 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3506 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \ 3507 } while (0) 3508 3509 #define __dmac_channel_set_transfer_unit_8bit(n) \ 3510 do { \ 3511 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3512 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \ 3513 } while (0) 3514 3515 #define __dmac_channel_set_transfer_unit_16byte(n) \ 3516 do { \ 3517 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3518 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \ 3519 } while (0) 3520 3521 #define __dmac_channel_set_transfer_unit_32byte(n) \ 3522 do { \ 3523 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3524 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \ 3525 } while (0) 3526 3527 /* w=8,16,32 */ 3528 #define __dmac_channel_set_dest_port_width(n,w) \ 3529 do { \ 3530 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \ 3531 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \ 3532 } while (0) 3533 3534 /* w=8,16,32 */ 3535 #define __dmac_channel_set_src_port_width(n,w) \ 3536 do { \ 3537 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \ 3538 REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \ 3539 } while (0) 3540 3541 /* v=0-15 */ 3542 #define __dmac_channel_set_rdil(n,v) \ 3543 do { \ 3544 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \ 3545 REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \ 3546 } while (0) 3547 3548 #define __dmac_channel_dest_addr_fixed(n) \ 3549 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI ) 3550 #define __dmac_channel_dest_addr_increment(n) \ 3551 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI ) 3552 3553 #define __dmac_channel_src_addr_fixed(n) \ 3554 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI ) 3555 #define __dmac_channel_src_addr_increment(n) \ 3556 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI ) 3557 3558 #define __dmac_channel_set_doorbell(n) \ 3559 ( REG_DMAC_DMADBSR = (1 << (n)) ) 3560 3561 #define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) ) 3562 #define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) ) 3563 3564 static __inline__ int __dmac_get_irq(void) 3565 { 3566 int i; 3567 for (i = 0; i < MAX_DMA_NUM; i++) 3568 if (__dmac_channel_irq_detected(i)) 3569 return i; 3570 return -1; 3571 } 3572 3573 3574 /*************************************************************************** 3575 * AIC (AC'97 & I2S Controller) 3576 ***************************************************************************/ 3577 3578 #define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) 3579 #define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) 3580 3581 #define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) 3582 #define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) 3583 3584 #define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) 3585 #define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) 3586 #define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST ) 3587 3588 #define __aic_reset() \ 3589 do { \ 3590 REG_AIC_FR |= AIC_FR_RST; \ 3591 } while(0) 3592 3593 3594 #define __aic_set_transmit_trigger(n) \ 3595 do { \ 3596 REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ 3597 REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \ 3598 } while(0) 3599 3600 #define __aic_set_receive_trigger(n) \ 3601 do { \ 3602 REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ 3603 REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \ 3604 } while(0) 3605 3606 #define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) 3607 #define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) 3608 #define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) 3609 #define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) 3610 #define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) 3611 #define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) 3612 3613 #define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH ) 3614 #define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH ) 3615 3616 #define __aic_enable_transmit_intr() \ 3617 ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) 3618 #define __aic_disable_transmit_intr() \ 3619 ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) 3620 #define __aic_enable_receive_intr() \ 3621 ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) 3622 #define __aic_disable_receive_intr() \ 3623 ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) 3624 3625 #define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) 3626 #define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) 3627 #define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) 3628 #define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) 3629 3630 #define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S ) 3631 #define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S ) 3632 #define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW ) 3633 #define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW ) 3634 #define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU ) 3635 #define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU ) 3636 3637 #define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3 3638 #define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4 3639 #define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6 3640 #define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7 3641 #define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8 3642 #define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9 3643 3644 #define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3 3645 #define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4 3646 #define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6 3647 #define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7 3648 #define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8 3649 #define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9 3650 3651 #define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) 3652 #define __ac97_set_xs_mono() \ 3653 do { \ 3654 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ 3655 REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ 3656 } while(0) 3657 #define __ac97_set_xs_stereo() \ 3658 do { \ 3659 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ 3660 REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ 3661 } while(0) 3662 3663 /* In fact, only stereo is support now. */ 3664 #define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) 3665 #define __ac97_set_rs_mono() \ 3666 do { \ 3667 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ 3668 REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ 3669 } while(0) 3670 #define __ac97_set_rs_stereo() \ 3671 do { \ 3672 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ 3673 REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ 3674 } while(0) 3675 3676 #define __ac97_warm_reset_codec() \ 3677 do { \ 3678 REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ 3679 REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ 3680 udelay(2); \ 3681 REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ 3682 REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ 3683 } while (0) 3684 3685 #define __ac97_cold_reset_codec() \ 3686 do { \ 3687 REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ 3688 udelay(2); \ 3689 REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ 3690 } while (0) 3691 3692 /* n=8,16,18,20 */ 3693 #define __ac97_set_iass(n) \ 3694 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) 3695 #define __ac97_set_oass(n) \ 3696 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) 3697 3698 #define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) 3699 #define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) 3700 3701 /* n=8,16,18,20,24 */ 3702 /*#define __i2s_set_sample_size(n) \ 3703 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/ 3704 3705 #define __i2s_set_oss_sample_size(n) \ 3706 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT ) 3707 #define __i2s_set_iss_sample_size(n) \ 3708 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT ) 3709 3710 #define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) 3711 #define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) 3712 3713 #define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) 3714 #define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) 3715 #define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) 3716 #define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) 3717 3718 #define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) 3719 3720 #define __aic_get_transmit_resident() \ 3721 ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT ) 3722 #define __aic_get_receive_count() \ 3723 ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) 3724 3725 #define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) 3726 #define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) 3727 #define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) 3728 #define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) 3729 #define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) 3730 #define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR ) 3731 #define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR ) 3732 3733 #define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) 3734 3735 #define CODEC_READ_CMD (1 << 19) 3736 #define CODEC_WRITE_CMD (0 << 19) 3737 #define CODEC_REG_INDEX_BIT 12 3738 #define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */ 3739 #define CODEC_REG_DATA_BIT 4 3740 #define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */ 3741 3742 #define __ac97_out_rcmd_addr(reg) \ 3743 do { \ 3744 REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ 3745 } while (0) 3746 3747 #define __ac97_out_wcmd_addr(reg) \ 3748 do { \ 3749 REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ 3750 } while (0) 3751 3752 #define __ac97_out_data(value) \ 3753 do { \ 3754 REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \ 3755 } while (0) 3756 3757 #define __ac97_in_data() \ 3758 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) 3759 3760 #define __ac97_in_status_addr() \ 3761 ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) 3762 3763 #define __i2s_set_sample_rate(i2sclk, sync) \ 3764 ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) 3765 3766 #define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) 3767 #define __aic_read_rfifo() ( REG_AIC_DR ) 3768 3769 #define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC ) 3770 #define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC ) 3771 3772 /* Define next ops for AC97 compatible */ 3773 3774 #define AC97_ACSR AIC_ACSR 3775 3776 #define __ac97_enable() __aic_enable(); __aic_select_ac97() 3777 #define __ac97_disable() __aic_disable() 3778 #define __ac97_reset() __aic_reset() 3779 3780 #define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) 3781 #define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) 3782 3783 #define __ac97_enable_record() __aic_enable_record() 3784 #define __ac97_disable_record() __aic_disable_record() 3785 #define __ac97_enable_replay() __aic_enable_replay() 3786 #define __ac97_disable_replay() __aic_disable_replay() 3787 #define __ac97_enable_loopback() __aic_enable_loopback() 3788 #define __ac97_disable_loopback() __aic_disable_loopback() 3789 3790 #define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() 3791 #define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() 3792 #define __ac97_enable_receive_dma() __aic_enable_receive_dma() 3793 #define __ac97_disable_receive_dma() __aic_disable_receive_dma() 3794 3795 #define __ac97_transmit_request() __aic_transmit_request() 3796 #define __ac97_receive_request() __aic_receive_request() 3797 #define __ac97_transmit_underrun() __aic_transmit_underrun() 3798 #define __ac97_receive_overrun() __aic_receive_overrun() 3799 3800 #define __ac97_clear_errors() __aic_clear_errors() 3801 3802 #define __ac97_get_transmit_resident() __aic_get_transmit_resident() 3803 #define __ac97_get_receive_count() __aic_get_receive_count() 3804 3805 #define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() 3806 #define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() 3807 #define __ac97_enable_receive_intr() __aic_enable_receive_intr() 3808 #define __ac97_disable_receive_intr() __aic_disable_receive_intr() 3809 3810 #define __ac97_write_tfifo(v) __aic_write_tfifo(v) 3811 #define __ac97_read_rfifo() __aic_read_rfifo() 3812 3813 /* Define next ops for I2S compatible */ 3814 3815 #define I2S_ACSR AIC_I2SSR 3816 3817 #define __i2s_enable() __aic_enable(); __aic_select_i2s() 3818 #define __i2s_disable() __aic_disable() 3819 #define __i2s_reset() __aic_reset() 3820 3821 #define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) 3822 #define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) 3823 3824 #define __i2s_enable_record() __aic_enable_record() 3825 #define __i2s_disable_record() __aic_disable_record() 3826 #define __i2s_enable_replay() __aic_enable_replay() 3827 #define __i2s_disable_replay() __aic_disable_replay() 3828 #define __i2s_enable_loopback() __aic_enable_loopback() 3829 #define __i2s_disable_loopback() __aic_disable_loopback() 3830 3831 #define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() 3832 #define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() 3833 #define __i2s_enable_receive_dma() __aic_enable_receive_dma() 3834 #define __i2s_disable_receive_dma() __aic_disable_receive_dma() 3835 3836 #define __i2s_transmit_request() __aic_transmit_request() 3837 #define __i2s_receive_request() __aic_receive_request() 3838 #define __i2s_transmit_underrun() __aic_transmit_underrun() 3839 #define __i2s_receive_overrun() __aic_receive_overrun() 3840 3841 #define __i2s_clear_errors() __aic_clear_errors() 3842 3843 #define __i2s_get_transmit_resident() __aic_get_transmit_resident() 3844 #define __i2s_get_receive_count() __aic_get_receive_count() 3845 3846 #define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() 3847 #define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() 3848 #define __i2s_enable_receive_intr() __aic_enable_receive_intr() 3849 #define __i2s_disable_receive_intr() __aic_disable_receive_intr() 3850 3851 #define __i2s_write_tfifo(v) __aic_write_tfifo(v) 3852 #define __i2s_read_rfifo() __aic_read_rfifo() 3853 3854 #define __i2s_reset_codec() \ 3855 do { \ 3856 } while (0) 3857 3858 3859 /*************************************************************************** 3860 * ICDC 3861 ***************************************************************************/ 3862 #define __i2s_internal_codec() __aic_internal_codec() 3863 #define __i2s_external_codec() __aic_external_codec() 3864 3865 /*************************************************************************** 3866 * INTC 3867 ***************************************************************************/ 3868 #define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) 3869 #define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) 3870 #define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) 3871 3872 3873 /*************************************************************************** 3874 * I2C 3875 ***************************************************************************/ 3876 3877 #define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE ) 3878 #define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE ) 3879 3880 #define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA ) 3881 #define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO ) 3882 #define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC ) 3883 #define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC ) 3884 3885 #define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF ) 3886 #define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF ) 3887 #define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF ) 3888 3889 #define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) ) 3890 #define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY ) 3891 #define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND ) 3892 3893 #define __i2c_set_clk(dev_clk, i2c_clk) \ 3894 ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) 3895 3896 #define __i2c_read() ( REG_I2C_DR ) 3897 #define __i2c_write(val) ( REG_I2C_DR = (val) ) 3898 3899 3900 /*************************************************************************** 3901 * MSC 3902 ***************************************************************************/ 3903 3904 #define __msc_start_op() \ 3905 ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) 3906 3907 #define __msc_set_resto(to) ( REG_MSC_RESTO = to ) 3908 #define __msc_set_rdto(to) ( REG_MSC_RDTO = to ) 3909 #define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd ) 3910 #define __msc_set_arg(arg) ( REG_MSC_ARG = arg ) 3911 #define __msc_set_nob(nob) ( REG_MSC_NOB = nob ) 3912 #define __msc_get_nob() ( REG_MSC_NOB ) 3913 #define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len ) 3914 #define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat ) 3915 #define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) 3916 #define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) 3917 3918 #define __msc_set_cmdat_bus_width1() \ 3919 do { \ 3920 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ 3921 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \ 3922 } while(0) 3923 3924 #define __msc_set_cmdat_bus_width4() \ 3925 do { \ 3926 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ 3927 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \ 3928 } while(0) 3929 3930 #define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN ) 3931 #define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT ) 3932 #define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY ) 3933 #define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) 3934 #define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) 3935 #define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) 3936 #define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) 3937 #define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN ) 3938 3939 /* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ 3940 #define __msc_set_cmdat_res_format(r) \ 3941 do { \ 3942 REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ 3943 REG_MSC_CMDAT |= (r); \ 3944 } while(0) 3945 3946 #define __msc_clear_cmdat() \ 3947 REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ 3948 MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ 3949 MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ) 3950 3951 #define __msc_get_imask() ( REG_MSC_IMASK ) 3952 #define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff ) 3953 #define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 ) 3954 #define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) 3955 #define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) 3956 #define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) 3957 #define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) 3958 #define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES ) 3959 #define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) 3960 #define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) 3961 #define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) 3962 #define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE ) 3963 #define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) 3964 3965 /* n=0,1,2,3,4,5,6,7 */ 3966 #define __msc_set_clkrt(n) \ 3967 do { \ 3968 REG_MSC_CLKRT = n; \ 3969 } while(0) 3970 3971 #define __msc_get_ireg() ( REG_MSC_IREG ) 3972 #define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) 3973 #define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) 3974 #define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES ) 3975 #define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) 3976 #define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE ) 3977 #define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES ) 3978 #define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) 3979 #define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE ) 3980 3981 #define __msc_get_stat() ( REG_MSC_STAT ) 3982 #define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0) 3983 #define __msc_stat_crc_err() \ 3984 ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) 3985 #define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR ) 3986 #define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR ) 3987 #define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) 3988 #define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES ) 3989 #define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ ) 3990 3991 #define __msc_rd_resfifo() ( REG_MSC_RES ) 3992 #define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) 3993 #define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) 3994 3995 #define __msc_reset() \ 3996 do { \ 3997 REG_MSC_STRPCL = MSC_STRPCL_RESET; \ 3998 while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ 3999 } while (0) 4000 4001 #define __msc_start_clk() \ 4002 do { \ 4003 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \ 4004 } while (0) 4005 4006 #define __msc_stop_clk() \ 4007 do { \ 4008 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \ 4009 } while (0) 4010 4011 #define MMC_CLK 19169200 4012 #define SD_CLK 24576000 4013 4014 /* msc_clk should little than pclk and little than clk retrieve from card */ 4015 #define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ 4016 do { \ 4017 unsigned int rate, pclk, i; \ 4018 pclk = dev_clk; \ 4019 rate = type?SD_CLK:MMC_CLK; \ 4020 if (msc_clk && msc_clk < pclk) \ 4021 pclk = msc_clk; \ 4022 i = 0; \ 4023 while (pclk < rate) \ 4024 { \ 4025 i ++; \ 4026 rate >>= 1; \ 4027 } \ 4028 lv = i; \ 4029 } while(0) 4030 4031 /* divide rate to little than or equal to 400kHz */ 4032 #define __msc_calc_slow_clk_divisor(type, lv) \ 4033 do { \ 4034 unsigned int rate, i; \ 4035 rate = (type?SD_CLK:MMC_CLK)/1000/400; \ 4036 i = 0; \ 4037 while (rate > 0) \ 4038 { \ 4039 rate >>= 1; \ 4040 i ++; \ 4041 } \ 4042 lv = i; \ 4043 } while(0) 4044 4045 4046 /*************************************************************************** 4047 * SSI 4048 ***************************************************************************/ 4049 4050 #define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE ) 4051 #define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE ) 4052 #define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL ) 4053 4054 #define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) 4055 4056 #define __ssi_select_ce2() \ 4057 do { \ 4058 REG_SSI_CR0 |= SSI_CR0_FSEL; \ 4059 REG_SSI_CR1 &= ~SSI_CR1_MULTS; \ 4060 } while (0) 4061 4062 #define __ssi_select_gpc() \ 4063 do { \ 4064 REG_SSI_CR0 &= ~SSI_CR0_FSEL; \ 4065 REG_SSI_CR1 |= SSI_CR1_MULTS; \ 4066 } while (0) 4067 4068 #define __ssi_enable_tx_intr() \ 4069 ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) 4070 4071 #define __ssi_disable_tx_intr() \ 4072 ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) 4073 4074 #define __ssi_enable_rx_intr() \ 4075 ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) 4076 4077 #define __ssi_disable_rx_intr() \ 4078 ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) 4079 4080 #define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP ) 4081 #define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP ) 4082 4083 #define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV ) 4084 #define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV ) 4085 4086 #define __ssi_finish_receive() \ 4087 ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) 4088 4089 #define __ssi_disable_recvfinish() \ 4090 ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) 4091 4092 #define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH ) 4093 #define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH ) 4094 4095 #define __ssi_flush_fifo() \ 4096 ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) 4097 4098 #define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN ) 4099 4100 #define __ssi_spi_format() \ 4101 do { \ 4102 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ 4103 REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \ 4104 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ 4105 REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ 4106 } while (0) 4107 4108 /* TI's SSP format, must clear SSI_CR1.UNFIN */ 4109 #define __ssi_ssp_format() \ 4110 do { \ 4111 REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ 4112 REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \ 4113 } while (0) 4114 4115 /* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ 4116 #define __ssi_microwire_format() \ 4117 do { \ 4118 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ 4119 REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \ 4120 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ 4121 REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ 4122 REG_SSI_CR0 &= ~SSI_CR0_RFINE; \ 4123 } while (0) 4124 4125 /* CE# level (FRMHL), CE# in interval time (ITFRM), 4126 clock phase and polarity (PHA POL), 4127 interval time (SSIITR), interval characters/frame (SSIICR) */ 4128 4129 /* frmhl,endian,mcom,flen,pha,pol MASK */ 4130 #define SSICR1_MISC_MASK \ 4131 ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ 4132 | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \ 4133 4134 #define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \ 4135 do { \ 4136 REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \ 4137 REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \ 4138 (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ 4139 ((pha) << 1) | (pol); \ 4140 } while(0) 4141 4142 /* Transfer with MSB or LSB first */ 4143 #define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST ) 4144 #define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST ) 4145 4146 #define __ssi_set_frame_length(n) \ 4147 REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4) 4148 4149 /* n = 1 - 16 */ 4150 #define __ssi_set_microwire_command_length(n) \ 4151 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) 4152 4153 /* Set the clock phase for SPI */ 4154 #define __ssi_set_spi_clock_phase(n) \ 4155 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) ) 4156 4157 /* Set the clock polarity for SPI */ 4158 #define __ssi_set_spi_clock_polarity(n) \ 4159 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) 4160 4161 /* n = ix8 */ 4162 #define __ssi_set_tx_trigger(n) \ 4163 do { \ 4164 REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \ 4165 REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \ 4166 } while (0) 4167 4168 /* n = ix8 */ 4169 #define __ssi_set_rx_trigger(n) \ 4170 do { \ 4171 REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \ 4172 REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \ 4173 } while (0) 4174 4175 #define __ssi_get_txfifo_count() \ 4176 ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) 4177 4178 #define __ssi_get_rxfifo_count() \ 4179 ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) 4180 4181 #define __ssi_clear_errors() \ 4182 ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) 4183 4184 #define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END ) 4185 #define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY ) 4186 4187 #define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF ) 4188 #define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE ) 4189 #define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF ) 4190 4191 #define __ssi_set_clk(dev_clk, ssi_clk) \ 4192 ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) 4193 4194 #define __ssi_receive_data() REG_SSI_DR 4195 #define __ssi_transmit_data(v) ( REG_SSI_DR = (v) ) 4196 4197 4198 /*************************************************************************** 4199 * CIM 4200 ***************************************************************************/ 4201 4202 #define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) 4203 #define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) 4204 4205 #define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) 4206 #define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) 4207 4208 #define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) 4209 #define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) 4210 4211 #define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) 4212 #define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) 4213 4214 #define __cim_sample_data_at_pclk_falling_edge() \ 4215 ( REG_CIM_CFG |= CIM_CFG_PCP ) 4216 #define __cim_sample_data_at_pclk_rising_edge() \ 4217 ( REG_CIM_CFG &= ~CIM_CFG_PCP ) 4218 4219 #define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) 4220 #define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) 4221 4222 #define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) 4223 #define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) 4224 4225 /* n=0-7 */ 4226 #define __cim_set_data_packing_mode(n) \ 4227 do { \ 4228 REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ 4229 REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ 4230 } while (0) 4231 4232 #define __cim_enable_ccir656_progressive_mode() \ 4233 do { \ 4234 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 4235 REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ 4236 } while (0) 4237 4238 #define __cim_enable_ccir656_interlace_mode() \ 4239 do { \ 4240 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 4241 REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ 4242 } while (0) 4243 4244 #define __cim_enable_gated_clock_mode() \ 4245 do { \ 4246 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 4247 REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ 4248 } while (0) 4249 4250 #define __cim_enable_nongated_clock_mode() \ 4251 do { \ 4252 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 4253 REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ 4254 } while (0) 4255 4256 /* sclk:system bus clock 4257 * mclk: CIM master clock 4258 */ 4259 #define __cim_set_master_clk(sclk, mclk) \ 4260 do { \ 4261 REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \ 4262 REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \ 4263 } while (0) 4264 4265 #define __cim_enable_sof_intr() \ 4266 ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) 4267 #define __cim_disable_sof_intr() \ 4268 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) 4269 4270 #define __cim_enable_eof_intr() \ 4271 ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) 4272 #define __cim_disable_eof_intr() \ 4273 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) 4274 4275 #define __cim_enable_stop_intr() \ 4276 ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) 4277 #define __cim_disable_stop_intr() \ 4278 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) 4279 4280 #define __cim_enable_trig_intr() \ 4281 ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) 4282 #define __cim_disable_trig_intr() \ 4283 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) 4284 4285 #define __cim_enable_rxfifo_overflow_intr() \ 4286 ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) 4287 #define __cim_disable_rxfifo_overflow_intr() \ 4288 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) 4289 4290 /* n=1-16 */ 4291 #define __cim_set_frame_rate(n) \ 4292 do { \ 4293 REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ 4294 REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ 4295 } while (0) 4296 4297 #define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) 4298 #define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) 4299 4300 #define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) 4301 #define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) 4302 4303 /* n=4,8,12,16,20,24,28,32 */ 4304 #define __cim_set_rxfifo_trigger(n) \ 4305 do { \ 4306 REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \ 4307 REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \ 4308 } while (0) 4309 4310 #define __cim_clear_state() ( REG_CIM_STATE = 0 ) 4311 4312 #define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) 4313 #define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) 4314 #define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) 4315 #define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) 4316 #define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) 4317 #define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) 4318 #define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) 4319 #define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) 4320 4321 #define __cim_get_iid() ( REG_CIM_IID ) 4322 #define __cim_get_image_data() ( REG_CIM_RXFIFO ) 4323 #define __cim_get_dam_cmd() ( REG_CIM_CMD ) 4324 4325 #define __cim_set_da(a) ( REG_CIM_DA = (a) ) 4326 4327 /*************************************************************************** 4328 * LCD 4329 ***************************************************************************/ 4330 #define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) ) 4331 #define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) ) 4332 4333 #define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS ) 4334 #define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS ) 4335 4336 #define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA ) 4337 #define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA ) 4338 4339 /* n=1,2,4,8,16 */ 4340 #define __lcd_set_bpp(n) \ 4341 ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n ) 4342 4343 /* n=4,8,16 */ 4344 #define __lcd_set_burst_length(n) \ 4345 do { \ 4346 REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \ 4347 REG_LCD_CTRL |= LCD_CTRL_BST_n##; \ 4348 } while (0) 4349 4350 #define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 ) 4351 #define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 ) 4352 4353 #define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP ) 4354 #define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP ) 4355 4356 /* n=2,4,16 */ 4357 #define __lcd_set_stn_frc(n) \ 4358 do { \ 4359 REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \ 4360 REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \ 4361 } while (0) 4362 4363 4364 #define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN ) 4365 #define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN ) 4366 4367 #define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN ) 4368 #define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN ) 4369 4370 #define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM ) 4371 #define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM ) 4372 4373 #define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM ) 4374 #define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM ) 4375 4376 #define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM ) 4377 #define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM ) 4378 4379 #define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 ) 4380 #define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 ) 4381 4382 #define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 ) 4383 #define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 ) 4384 4385 #define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM ) 4386 #define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM ) 4387 4388 #define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM ) 4389 #define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM ) 4390 4391 4392 /* LCD status register indication */ 4393 4394 #define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD ) 4395 #define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD ) 4396 #define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 ) 4397 #define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 ) 4398 #define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU ) 4399 #define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF ) 4400 #define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF ) 4401 4402 #define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU ) 4403 #define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF ) 4404 #define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF ) 4405 4406 #define __lcd_panel_white() ( REG_LCD_CFG |= LCD_CFG_WHITE ) 4407 #define __lcd_panel_black() ( REG_LCD_CFG &= ~LCD_CFG_WHITE ) 4408 4409 /* n=1,2,4,8 for single mono-STN 4410 * n=4,8 for dual mono-STN 4411 */ 4412 #define __lcd_set_panel_datawidth(n) \ 4413 do { \ 4414 REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \ 4415 REG_LCD_CFG |= LCD_CFG_PDW_n##; \ 4416 } while (0) 4417 4418 /* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */ 4419 #define __lcd_set_panel_mode(m) \ 4420 do { \ 4421 REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \ 4422 REG_LCD_CFG |= (m); \ 4423 } while(0) 4424 4425 /* n = 0-255 */ 4426 #define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff ) 4427 #define __lcd_set_ac_bias(n) \ 4428 do { \ 4429 REG_LCD_IO &= ~LCD_IO_ACB_MASK; \ 4430 REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \ 4431 } while(0) 4432 4433 #define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR ) 4434 #define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR ) 4435 4436 #define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP ) 4437 #define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP ) 4438 4439 #define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP ) 4440 #define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP ) 4441 4442 #define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP ) 4443 #define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP ) 4444 4445 #define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP ) 4446 #define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP ) 4447 4448 #define __lcd_vsync_get_vps() \ 4449 ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT ) 4450 4451 #define __lcd_vsync_get_vpe() \ 4452 ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT ) 4453 #define __lcd_vsync_set_vpe(n) \ 4454 do { \ 4455 REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \ 4456 REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \ 4457 } while (0) 4458 4459 #define __lcd_hsync_get_hps() \ 4460 ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT ) 4461 #define __lcd_hsync_set_hps(n) \ 4462 do { \ 4463 REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \ 4464 REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \ 4465 } while (0) 4466 4467 #define __lcd_hsync_get_hpe() \ 4468 ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT ) 4469 #define __lcd_hsync_set_hpe(n) \ 4470 do { \ 4471 REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \ 4472 REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \ 4473 } while (0) 4474 4475 #define __lcd_vat_get_ht() \ 4476 ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT ) 4477 #define __lcd_vat_set_ht(n) \ 4478 do { \ 4479 REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \ 4480 REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \ 4481 } while (0) 4482 4483 #define __lcd_vat_get_vt() \ 4484 ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT ) 4485 #define __lcd_vat_set_vt(n) \ 4486 do { \ 4487 REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \ 4488 REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \ 4489 } while (0) 4490 4491 #define __lcd_dah_get_hds() \ 4492 ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT ) 4493 #define __lcd_dah_set_hds(n) \ 4494 do { \ 4495 REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \ 4496 REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \ 4497 } while (0) 4498 4499 #define __lcd_dah_get_hde() \ 4500 ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT ) 4501 #define __lcd_dah_set_hde(n) \ 4502 do { \ 4503 REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \ 4504 REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \ 4505 } while (0) 4506 4507 #define __lcd_dav_get_vds() \ 4508 ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT ) 4509 #define __lcd_dav_set_vds(n) \ 4510 do { \ 4511 REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \ 4512 REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \ 4513 } while (0) 4514 4515 #define __lcd_dav_get_vde() \ 4516 ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT ) 4517 #define __lcd_dav_set_vde(n) \ 4518 do { \ 4519 REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \ 4520 REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \ 4521 } while (0) 4522 4523 #define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT ) 4524 #define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT ) 4525 #define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT ) 4526 #define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT ) 4527 4528 #define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT ) 4529 #define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT ) 4530 #define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT ) 4531 #define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT ) 4532 4533 #define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL ) 4534 #define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL ) 4535 4536 #define __lcd_cmd0_get_len() \ 4537 ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) 4538 #define __lcd_cmd1_get_len() \ 4539 ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) 4540 4541 /*************************************************************************** 4542 * RTC ops 4543 ***************************************************************************/ 4544 4545 #define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY ) 4546 #define __rtc_enabled() \ 4547 do{ \ 4548 while(!__rtc_write_ready()); \ 4549 REG_RTC_RCR |= RTC_RCR_RTCE ; \ 4550 }while(0) \ 4551 4552 #define __rtc_disabled() \ 4553 do{ \ 4554 while(!__rtc_write_ready()); \ 4555 REG_RTC_RCR &= ~RTC_RCR_RTCE; \ 4556 }while(0) 4557 #define __rtc_enable_alarm() \ 4558 do{ \ 4559 while(!__rtc_write_ready()); \ 4560 REG_RTC_RCR |= RTC_RCR_AE; \ 4561 }while(0) 4562 4563 #define __rtc_disable_alarm() \ 4564 do{ \ 4565 while(!__rtc_write_ready()); \ 4566 REG_RTC_RCR &= ~RTC_RCR_AE; \ 4567 }while(0) 4568 4569 #define __rtc_enable_alarm_irq() \ 4570 do{ \ 4571 while(!__rtc_write_ready()); \ 4572 REG_RTC_RCR |= RTC_RCR_AIE; \ 4573 }while(0) 4574 4575 #define __rtc_disable_alarm_irq() \ 4576 do{ \ 4577 while(!__rtc_write_ready()); \ 4578 REG_RTC_RCR &= ~RTC_RCR_AIE; \ 4579 }while(0) 4580 #define __rtc_enable_Hz_irq() \ 4581 do{ \ 4582 while(!__rtc_write_ready()); \ 4583 REG_RTC_RCR |= RTC_RCR_HZIE; \ 4584 }while(0) 4585 4586 #define __rtc_disable_Hz_irq() \ 4587 do{ \ 4588 while(!__rtc_write_ready()); \ 4589 REG_RTC_RCR &= ~RTC_RCR_HZIE; \ 4590 }while(0) 4591 #define __rtc_get_1Hz_flag() \ 4592 do{ \ 4593 while(!__rtc_write_ready()); \ 4594 ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \ 4595 }while(0) 4596 #define __rtc_clear_1Hz_flag() \ 4597 do{ \ 4598 while(!__rtc_write_ready()); \ 4599 REG_RTC_RCR &= ~RTC_RCR_HZ; \ 4600 }while(0) 4601 #define __rtc_get_alarm_flag() \ 4602 do{ \ 4603 while(!__rtc_write_ready()); \ 4604 ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1) \ 4605 while(0) 4606 #define __rtc_clear_alarm_flag() \ 4607 do{ \ 4608 while(!__rtc_write_ready()); \ 4609 REG_RTC_RCR &= ~RTC_RCR_AF; \ 4610 }while(0) 4611 #define __rtc_get_second() \ 4612 do{ \ 4613 while(!__rtc_write_ready());\ 4614 REG_RTC_RSR; \ 4615 }while(0) 4616 4617 #define __rtc_set_second(v) \ 4618 do{ \ 4619 while(!__rtc_write_ready()); \ 4620 REG_RTC_RSR = v; \ 4621 }while(0) 4622 4623 #define __rtc_get_alarm_second() \ 4624 do{ \ 4625 while(!__rtc_write_ready()); \ 4626 REG_RTC_RSAR; \ 4627 }while(0) 4628 4629 4630 #define __rtc_set_alarm_second(v) \ 4631 do{ \ 4632 while(!__rtc_write_ready()); \ 4633 REG_RTC_RSAR = v; \ 4634 }while(0) 4635 4636 #define __rtc_RGR_is_locked() \ 4637 do{ \ 4638 while(!__rtc_write_ready()); \ 4639 REG_RTC_RGR >> RTC_RGR_LOCK; \ 4640 }while(0) 4641 #define __rtc_lock_RGR() \ 4642 do{ \ 4643 while(!__rtc_write_ready()); \ 4644 REG_RTC_RGR |= RTC_RGR_LOCK; \ 4645 }while(0) 4646 4647 #define __rtc_unlock_RGR() \ 4648 do{ \ 4649 while(!__rtc_write_ready()); \ 4650 REG_RTC_RGR &= ~RTC_RGR_LOCK; \ 4651 }while(0) 4652 4653 #define __rtc_get_adjc_val() \ 4654 do{ \ 4655 while(!__rtc_write_ready()); \ 4656 ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \ 4657 }while(0) 4658 #define __rtc_set_adjc_val(v) \ 4659 do{ \ 4660 while(!__rtc_write_ready()); \ 4661 ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) )) \ 4662 }while(0) 4663 4664 #define __rtc_get_nc1Hz_val() \ 4665 while(!__rtc_write_ready()); \ 4666 ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT ) 4667 4668 #define __rtc_set_nc1Hz_val(v) \ 4669 do{ \ 4670 while(!__rtc_write_ready()); \ 4671 ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) )) \ 4672 }while(0) 4673 #define __rtc_power_down() \ 4674 do{ \ 4675 while(!__rtc_write_ready()); \ 4676 REG_RTC_HCR |= RTC_HCR_PD; \ 4677 }while(0) 4678 4679 #define __rtc_get_hwfcr_val() \ 4680 do{ \ 4681 while(!__rtc_write_ready()); \ 4682 REG_RTC_HWFCR & RTC_HWFCR_MASK; \ 4683 }while(0) 4684 #define __rtc_set_hwfcr_val(v) \ 4685 do{ \ 4686 while(!__rtc_write_ready()); \ 4687 REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \ 4688 }while(0) 4689 4690 #define __rtc_get_hrcr_val() \ 4691 do{ \ 4692 while(!__rtc_write_ready()); \ 4693 ( REG_RTC_HRCR & RTC_HRCR_MASK ); \ 4694 }while(0) 4695 #define __rtc_set_hrcr_val(v) \ 4696 do{ \ 4697 while(!__rtc_write_ready()); \ 4698 ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \ 4699 }while(0) 4700 4701 #define __rtc_enable_alarm_wakeup() \ 4702 do{ \ 4703 while(!__rtc_write_ready()); \ 4704 ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \ 4705 }while(0) 4706 4707 #define __rtc_disable_alarm_wakeup() \ 4708 do{ \ 4709 while(!__rtc_write_ready()); \ 4710 ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \ 4711 }while(0) 4712 4713 #define __rtc_status_hib_reset_occur() \ 4714 do{ \ 4715 while(!__rtc_write_ready()); \ 4716 ( (REG_RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 ); \ 4717 }while(0) 4718 #define __rtc_status_ppr_reset_occur() \ 4719 do{ \ 4720 while(!__rtc_write_ready()); \ 4721 ( (REG_RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 ); \ 4722 }while(0) 4723 #define __rtc_status_wakeup_pin_waken_up() \ 4724 do{ \ 4725 while(!__rtc_write_ready()); \ 4726 ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \ 4727 }while(0) 4728 #define __rtc_status_alarm_waken_up() \ 4729 do{ \ 4730 while(!__rtc_write_ready()); \ 4731 ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \ 4732 }while(0) 4733 #define __rtc_clear_hib_stat_all() \ 4734 do{ \ 4735 while(!__rtc_write_ready()); \ 4736 ( REG_RTC_HWRSR = 0 ); \ 4737 }while(0) 4738 4739 #define __rtc_get_scratch_pattern() \ 4740 while(!__rtc_write_ready()); \ 4741 (REG_RTC_HSPR) 4742 #define __rtc_set_scratch_pattern(n) \ 4743 do{ \ 4744 while(!__rtc_write_ready()); \ 4745 (REG_RTC_HSPR = n ); \ 4746 }while(0) 4747 4748 4749 #endif /* !__ASSEMBLY__ */ 4750 4751 #endif /* __JZ4740_H__ */