1 /* 2 * U-Boot and JzRISC LCD controller definitions 3 * 4 * Copyright (C) 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * Copyright (C) 2005-2007, Ingenic Semiconductor Inc. 6 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> 7 * Copyright (C) 2015, 2016, 2017 Paul Boddie <paul@boddie.org.uk> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 22 * Boston, MA 02110-1301, USA 23 */ 24 25 #ifndef __JZLCD_H__ 26 #define __JZLCD_H__ 27 28 #include <stdint.h> 29 30 /* Framebuffer characteristics. */ 31 32 struct jzfb_info { 33 uint32_t cfg; /* panel mode and pin usage etc. */ 34 uint16_t w; /* display width in pixels */ 35 uint16_t h; /* display height in pixels */ 36 uint8_t bpp; /* bits per pixel */ 37 uint32_t fclk; /* frame clock */ 38 uint32_t hsw; /* hsync width, in pixel clock */ 39 uint32_t vsw; /* vsync width, in line count */ 40 uint32_t elw; /* end of line, in pixel clock */ 41 uint32_t blw; /* begin of line, in pixel clock */ 42 uint32_t efw; /* end of frame, in line count */ 43 uint32_t bfw; /* begin of frame, in line count */ 44 }; 45 46 /* LCD controller stucture for jz4740. */ 47 48 struct jz_fb_dma_descriptor { 49 struct jz_fb_dma_descriptor *fdadr; /* frame descriptor address register */ 50 uint32_t fsadr; /* frame source address register */ 51 uint32_t fidr; /* frame identifier register */ 52 uint32_t ldcmd; /* command register */ 53 }; 54 55 /* Framebuffer and controller memory information. */ 56 57 struct jz_mem_info { 58 59 /* DMA descriptor references (updated for transfers). */ 60 61 struct jz_fb_dma_descriptor *fdadr0; /* physical address of frame descriptor */ 62 struct jz_fb_dma_descriptor *fdadr1; /* physical address of frame/palette descriptor */ 63 64 /* DMA descriptor references (indicating allocated regions). */ 65 66 struct jz_fb_dma_descriptor *dmadesc_fb0; 67 struct jz_fb_dma_descriptor *dmadesc_fb1; 68 struct jz_fb_dma_descriptor *dmadesc_palette; 69 70 uint32_t screen; /* address of first frame buffer (base of memory used) */ 71 uint32_t palette; /* address of palette memory */ 72 uint32_t total; /* total memory used */ 73 }; 74 75 /* Display characteristics and memory resources. */ 76 77 typedef struct vidinfo { 78 struct jzfb_info *jz_fb; /* framebuffer and panel properties */ 79 struct jz_mem_info jz_mem; /* framebuffer memory information */ 80 void *lcd; /* address of LCD controller registers */ 81 } vidinfo_t; 82 83 /* Public functions. */ 84 85 uint32_t jz4740_lcd_get_total_size(vidinfo_t *vid); 86 uint32_t jz4740_lcd_get_pixel_clock(vidinfo_t *vid); 87 void jz4740_lcd_ctrl_init(void *lcd_base, void *fb_vaddr, vidinfo_t *vid); 88 void jz4740_lcd_hw_init(vidinfo_t *vid); 89 void jz4740_lcd_dma_init(vidinfo_t *vid); 90 void lcd_set_bpp(uint8_t bpp); 91 uint32_t lcd_ctrl_init(); 92 void lcd_enable(); 93 void lcd_disable(); 94 95 /* Alignment/rounding macros. */ 96 97 #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) 98 #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) 99 100 /* Transfer and display types. */ 101 102 #define MODE_MASK 0x0f 103 #define MODE_TFT_GEN 0x00 104 #define MODE_TFT_SHARP 0x01 105 #define MODE_TFT_CASIO 0x02 106 #define MODE_TFT_SAMSUNG 0x03 107 #define MODE_CCIR656_NONINT 0x04 108 #define MODE_CCIR656_INT 0x05 109 #define MODE_STN_COLOR_SINGLE 0x08 110 #define MODE_STN_MONO_SINGLE 0x09 111 #define MODE_STN_COLOR_DUAL 0x0a 112 #define MODE_STN_MONO_DUAL 0x0b 113 #define MODE_8BIT_SERIAL_TFT 0x0c 114 115 #define MODE_TFT_18BIT (1<<7) 116 117 #define STN_DAT_PIN1 (0x00 << 4) 118 #define STN_DAT_PIN2 (0x01 << 4) 119 #define STN_DAT_PIN4 (0x02 << 4) 120 #define STN_DAT_PIN8 (0x03 << 4) 121 #define STN_DAT_PINMASK STN_DAT_PIN8 122 123 #define STFT_PSHI (1 << 15) 124 #define STFT_CLSHI (1 << 14) 125 #define STFT_SPLHI (1 << 13) 126 #define STFT_REVHI (1 << 12) 127 128 #define SYNC_MASTER (0 << 16) 129 #define SYNC_SLAVE (1 << 16) 130 131 #define DE_P (0 << 9) 132 #define DE_N (1 << 9) 133 134 #define PCLK_P (0 << 10) 135 #define PCLK_N (1 << 10) 136 137 #define HSYNC_P (0 << 11) 138 #define HSYNC_N (1 << 11) 139 140 #define VSYNC_P (0 << 8) 141 #define VSYNC_N (1 << 8) 142 143 #define DATA_NORMAL (0 << 17) 144 #define DATA_INVERSE (1 << 17) 145 146 /* LCD register base. */ 147 148 #define LCD_BASE_KSEG1 0xB3050000 149 150 /* Register offsets. */ 151 152 #define LCD_CFG 0x00 /* LCD Configure Register */ 153 #define LCD_VSYNC 0x04 /* Vertical Synchronize Register */ 154 #define LCD_HSYNC 0x08 /* Horizontal Synchronize Register */ 155 #define LCD_VAT 0x0c /* Virtual Area Setting Register */ 156 #define LCD_DAH 0x10 /* Display Area Horizontal Start/End Point */ 157 #define LCD_DAV 0x14 /* Display Area Vertical Start/End Point */ 158 #define LCD_PS 0x18 /* PS Signal Setting */ 159 #define LCD_CLS 0x1c /* CLS Signal Setting */ 160 #define LCD_SPL 0x20 /* SPL Signal Setting */ 161 #define LCD_REV 0x24 /* REV Signal Setting */ 162 #define LCD_CTRL 0x30 /* LCD Control Register */ 163 #define LCD_STATE 0x34 /* LCD Status Register */ 164 #define LCD_IID 0x38 /* Interrupt ID Register */ 165 #define LCD_DA0 0x40 /* Descriptor Address Register 0 */ 166 #define LCD_SA0 0x44 /* Source Address Register 0 */ 167 #define LCD_FID0 0x48 /* Frame ID Register 0 */ 168 #define LCD_CMD0 0x4c /* DMA Command Register 0 */ 169 #define LCD_DA1 0x50 /* Descriptor Address Register 1 */ 170 #define LCD_SA1 0x54 /* Source Address Register 1 */ 171 #define LCD_FID1 0x58 /* Frame ID Register 1 */ 172 #define LCD_CMD1 0x5c /* DMA Command Register 1 */ 173 174 /* Palette buffer (LCD_CMDx.PAL). */ 175 176 #define LCD_CMD_PAL (1 << 28) 177 178 #endif /* __JZLCD_H__ */