1 /* 2 * Include file for Ingenic Semiconductor's JZ4740 CPU. 3 * 4 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc. 5 * Copyright (C) 2009 Qi Hardware Inc. 6 * Author: Xiangfu Liu <xiangfu@sharism.cc> 7 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 22 * Boston, MA 02110-1301, USA 23 */ 24 #ifndef __JZ4740_H__ 25 #define __JZ4740_H__ 26 27 #include "xburst_types.h" 28 29 /* NOTE: Independent of usbboot parameters. */ 30 31 #define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ 32 #define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */ 33 #define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */ 34 35 /* Boot ROM Specification */ 36 /* NOR Boot config */ 37 #define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */ 38 #define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ 39 #define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ 40 41 /* NAND Boot config */ 42 #define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */ 43 #define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ 44 #define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ 45 #define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */ 46 47 48 /* Register Definitions */ 49 #define CPM_BASE 0xB0000000 50 #define INTC_BASE 0xB0001000 51 #define TCU_BASE 0xB0002000 52 #define WDT_BASE 0xB0002000 53 #define RTC_BASE 0xB0003000 54 #define GPIO_BASE 0xB0010000 55 #define AIC_BASE 0xB0020000 56 #define ICDC_BASE 0xB0020000 57 #define MSC_BASE 0xB0021000 58 #define UART0_BASE 0xB0030000 59 #define I2C_BASE 0xB0042000 60 #define SSI_BASE 0xB0043000 61 #define SADC_BASE 0xB0070000 62 #define EMC_BASE 0xB3010000 63 #define DMAC_BASE 0xB3020000 64 #define UHC_BASE 0xB3030000 65 #define UDC_BASE 0xB3040000 66 #define LCD_BASE 0xB3050000 67 #define SLCD_BASE 0xB3050000 68 #define CIM_BASE 0xB3060000 69 #define ETH_BASE 0xB3100000 70 71 72 /* 73 * INTC (Interrupt Controller) 74 */ 75 #define INTC_ISR (INTC_BASE + 0x00) 76 #define INTC_IMR (INTC_BASE + 0x04) 77 #define INTC_IMSR (INTC_BASE + 0x08) 78 #define INTC_IMCR (INTC_BASE + 0x0c) 79 #define INTC_IPR (INTC_BASE + 0x10) 80 81 #define REG_INTC_ISR REG32(INTC_ISR) 82 #define REG_INTC_IMR REG32(INTC_IMR) 83 #define REG_INTC_IMSR REG32(INTC_IMSR) 84 #define REG_INTC_IMCR REG32(INTC_IMCR) 85 #define REG_INTC_IPR REG32(INTC_IPR) 86 87 /* 1st-level interrupts */ 88 #define IRQ_I2C 1 89 #define IRQ_UHC 3 90 #define IRQ_UART0 9 91 #define IRQ_SADC 12 92 #define IRQ_MSC 14 93 #define IRQ_RTC 15 94 #define IRQ_SSI 16 95 #define IRQ_CIM 17 96 #define IRQ_AIC 18 97 #define IRQ_ETH 19 98 #define IRQ_DMAC 20 99 #define IRQ_TCU2 21 100 #define IRQ_TCU1 22 101 #define IRQ_TCU0 23 102 #define IRQ_UDC 24 103 #define IRQ_GPIO3 25 104 #define IRQ_GPIO2 26 105 #define IRQ_GPIO1 27 106 #define IRQ_GPIO0 28 107 #define IRQ_IPU 29 108 #define IRQ_LCD 30 109 110 /* 2nd-level interrupts */ 111 #define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ 112 #define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ 113 114 115 /* 116 * RTC 117 */ 118 #define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */ 119 #define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */ 120 #define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */ 121 #define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */ 122 123 #define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */ 124 #define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */ 125 #define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */ 126 #define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ 127 #define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ 128 #define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */ 129 130 #define REG_RTC_RCR REG32(RTC_RCR) 131 #define REG_RTC_RSR REG32(RTC_RSR) 132 #define REG_RTC_RSAR REG32(RTC_RSAR) 133 #define REG_RTC_RGR REG32(RTC_RGR) 134 #define REG_RTC_HCR REG32(RTC_HCR) 135 #define REG_RTC_HWFCR REG32(RTC_HWFCR) 136 #define REG_RTC_HRCR REG32(RTC_HRCR) 137 #define REG_RTC_HWCR REG32(RTC_HWCR) 138 #define REG_RTC_HWRSR REG32(RTC_HWRSR) 139 #define REG_RTC_HSPR REG32(RTC_HSPR) 140 141 /* RTC Control Register */ 142 #define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ 143 #define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */ 144 #define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */ 145 #define RTC_RCR_AF (1 << 4) /* Alarm Flag */ 146 #define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */ 147 #define RTC_RCR_AE (1 << 2) /* Alarm Enable */ 148 #define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ 149 150 /* RTC Regulator Register */ 151 #define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ 152 #define RTC_RGR_ADJC_BIT 16 153 #define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) 154 #define RTC_RGR_NC1HZ_BIT 0 155 #define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) 156 157 /* Hibernate Control Register */ 158 #define RTC_HCR_PD (1 << 0) /* Power Down */ 159 160 /* Hibernate Wakeup Filter Counter Register */ 161 #define RTC_HWFCR_BIT 5 162 #define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT) 163 164 /* Hibernate Reset Counter Register */ 165 #define RTC_HRCR_BIT 5 166 #define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) 167 168 /* Hibernate Wakeup Control Register */ 169 #define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */ 170 171 /* Hibernate Wakeup Status Register */ 172 #define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */ 173 #define RTC_HWRSR_PPR (1 << 4) /* PPR reset */ 174 #define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */ 175 #define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */ 176 177 /************************************************************************* 178 * CPM (Clock reset and Power control Management) 179 *************************************************************************/ 180 181 /* Register definitions with absolute positioning have been removed. */ 182 183 #define CPM_CPCCR (CPM_BASE+0x00) 184 #define CPM_CPPCR (CPM_BASE+0x10) 185 #define CPM_I2SCDR (CPM_BASE+0x60) 186 #define CPM_LPCDR (CPM_BASE+0x64) 187 #define CPM_MSCCDR (CPM_BASE+0x68) 188 #define CPM_UHCCDR (CPM_BASE+0x6C) 189 190 #define CPM_LCR (CPM_BASE+0x04) 191 #define CPM_CLKGR (CPM_BASE+0x20) 192 #define CPM_SCR (CPM_BASE+0x24) 193 194 #define CPM_HCR (CPM_BASE+0x30) 195 #define CPM_HWFCR (CPM_BASE+0x34) 196 #define CPM_HRCR (CPM_BASE+0x38) 197 #define CPM_HWCR (CPM_BASE+0x3c) 198 #define CPM_HWSR (CPM_BASE+0x40) 199 #define CPM_HSPR (CPM_BASE+0x44) 200 201 #define CPM_RSR (CPM_BASE+0x08) 202 203 204 #define REG_CPM_CPCCR REG32(CPM_CPCCR) 205 #define REG_CPM_CPPCR REG32(CPM_CPPCR) 206 #define REG_CPM_I2SCDR REG32(CPM_I2SCDR) 207 #define REG_CPM_LPCDR REG32(CPM_LPCDR) 208 #define REG_CPM_MSCCDR REG32(CPM_MSCCDR) 209 #define REG_CPM_UHCCDR REG32(CPM_UHCCDR) 210 211 #define REG_CPM_LCR REG32(CPM_LCR) 212 #define REG_CPM_CLKGR REG32(CPM_CLKGR) 213 #define REG_CPM_SCR REG32(CPM_SCR) 214 #define REG_CPM_HCR REG32(CPM_HCR) 215 #define REG_CPM_HWFCR REG32(CPM_HWFCR) 216 #define REG_CPM_HRCR REG32(CPM_HRCR) 217 #define REG_CPM_HWCR REG32(CPM_HWCR) 218 #define REG_CPM_HWSR REG32(CPM_HWSR) 219 #define REG_CPM_HSPR REG32(CPM_HSPR) 220 221 #define REG_CPM_RSR REG32(CPM_RSR) 222 223 224 /* Clock Control Register */ 225 #define CPM_CPCCR_I2CS (1 << 31) 226 #define CPM_CPCCR_CLKOEN (1 << 30) 227 #define CPM_CPCCR_UCS (1 << 29) 228 #define CPM_CPCCR_UDIV_BIT 23 229 #define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT) 230 #define CPM_CPCCR_CE (1 << 22) 231 #define CPM_CPCCR_PCS (1 << 21) 232 #define CPM_CPCCR_LDIV_BIT 16 233 #define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT) 234 #define CPM_CPCCR_MDIV_BIT 12 235 #define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT) 236 #define CPM_CPCCR_PDIV_BIT 8 237 #define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT) 238 #define CPM_CPCCR_HDIV_BIT 4 239 #define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT) 240 #define CPM_CPCCR_CDIV_BIT 0 241 #define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) 242 243 /* I2S Clock Divider Register */ 244 #define CPM_I2SCDR_I2SDIV_BIT 0 245 #define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) 246 247 /* LCD Pixel Clock Divider Register */ 248 #define CPM_LPCDR_PIXDIV_BIT 0 249 #define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT) 250 251 /* MSC Clock Divider Register */ 252 #define CPM_MSCCDR_MSCDIV_BIT 0 253 #define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT) 254 255 /* PLL Control Register */ 256 #define CPM_CPPCR_PLLM_BIT 23 257 #define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT) 258 #define CPM_CPPCR_PLLN_BIT 18 259 #define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT) 260 #define CPM_CPPCR_PLLOD_BIT 16 261 #define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) 262 #define CPM_CPPCR_PLLS (1 << 10) 263 #define CPM_CPPCR_PLLBP (1 << 9) 264 #define CPM_CPPCR_PLLEN (1 << 8) 265 #define CPM_CPPCR_PLLST_BIT 0 266 #define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) 267 268 /* Low Power Control Register */ 269 #define CPM_LCR_DOZE_DUTY_BIT 3 270 #define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) 271 #define CPM_LCR_DOZE_ON (1 << 2) 272 #define CPM_LCR_LPM_BIT 0 273 #define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) 274 #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) 275 #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) 276 277 /* Clock Gate Register */ 278 #define CPM_CLKGR_UART1 (1 << 15) 279 #define CPM_CLKGR_UHC (1 << 14) 280 #define CPM_CLKGR_IPU (1 << 13) 281 #define CPM_CLKGR_DMAC (1 << 12) 282 #define CPM_CLKGR_UDC (1 << 11) 283 #define CPM_CLKGR_LCD (1 << 10) 284 #define CPM_CLKGR_CIM (1 << 9) 285 #define CPM_CLKGR_SADC (1 << 8) 286 #define CPM_CLKGR_MSC (1 << 7) 287 #define CPM_CLKGR_AIC1 (1 << 6) 288 #define CPM_CLKGR_AIC2 (1 << 5) 289 #define CPM_CLKGR_SSI (1 << 4) 290 #define CPM_CLKGR_I2C (1 << 3) 291 #define CPM_CLKGR_RTC (1 << 2) 292 #define CPM_CLKGR_TCU (1 << 1) 293 #define CPM_CLKGR_UART0 (1 << 0) 294 295 /* Sleep Control Register */ 296 #define CPM_SCR_O1ST_BIT 8 297 #define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) 298 #define CPM_SCR_UDCPHY_ENABLE (1 << 6) 299 #define CPM_SCR_USBPHY_DISABLE (1 << 7) 300 #define CPM_SCR_OSC_ENABLE (1 << 4) 301 302 /* Hibernate Control Register */ 303 #define CPM_HCR_PD (1 << 0) 304 305 /* Wakeup Filter Counter Register in Hibernate Mode */ 306 #define CPM_HWFCR_TIME_BIT 0 307 #define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT) 308 309 /* Reset Counter Register in Hibernate Mode */ 310 #define CPM_HRCR_TIME_BIT 0 311 #define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT) 312 313 /* Wakeup Control Register in Hibernate Mode */ 314 #define CPM_HWCR_WLE_LOW (0 << 2) 315 #define CPM_HWCR_WLE_HIGH (1 << 2) 316 #define CPM_HWCR_PIN_WAKEUP (1 << 1) 317 #define CPM_HWCR_RTC_WAKEUP (1 << 0) 318 319 /* Wakeup Status Register in Hibernate Mode */ 320 #define CPM_HWSR_WSR_PIN (1 << 1) 321 #define CPM_HWSR_WSR_RTC (1 << 0) 322 323 /* Reset Status Register */ 324 #define CPM_RSR_HR (1 << 2) 325 #define CPM_RSR_WR (1 << 1) 326 #define CPM_RSR_PR (1 << 0) 327 328 329 /************************************************************************* 330 * TCU (Timer Counter Unit) 331 *************************************************************************/ 332 #define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */ 333 #define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */ 334 #define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */ 335 #define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */ 336 #define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */ 337 #define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */ 338 #define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */ 339 #define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */ 340 #define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */ 341 #define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */ 342 #define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */ 343 #define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */ 344 #define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */ 345 #define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */ 346 #define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */ 347 #define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */ 348 #define TCU_TDFR1 (TCU_BASE + 0x50) 349 #define TCU_TDHR1 (TCU_BASE + 0x54) 350 #define TCU_TCNT1 (TCU_BASE + 0x58) 351 #define TCU_TCSR1 (TCU_BASE + 0x5C) 352 #define TCU_TDFR2 (TCU_BASE + 0x60) 353 #define TCU_TDHR2 (TCU_BASE + 0x64) 354 #define TCU_TCNT2 (TCU_BASE + 0x68) 355 #define TCU_TCSR2 (TCU_BASE + 0x6C) 356 #define TCU_TDFR3 (TCU_BASE + 0x70) 357 #define TCU_TDHR3 (TCU_BASE + 0x74) 358 #define TCU_TCNT3 (TCU_BASE + 0x78) 359 #define TCU_TCSR3 (TCU_BASE + 0x7C) 360 #define TCU_TDFR4 (TCU_BASE + 0x80) 361 #define TCU_TDHR4 (TCU_BASE + 0x84) 362 #define TCU_TCNT4 (TCU_BASE + 0x88) 363 #define TCU_TCSR4 (TCU_BASE + 0x8C) 364 #define TCU_TDFR5 (TCU_BASE + 0x90) 365 #define TCU_TDHR5 (TCU_BASE + 0x94) 366 #define TCU_TCNT5 (TCU_BASE + 0x98) 367 #define TCU_TCSR5 (TCU_BASE + 0x9C) 368 369 #define REG_TCU_TSR REG32(TCU_TSR) 370 #define REG_TCU_TSSR REG32(TCU_TSSR) 371 #define REG_TCU_TSCR REG32(TCU_TSCR) 372 #define REG_TCU_TER REG8(TCU_TER) 373 #define REG_TCU_TESR REG8(TCU_TESR) 374 #define REG_TCU_TECR REG8(TCU_TECR) 375 #define REG_TCU_TFR REG32(TCU_TFR) 376 #define REG_TCU_TFSR REG32(TCU_TFSR) 377 #define REG_TCU_TFCR REG32(TCU_TFCR) 378 #define REG_TCU_TMR REG32(TCU_TMR) 379 #define REG_TCU_TMSR REG32(TCU_TMSR) 380 #define REG_TCU_TMCR REG32(TCU_TMCR) 381 #define REG_TCU_TDFR0 REG16(TCU_TDFR0) 382 #define REG_TCU_TDHR0 REG16(TCU_TDHR0) 383 #define REG_TCU_TCNT0 REG16(TCU_TCNT0) 384 #define REG_TCU_TCSR0 REG16(TCU_TCSR0) 385 #define REG_TCU_TDFR1 REG16(TCU_TDFR1) 386 #define REG_TCU_TDHR1 REG16(TCU_TDHR1) 387 #define REG_TCU_TCNT1 REG16(TCU_TCNT1) 388 #define REG_TCU_TCSR1 REG16(TCU_TCSR1) 389 #define REG_TCU_TDFR2 REG16(TCU_TDFR2) 390 #define REG_TCU_TDHR2 REG16(TCU_TDHR2) 391 #define REG_TCU_TCNT2 REG16(TCU_TCNT2) 392 #define REG_TCU_TCSR2 REG16(TCU_TCSR2) 393 #define REG_TCU_TDFR3 REG16(TCU_TDFR3) 394 #define REG_TCU_TDHR3 REG16(TCU_TDHR3) 395 #define REG_TCU_TCNT3 REG16(TCU_TCNT3) 396 #define REG_TCU_TCSR3 REG16(TCU_TCSR3) 397 #define REG_TCU_TDFR4 REG16(TCU_TDFR4) 398 #define REG_TCU_TDHR4 REG16(TCU_TDHR4) 399 #define REG_TCU_TCNT4 REG16(TCU_TCNT4) 400 #define REG_TCU_TCSR4 REG16(TCU_TCSR4) 401 402 /* n = 0,1,2,3,4,5 */ 403 #define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */ 404 #define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */ 405 #define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */ 406 #define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */ 407 408 #define REG_TCU_TDFR(n) REG16(TCU_TDFR((n))) 409 #define REG_TCU_TDHR(n) REG16(TCU_TDHR((n))) 410 #define REG_TCU_TCNT(n) REG16(TCU_TCNT((n))) 411 #define REG_TCU_TCSR(n) REG16(TCU_TCSR((n))) 412 413 /* Register definitions */ 414 #define TCU_TCSR_PWM_SD (1 << 9) 415 #define TCU_TCSR_PWM_INITL_HIGH (1 << 8) 416 #define TCU_TCSR_PWM_EN (1 << 7) 417 #define TCU_TCSR_PRESCALE_BIT 3 418 #define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) 419 #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) 420 #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) 421 #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) 422 #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) 423 #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) 424 #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) 425 #define TCU_TCSR_EXT_EN (1 << 2) 426 #define TCU_TCSR_RTC_EN (1 << 1) 427 #define TCU_TCSR_PCK_EN (1 << 0) 428 429 #define TCU_TER_TCEN5 (1 << 5) 430 #define TCU_TER_TCEN4 (1 << 4) 431 #define TCU_TER_TCEN3 (1 << 3) 432 #define TCU_TER_TCEN2 (1 << 2) 433 #define TCU_TER_TCEN1 (1 << 1) 434 #define TCU_TER_TCEN0 (1 << 0) 435 436 #define TCU_TESR_TCST5 (1 << 5) 437 #define TCU_TESR_TCST4 (1 << 4) 438 #define TCU_TESR_TCST3 (1 << 3) 439 #define TCU_TESR_TCST2 (1 << 2) 440 #define TCU_TESR_TCST1 (1 << 1) 441 #define TCU_TESR_TCST0 (1 << 0) 442 443 #define TCU_TECR_TCCL5 (1 << 5) 444 #define TCU_TECR_TCCL4 (1 << 4) 445 #define TCU_TECR_TCCL3 (1 << 3) 446 #define TCU_TECR_TCCL2 (1 << 2) 447 #define TCU_TECR_TCCL1 (1 << 1) 448 #define TCU_TECR_TCCL0 (1 << 0) 449 450 #define TCU_TFR_HFLAG5 (1 << 21) 451 #define TCU_TFR_HFLAG4 (1 << 20) 452 #define TCU_TFR_HFLAG3 (1 << 19) 453 #define TCU_TFR_HFLAG2 (1 << 18) 454 #define TCU_TFR_HFLAG1 (1 << 17) 455 #define TCU_TFR_HFLAG0 (1 << 16) 456 #define TCU_TFR_FFLAG5 (1 << 5) 457 #define TCU_TFR_FFLAG4 (1 << 4) 458 #define TCU_TFR_FFLAG3 (1 << 3) 459 #define TCU_TFR_FFLAG2 (1 << 2) 460 #define TCU_TFR_FFLAG1 (1 << 1) 461 #define TCU_TFR_FFLAG0 (1 << 0) 462 463 #define TCU_TFSR_HFLAG5 (1 << 21) 464 #define TCU_TFSR_HFLAG4 (1 << 20) 465 #define TCU_TFSR_HFLAG3 (1 << 19) 466 #define TCU_TFSR_HFLAG2 (1 << 18) 467 #define TCU_TFSR_HFLAG1 (1 << 17) 468 #define TCU_TFSR_HFLAG0 (1 << 16) 469 #define TCU_TFSR_FFLAG5 (1 << 5) 470 #define TCU_TFSR_FFLAG4 (1 << 4) 471 #define TCU_TFSR_FFLAG3 (1 << 3) 472 #define TCU_TFSR_FFLAG2 (1 << 2) 473 #define TCU_TFSR_FFLAG1 (1 << 1) 474 #define TCU_TFSR_FFLAG0 (1 << 0) 475 476 #define TCU_TFCR_HFLAG5 (1 << 21) 477 #define TCU_TFCR_HFLAG4 (1 << 20) 478 #define TCU_TFCR_HFLAG3 (1 << 19) 479 #define TCU_TFCR_HFLAG2 (1 << 18) 480 #define TCU_TFCR_HFLAG1 (1 << 17) 481 #define TCU_TFCR_HFLAG0 (1 << 16) 482 #define TCU_TFCR_FFLAG5 (1 << 5) 483 #define TCU_TFCR_FFLAG4 (1 << 4) 484 #define TCU_TFCR_FFLAG3 (1 << 3) 485 #define TCU_TFCR_FFLAG2 (1 << 2) 486 #define TCU_TFCR_FFLAG1 (1 << 1) 487 #define TCU_TFCR_FFLAG0 (1 << 0) 488 489 #define TCU_TMR_HMASK5 (1 << 21) 490 #define TCU_TMR_HMASK4 (1 << 20) 491 #define TCU_TMR_HMASK3 (1 << 19) 492 #define TCU_TMR_HMASK2 (1 << 18) 493 #define TCU_TMR_HMASK1 (1 << 17) 494 #define TCU_TMR_HMASK0 (1 << 16) 495 #define TCU_TMR_FMASK5 (1 << 5) 496 #define TCU_TMR_FMASK4 (1 << 4) 497 #define TCU_TMR_FMASK3 (1 << 3) 498 #define TCU_TMR_FMASK2 (1 << 2) 499 #define TCU_TMR_FMASK1 (1 << 1) 500 #define TCU_TMR_FMASK0 (1 << 0) 501 502 #define TCU_TMSR_HMST5 (1 << 21) 503 #define TCU_TMSR_HMST4 (1 << 20) 504 #define TCU_TMSR_HMST3 (1 << 19) 505 #define TCU_TMSR_HMST2 (1 << 18) 506 #define TCU_TMSR_HMST1 (1 << 17) 507 #define TCU_TMSR_HMST0 (1 << 16) 508 #define TCU_TMSR_FMST5 (1 << 5) 509 #define TCU_TMSR_FMST4 (1 << 4) 510 #define TCU_TMSR_FMST3 (1 << 3) 511 #define TCU_TMSR_FMST2 (1 << 2) 512 #define TCU_TMSR_FMST1 (1 << 1) 513 #define TCU_TMSR_FMST0 (1 << 0) 514 515 #define TCU_TMCR_HMCL5 (1 << 21) 516 #define TCU_TMCR_HMCL4 (1 << 20) 517 #define TCU_TMCR_HMCL3 (1 << 19) 518 #define TCU_TMCR_HMCL2 (1 << 18) 519 #define TCU_TMCR_HMCL1 (1 << 17) 520 #define TCU_TMCR_HMCL0 (1 << 16) 521 #define TCU_TMCR_FMCL5 (1 << 5) 522 #define TCU_TMCR_FMCL4 (1 << 4) 523 #define TCU_TMCR_FMCL3 (1 << 3) 524 #define TCU_TMCR_FMCL2 (1 << 2) 525 #define TCU_TMCR_FMCL1 (1 << 1) 526 #define TCU_TMCR_FMCL0 (1 << 0) 527 528 #define TCU_TSR_WDTS (1 << 16) 529 #define TCU_TSR_STOP5 (1 << 5) 530 #define TCU_TSR_STOP4 (1 << 4) 531 #define TCU_TSR_STOP3 (1 << 3) 532 #define TCU_TSR_STOP2 (1 << 2) 533 #define TCU_TSR_STOP1 (1 << 1) 534 #define TCU_TSR_STOP0 (1 << 0) 535 536 #define TCU_TSSR_WDTSS (1 << 16) 537 #define TCU_TSSR_STPS5 (1 << 5) 538 #define TCU_TSSR_STPS4 (1 << 4) 539 #define TCU_TSSR_STPS3 (1 << 3) 540 #define TCU_TSSR_STPS2 (1 << 2) 541 #define TCU_TSSR_STPS1 (1 << 1) 542 #define TCU_TSSR_STPS0 (1 << 0) 543 544 #define TCU_TSSR_WDTSC (1 << 16) 545 #define TCU_TSSR_STPC5 (1 << 5) 546 #define TCU_TSSR_STPC4 (1 << 4) 547 #define TCU_TSSR_STPC3 (1 << 3) 548 #define TCU_TSSR_STPC2 (1 << 2) 549 #define TCU_TSSR_STPC1 (1 << 1) 550 #define TCU_TSSR_STPC0 (1 << 0) 551 552 553 /* 554 * WDT (WatchDog Timer) 555 */ 556 #define WDT_TDR (WDT_BASE + 0x00) 557 #define WDT_TCER (WDT_BASE + 0x04) 558 #define WDT_TCNT (WDT_BASE + 0x08) 559 #define WDT_TCSR (WDT_BASE + 0x0C) 560 561 #define REG_WDT_TDR REG16(WDT_TDR) 562 #define REG_WDT_TCER REG8(WDT_TCER) 563 #define REG_WDT_TCNT REG16(WDT_TCNT) 564 #define REG_WDT_TCSR REG16(WDT_TCSR) 565 566 /* Register definition */ 567 #define WDT_TCSR_PRESCALE_BIT 3 568 #define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) 569 #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) 570 #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) 571 #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) 572 #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) 573 #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) 574 #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) 575 #define WDT_TCSR_EXT_EN (1 << 2) 576 #define WDT_TCSR_RTC_EN (1 << 1) 577 #define WDT_TCSR_PCK_EN (1 << 0) 578 579 #define WDT_TCER_TCEN (1 << 0) 580 581 582 /* 583 * DMAC (DMA Controller) 584 */ 585 586 #define MAX_DMA_NUM 6 /* max 6 channels */ 587 588 #define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */ 589 #define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */ 590 #define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */ 591 #define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */ 592 #define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */ 593 #define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */ 594 #define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */ 595 #define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */ 596 #define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */ 597 #define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */ 598 #define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */ 599 600 /* channel 0 */ 601 #define DMAC_DSAR0 DMAC_DSAR(0) 602 #define DMAC_DTAR0 DMAC_DTAR(0) 603 #define DMAC_DTCR0 DMAC_DTCR(0) 604 #define DMAC_DRSR0 DMAC_DRSR(0) 605 #define DMAC_DCCSR0 DMAC_DCCSR(0) 606 #define DMAC_DCMD0 DMAC_DCMD(0) 607 #define DMAC_DDA0 DMAC_DDA(0) 608 609 /* channel 1 */ 610 #define DMAC_DSAR1 DMAC_DSAR(1) 611 #define DMAC_DTAR1 DMAC_DTAR(1) 612 #define DMAC_DTCR1 DMAC_DTCR(1) 613 #define DMAC_DRSR1 DMAC_DRSR(1) 614 #define DMAC_DCCSR1 DMAC_DCCSR(1) 615 #define DMAC_DCMD1 DMAC_DCMD(1) 616 #define DMAC_DDA1 DMAC_DDA(1) 617 618 /* channel 2 */ 619 #define DMAC_DSAR2 DMAC_DSAR(2) 620 #define DMAC_DTAR2 DMAC_DTAR(2) 621 #define DMAC_DTCR2 DMAC_DTCR(2) 622 #define DMAC_DRSR2 DMAC_DRSR(2) 623 #define DMAC_DCCSR2 DMAC_DCCSR(2) 624 #define DMAC_DCMD2 DMAC_DCMD(2) 625 #define DMAC_DDA2 DMAC_DDA(2) 626 627 /* channel 3 */ 628 #define DMAC_DSAR3 DMAC_DSAR(3) 629 #define DMAC_DTAR3 DMAC_DTAR(3) 630 #define DMAC_DTCR3 DMAC_DTCR(3) 631 #define DMAC_DRSR3 DMAC_DRSR(3) 632 #define DMAC_DCCSR3 DMAC_DCCSR(3) 633 #define DMAC_DCMD3 DMAC_DCMD(3) 634 #define DMAC_DDA3 DMAC_DDA(3) 635 636 /* channel 4 */ 637 #define DMAC_DSAR4 DMAC_DSAR(4) 638 #define DMAC_DTAR4 DMAC_DTAR(4) 639 #define DMAC_DTCR4 DMAC_DTCR(4) 640 #define DMAC_DRSR4 DMAC_DRSR(4) 641 #define DMAC_DCCSR4 DMAC_DCCSR(4) 642 #define DMAC_DCMD4 DMAC_DCMD(4) 643 #define DMAC_DDA4 DMAC_DDA(4) 644 645 /* channel 5 */ 646 #define DMAC_DSAR5 DMAC_DSAR(5) 647 #define DMAC_DTAR5 DMAC_DTAR(5) 648 #define DMAC_DTCR5 DMAC_DTCR(5) 649 #define DMAC_DRSR5 DMAC_DRSR(5) 650 #define DMAC_DCCSR5 DMAC_DCCSR(5) 651 #define DMAC_DCMD5 DMAC_DCMD(5) 652 #define DMAC_DDA5 DMAC_DDA(5) 653 654 #define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) 655 #define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n))) 656 #define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) 657 #define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) 658 #define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) 659 #define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n))) 660 #define REG_DMAC_DDA(n) REG32(DMAC_DDA((n))) 661 #define REG_DMAC_DMACR REG32(DMAC_DMACR) 662 #define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR) 663 #define REG_DMAC_DMADBR REG32(DMAC_DMADBR) 664 #define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR) 665 666 /* DMA request source register */ 667 #define DMAC_DRSR_RS_BIT 0 668 #define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) 669 #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) 670 #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) 671 #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) 672 #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) 673 #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) 674 #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) 675 #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) 676 #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) 677 #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) 678 #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT) 679 #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT) 680 #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT) 681 682 /* DMA channel control/status register */ 683 #define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */ 684 #define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */ 685 #define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT) 686 #define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */ 687 #define DMAC_DCCSR_AR (1 << 4) /* address error */ 688 #define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */ 689 #define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */ 690 #define DMAC_DCCSR_CT (1 << 1) /* count terminated */ 691 #define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */ 692 693 /* DMA channel command register */ 694 #define DMAC_DCMD_SAI (1 << 23) /* source address increment */ 695 #define DMAC_DCMD_DAI (1 << 22) /* dest address increment */ 696 #define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */ 697 #define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT) 698 #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT) 699 #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT) 700 #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT) 701 #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT) 702 #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT) 703 #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT) 704 #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT) 705 #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT) 706 #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT) 707 #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT) 708 #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT) 709 #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT) 710 #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT) 711 #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT) 712 #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT) 713 #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT) 714 #define DMAC_DCMD_SWDH_BIT 14 /* source port width */ 715 #define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT) 716 #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT) 717 #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT) 718 #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT) 719 #define DMAC_DCMD_DWDH_BIT 12 /* dest port width */ 720 #define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT) 721 #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT) 722 #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT) 723 #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT) 724 #define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */ 725 #define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT) 726 #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT) 727 #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT) 728 #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT) 729 #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT) 730 #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT) 731 #define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */ 732 #define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */ 733 #define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */ 734 #define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */ 735 #define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */ 736 #define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */ 737 738 /* DMA descriptor address register */ 739 #define DMAC_DDA_BASE_BIT 12 /* descriptor base address */ 740 #define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT) 741 #define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */ 742 #define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT) 743 744 /* DMA control register */ 745 #define DMAC_DMACR_PR_BIT 8 /* channel priority mode */ 746 #define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) 747 #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT) 748 #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT) 749 #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT) 750 #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */ 751 #define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */ 752 #define DMAC_DMACR_AR (1 << 2) /* address error flag */ 753 #define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */ 754 755 /* DMA doorbell register */ 756 #define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */ 757 #define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */ 758 #define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */ 759 #define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */ 760 #define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */ 761 #define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */ 762 763 /* DMA doorbell set register */ 764 #define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */ 765 #define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */ 766 #define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */ 767 #define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */ 768 #define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */ 769 #define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */ 770 771 /* DMA interrupt pending register */ 772 #define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */ 773 #define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */ 774 #define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */ 775 #define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */ 776 #define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */ 777 #define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */ 778 779 780 /************************************************************************* 781 * GPIO (General-Purpose I/O Ports) 782 *************************************************************************/ 783 #define MAX_GPIO_NUM 128 784 785 /* = 0,1,2,3 */ 786 #define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */ 787 #define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */ 788 #define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */ 789 #define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */ 790 #define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */ 791 #define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */ 792 #define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */ 793 #define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */ 794 #define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */ 795 #define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */ 796 #define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */ 797 #define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */ 798 #define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */ 799 #define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */ 800 #define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */ 801 #define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */ 802 #define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */ 803 #define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */ 804 #define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */ 805 #define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */ 806 #define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */ 807 #define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */ 808 #define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */ 809 #define GPIO_PXFLGC(n) (GPIO_BASE + (0x84 + (n)*0x100)) /* Port Flag clear Register */ 810 811 #define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */ 812 #define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */ 813 #define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n))) 814 #define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n))) 815 #define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */ 816 #define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n))) 817 #define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n))) 818 #define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */ 819 #define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n))) 820 #define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n))) 821 #define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */ 822 #define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n))) 823 #define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n))) 824 #define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/ 825 #define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n))) 826 #define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n))) 827 #define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */ 828 #define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n))) 829 #define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n))) 830 #define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */ 831 #define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n))) 832 #define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n))) 833 #define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */ 834 #define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */ 835 836 837 /************************************************************************* 838 * UART 839 *************************************************************************/ 840 841 #define IRDA_BASE UART0_BASE 842 /* #define UART_BASE UART0_BASE */ 843 #define UART_OFF 0x1000 844 845 /* Register Offset */ 846 #define OFF_RDR (0x00) /* R 8b H'xx */ 847 #define OFF_TDR (0x00) /* W 8b H'xx */ 848 #define OFF_DLLR (0x00) /* RW 8b H'00 */ 849 #define OFF_DLHR (0x04) /* RW 8b H'00 */ 850 #define OFF_IER (0x04) /* RW 8b H'00 */ 851 #define OFF_ISR (0x08) /* R 8b H'01 */ 852 #define OFF_FCR (0x08) /* W 8b H'00 */ 853 #define OFF_LCR (0x0C) /* RW 8b H'00 */ 854 #define OFF_MCR (0x10) /* RW 8b H'00 */ 855 #define OFF_LSR (0x14) /* R 8b H'00 */ 856 #define OFF_MSR (0x18) /* R 8b H'00 */ 857 #define OFF_SPR (0x1C) /* RW 8b H'00 */ 858 #define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ 859 #define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */ 860 #define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */ 861 862 /* Register Address */ 863 #define UART0_RDR (UART0_BASE + OFF_RDR) 864 #define UART0_TDR (UART0_BASE + OFF_TDR) 865 #define UART0_DLLR (UART0_BASE + OFF_DLLR) 866 #define UART0_DLHR (UART0_BASE + OFF_DLHR) 867 #define UART0_IER (UART0_BASE + OFF_IER) 868 #define UART0_ISR (UART0_BASE + OFF_ISR) 869 #define UART0_FCR (UART0_BASE + OFF_FCR) 870 #define UART0_LCR (UART0_BASE + OFF_LCR) 871 #define UART0_MCR (UART0_BASE + OFF_MCR) 872 #define UART0_LSR (UART0_BASE + OFF_LSR) 873 #define UART0_MSR (UART0_BASE + OFF_MSR) 874 #define UART0_SPR (UART0_BASE + OFF_SPR) 875 #define UART0_SIRCR (UART0_BASE + OFF_SIRCR) 876 #define UART0_UMR (UART0_BASE + OFF_UMR) 877 #define UART0_UACR (UART0_BASE + OFF_UACR) 878 879 /* 880 * Define macros for UART_IER 881 * UART Interrupt Enable Register 882 */ 883 #define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ 884 #define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ 885 #define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ 886 #define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ 887 #define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ 888 889 /* 890 * Define macros for UART_ISR 891 * UART Interrupt Status Register 892 */ 893 #define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ 894 #define UART_ISR_IID (7 << 1) /* Source of Interrupt */ 895 #define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ 896 #define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ 897 #define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ 898 #define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ 899 #define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */ 900 #define UART_ISR_FFMS_NO_FIFO (0 << 6) 901 #define UART_ISR_FFMS_FIFO_MODE (3 << 6) 902 903 /* 904 * Define macros for UART_FCR 905 * UART FIFO Control Register 906 */ 907 #define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ 908 #define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ 909 #define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ 910 #define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ 911 #define UART_FCR_UUE (1 << 4) /* 0: disable UART */ 912 #define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ 913 #define UART_FCR_RTRG_1 (0 << 6) 914 #define UART_FCR_RTRG_4 (1 << 6) 915 #define UART_FCR_RTRG_8 (2 << 6) 916 #define UART_FCR_RTRG_15 (3 << 6) 917 918 /* 919 * Define macros for UART_LCR 920 * UART Line Control Register 921 */ 922 #define UART_LCR_WLEN (3 << 0) /* word length */ 923 #define UART_LCR_WLEN_5 (0 << 0) 924 #define UART_LCR_WLEN_6 (1 << 0) 925 #define UART_LCR_WLEN_7 (2 << 0) 926 #define UART_LCR_WLEN_8 (3 << 0) 927 #define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 928 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 929 #define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 930 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 931 #define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 932 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 933 934 #define UART_LCR_PE (1 << 3) /* 0: parity disable */ 935 #define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ 936 #define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ 937 #define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ 938 #define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ 939 940 /* 941 * Define macros for UART_LSR 942 * UART Line Status Register 943 */ 944 #define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ 945 #define UART_LSR_ORER (1 << 1) /* 0: no overrun error */ 946 #define UART_LSR_PER (1 << 2) /* 0: no parity error */ 947 #define UART_LSR_FER (1 << 3) /* 0; no framing error */ 948 #define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ 949 #define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ 950 #define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ 951 #define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ 952 953 /* 954 * Define macros for UART_MCR 955 * UART Modem Control Register 956 */ 957 #define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ 958 #define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ 959 #define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */ 960 #define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ 961 #define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ 962 #define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ 963 964 /* 965 * Define macros for UART_MSR 966 * UART Modem Status Register 967 */ 968 #define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */ 969 #define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */ 970 #define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */ 971 #define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */ 972 #define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ 973 #define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ 974 #define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ 975 #define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ 976 977 /* 978 * Define macros for SIRCR 979 * Slow IrDA Control Register 980 */ 981 #define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ 982 #define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ 983 #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length 984 1: 0 pulse width is 1.6us for 115.2Kbps */ 985 #define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ 986 #define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ 987 988 989 /************************************************************************* 990 * AIC (AC97/I2S Controller) 991 *************************************************************************/ 992 #define AIC_FR (AIC_BASE + 0x000) 993 #define AIC_CR (AIC_BASE + 0x004) 994 #define AIC_ACCR1 (AIC_BASE + 0x008) 995 #define AIC_ACCR2 (AIC_BASE + 0x00C) 996 #define AIC_I2SCR (AIC_BASE + 0x010) 997 #define AIC_SR (AIC_BASE + 0x014) 998 #define AIC_ACSR (AIC_BASE + 0x018) 999 #define AIC_I2SSR (AIC_BASE + 0x01C) 1000 #define AIC_ACCAR (AIC_BASE + 0x020) 1001 #define AIC_ACCDR (AIC_BASE + 0x024) 1002 #define AIC_ACSAR (AIC_BASE + 0x028) 1003 #define AIC_ACSDR (AIC_BASE + 0x02C) 1004 #define AIC_I2SDIV (AIC_BASE + 0x030) 1005 #define AIC_DR (AIC_BASE + 0x034) 1006 1007 #define REG_AIC_FR REG32(AIC_FR) 1008 #define REG_AIC_CR REG32(AIC_CR) 1009 #define REG_AIC_ACCR1 REG32(AIC_ACCR1) 1010 #define REG_AIC_ACCR2 REG32(AIC_ACCR2) 1011 #define REG_AIC_I2SCR REG32(AIC_I2SCR) 1012 #define REG_AIC_SR REG32(AIC_SR) 1013 #define REG_AIC_ACSR REG32(AIC_ACSR) 1014 #define REG_AIC_I2SSR REG32(AIC_I2SSR) 1015 #define REG_AIC_ACCAR REG32(AIC_ACCAR) 1016 #define REG_AIC_ACCDR REG32(AIC_ACCDR) 1017 #define REG_AIC_ACSAR REG32(AIC_ACSAR) 1018 #define REG_AIC_ACSDR REG32(AIC_ACSDR) 1019 #define REG_AIC_I2SDIV REG32(AIC_I2SDIV) 1020 #define REG_AIC_DR REG32(AIC_DR) 1021 1022 /* AIC Controller Configuration Register (AIC_FR) */ 1023 1024 #define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */ 1025 #define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) 1026 #define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */ 1027 #define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) 1028 #define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */ 1029 #define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */ 1030 #define AIC_FR_RST (1 << 3) /* AIC registers reset */ 1031 #define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */ 1032 #define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */ 1033 #define AIC_FR_ENB (1 << 0) /* AIC enable bit */ 1034 1035 /* AIC Controller Common Control Register (AIC_CR) */ 1036 1037 #define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */ 1038 #define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT) 1039 #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT) 1040 #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT) 1041 #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT) 1042 #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT) 1043 #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT) 1044 #define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */ 1045 #define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT) 1046 #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT) 1047 #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT) 1048 #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT) 1049 #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT) 1050 #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT) 1051 #define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */ 1052 #define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */ 1053 #define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */ 1054 #define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */ 1055 #define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */ 1056 #define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */ 1057 #define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */ 1058 #define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */ 1059 #define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */ 1060 #define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */ 1061 #define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */ 1062 #define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */ 1063 #define AIC_CR_EREC (1 << 0) /* Enable Record Function */ 1064 1065 /* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ 1066 1067 #define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */ 1068 #define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) 1069 #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ 1070 #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ 1071 #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ 1072 #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */ 1073 #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */ 1074 #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */ 1075 #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */ 1076 #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ 1077 #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */ 1078 #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */ 1079 #define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */ 1080 #define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) 1081 #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ 1082 #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ 1083 #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ 1084 #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */ 1085 #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */ 1086 #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */ 1087 #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */ 1088 #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ 1089 #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */ 1090 #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */ 1091 1092 /* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ 1093 1094 #define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */ 1095 #define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */ 1096 #define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */ 1097 #define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */ 1098 #define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) 1099 #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ 1100 #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ 1101 #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ 1102 #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ 1103 #define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */ 1104 #define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) 1105 #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ 1106 #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ 1107 #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ 1108 #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ 1109 #define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */ 1110 #define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */ 1111 #define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */ 1112 #define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */ 1113 1114 /* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ 1115 1116 #define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */ 1117 #define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */ 1118 #define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) 1119 #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ 1120 #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ 1121 #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ 1122 #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ 1123 #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ 1124 #define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */ 1125 1126 /* AIC Controller FIFO Status Register (AIC_SR) */ 1127 1128 #define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */ 1129 #define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT) 1130 #define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */ 1131 #define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT) 1132 #define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */ 1133 #define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */ 1134 #define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */ 1135 #define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */ 1136 1137 /* AIC Controller AC-link Status Register (AIC_ACSR) */ 1138 1139 #define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */ 1140 #define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */ 1141 #define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */ 1142 #define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */ 1143 #define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */ 1144 #define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */ 1145 1146 /* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ 1147 1148 #define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */ 1149 1150 /* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ 1151 1152 #define AIC_ACCAR_CAR_BIT 0 1153 #define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) 1154 1155 /* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ 1156 1157 #define AIC_ACCDR_CDR_BIT 0 1158 #define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) 1159 1160 /* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ 1161 1162 #define AIC_ACSAR_SAR_BIT 0 1163 #define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) 1164 1165 /* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ 1166 1167 #define AIC_ACSDR_SDR_BIT 0 1168 #define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) 1169 1170 /* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ 1171 1172 #define AIC_I2SDIV_DIV_BIT 0 1173 #define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) 1174 #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ 1175 #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ 1176 #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ 1177 #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ 1178 #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ 1179 #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ 1180 1181 1182 /************************************************************************* 1183 * ICDC (Internal CODEC) 1184 *************************************************************************/ 1185 #define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */ 1186 #define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */ 1187 #define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */ 1188 #define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */ 1189 #define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */ 1190 #define ICDC_CDCCR1 (ICDC_BASE + 0x0080) 1191 #define ICDC_CDCCR2 (ICDC_BASE + 0x0084) 1192 1193 #define REG_ICDC_CR REG32(ICDC_CR) 1194 #define REG_ICDC_APWAIT REG32(ICDC_APWAIT) 1195 #define REG_ICDC_APPRE REG32(ICDC_APPRE) 1196 #define REG_ICDC_APHPEN REG32(ICDC_APHPEN) 1197 #define REG_ICDC_APSR REG32(ICDC_APSR) 1198 #define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1) 1199 #define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2) 1200 1201 /* ICDC Control Register */ 1202 #define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */ 1203 #define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT) 1204 #define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */ 1205 #define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT) 1206 #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT) 1207 #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT) 1208 #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT) 1209 #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT) 1210 #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT) 1211 #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT) 1212 #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT) 1213 #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT) 1214 #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT) 1215 #define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */ 1216 #define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT) 1217 #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT) 1218 #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT) 1219 #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT) 1220 #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT) 1221 #define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */ 1222 #define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT) 1223 #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT) 1224 #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT) 1225 #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT) 1226 #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT) 1227 #define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */ 1228 #define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */ 1229 #define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */ 1230 #define ICDC_CR_EADC (1 << 10) /* Enable ADC */ 1231 #define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */ 1232 #define ICDC_CR_EDAC (1 << 8) /* Enable DAC */ 1233 #define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */ 1234 #define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */ 1235 #define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */ 1236 #define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */ 1237 #define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */ 1238 #define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */ 1239 1240 /* Anti-Pop WAIT Stage Timing Control Register */ 1241 #define ICDC_APWAIT_WAITSN_BIT 0 1242 #define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT) 1243 1244 /* Anti-Pop HPEN-PRE Stage Timing Control Register */ 1245 #define ICDC_APPRE_PRESN_BIT 0 1246 #define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT) 1247 1248 /* Anti-Pop HPEN Stage Timing Control Register */ 1249 #define ICDC_APHPEN_HPENSN_BIT 0 1250 #define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT) 1251 1252 /* Anti-Pop Status Register */ 1253 #define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */ 1254 #define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT) 1255 #define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */ 1256 #define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */ 1257 #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */ 1258 #define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */ 1259 #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */ 1260 #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */ 1261 #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */ 1262 #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */ 1263 #define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */ 1264 #define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT) 1265 1266 1267 /************************************************************************* 1268 * I2C 1269 *************************************************************************/ 1270 #define I2C_DR (I2C_BASE + 0x000) 1271 #define I2C_CR (I2C_BASE + 0x004) 1272 #define I2C_SR (I2C_BASE + 0x008) 1273 #define I2C_GR (I2C_BASE + 0x00C) 1274 1275 #define REG_I2C_DR REG8(I2C_DR) 1276 #define REG_I2C_CR REG8(I2C_CR) 1277 #define REG_I2C_SR REG8(I2C_SR) 1278 #define REG_I2C_GR REG16(I2C_GR) 1279 1280 /* I2C Control Register (I2C_CR) */ 1281 1282 #define I2C_CR_IEN (1 << 4) 1283 #define I2C_CR_STA (1 << 3) 1284 #define I2C_CR_STO (1 << 2) 1285 #define I2C_CR_AC (1 << 1) 1286 #define I2C_CR_I2CE (1 << 0) 1287 1288 /* I2C Status Register (I2C_SR) */ 1289 1290 #define I2C_SR_STX (1 << 4) 1291 #define I2C_SR_BUSY (1 << 3) 1292 #define I2C_SR_TEND (1 << 2) 1293 #define I2C_SR_DRF (1 << 1) 1294 #define I2C_SR_ACKF (1 << 0) 1295 1296 1297 /************************************************************************* 1298 * SSI 1299 *************************************************************************/ 1300 #define SSI_DR (SSI_BASE + 0x000) 1301 #define SSI_CR0 (SSI_BASE + 0x004) 1302 #define SSI_CR1 (SSI_BASE + 0x008) 1303 #define SSI_SR (SSI_BASE + 0x00C) 1304 #define SSI_ITR (SSI_BASE + 0x010) 1305 #define SSI_ICR (SSI_BASE + 0x014) 1306 #define SSI_GR (SSI_BASE + 0x018) 1307 1308 #define REG_SSI_DR REG32(SSI_DR) 1309 #define REG_SSI_CR0 REG16(SSI_CR0) 1310 #define REG_SSI_CR1 REG32(SSI_CR1) 1311 #define REG_SSI_SR REG32(SSI_SR) 1312 #define REG_SSI_ITR REG16(SSI_ITR) 1313 #define REG_SSI_ICR REG8(SSI_ICR) 1314 #define REG_SSI_GR REG16(SSI_GR) 1315 1316 /* SSI Data Register (SSI_DR) */ 1317 1318 #define SSI_DR_GPC_BIT 0 1319 #define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) 1320 1321 /* SSI Control Register 0 (SSI_CR0) */ 1322 1323 #define SSI_CR0_SSIE (1 << 15) 1324 #define SSI_CR0_TIE (1 << 14) 1325 #define SSI_CR0_RIE (1 << 13) 1326 #define SSI_CR0_TEIE (1 << 12) 1327 #define SSI_CR0_REIE (1 << 11) 1328 #define SSI_CR0_LOOP (1 << 10) 1329 #define SSI_CR0_RFINE (1 << 9) 1330 #define SSI_CR0_RFINC (1 << 8) 1331 #define SSI_CR0_FSEL (1 << 6) 1332 #define SSI_CR0_TFLUSH (1 << 2) 1333 #define SSI_CR0_RFLUSH (1 << 1) 1334 #define SSI_CR0_DISREV (1 << 0) 1335 1336 /* SSI Control Register 1 (SSI_CR1) */ 1337 1338 #define SSI_CR1_FRMHL_BIT 30 1339 #define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) 1340 #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ 1341 #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ 1342 #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ 1343 #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ 1344 #define SSI_CR1_TFVCK_BIT 28 1345 #define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) 1346 #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) 1347 #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) 1348 #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) 1349 #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) 1350 #define SSI_CR1_TCKFI_BIT 26 1351 #define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) 1352 #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) 1353 #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) 1354 #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) 1355 #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) 1356 #define SSI_CR1_LFST (1 << 25) 1357 #define SSI_CR1_ITFRM (1 << 24) 1358 #define SSI_CR1_UNFIN (1 << 23) 1359 #define SSI_CR1_MULTS (1 << 22) 1360 #define SSI_CR1_FMAT_BIT 20 1361 #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) 1362 #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola????s SPI format */ 1363 #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ 1364 #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ 1365 #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ 1366 #define SSI_CR1_TTRG_BIT 16 1367 #define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT) 1368 #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT) 1369 #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT) 1370 #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT) 1371 #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT) 1372 #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT) 1373 #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT) 1374 #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT) 1375 #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT) 1376 #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT) 1377 #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT) 1378 #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT) 1379 #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT) 1380 #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT) 1381 #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT) 1382 #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT) 1383 #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT) 1384 #define SSI_CR1_MCOM_BIT 12 1385 #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) 1386 #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ 1387 #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ 1388 #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ 1389 #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ 1390 #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ 1391 #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ 1392 #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ 1393 #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ 1394 #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ 1395 #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ 1396 #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ 1397 #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ 1398 #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ 1399 #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ 1400 #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ 1401 #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ 1402 #define SSI_CR1_RTRG_BIT 8 1403 #define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT) 1404 #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) 1405 #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT) 1406 #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT) 1407 #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT) 1408 #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT) 1409 #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT) 1410 #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT) 1411 #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT) 1412 #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT) 1413 #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT) 1414 #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT) 1415 #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT) 1416 #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT) 1417 #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT) 1418 #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT) 1419 #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT) 1420 #define SSI_CR1_FLEN_BIT 4 1421 #define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) 1422 #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) 1423 #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) 1424 #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) 1425 #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) 1426 #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) 1427 #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) 1428 #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) 1429 #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) 1430 #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) 1431 #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) 1432 #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) 1433 #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) 1434 #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) 1435 #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) 1436 #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) 1437 #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) 1438 #define SSI_CR1_PHA (1 << 1) 1439 #define SSI_CR1_POL (1 << 0) 1440 1441 /* SSI Status Register (SSI_SR) */ 1442 1443 #define SSI_SR_TFIFONUM_BIT 16 1444 #define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT) 1445 #define SSI_SR_RFIFONUM_BIT 8 1446 #define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT) 1447 #define SSI_SR_END (1 << 7) 1448 #define SSI_SR_BUSY (1 << 6) 1449 #define SSI_SR_TFF (1 << 5) 1450 #define SSI_SR_RFE (1 << 4) 1451 #define SSI_SR_TFHE (1 << 3) 1452 #define SSI_SR_RFHF (1 << 2) 1453 #define SSI_SR_UNDR (1 << 1) 1454 #define SSI_SR_OVER (1 << 0) 1455 1456 /* SSI Interval Time Control Register (SSI_ITR) */ 1457 1458 #define SSI_ITR_CNTCLK (1 << 15) 1459 #define SSI_ITR_IVLTM_BIT 0 1460 #define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) 1461 1462 1463 /************************************************************************* 1464 * MSC 1465 *************************************************************************/ 1466 #define MSC_STRPCL (MSC_BASE + 0x000) 1467 #define MSC_STAT (MSC_BASE + 0x004) 1468 #define MSC_CLKRT (MSC_BASE + 0x008) 1469 #define MSC_CMDAT (MSC_BASE + 0x00C) 1470 #define MSC_RESTO (MSC_BASE + 0x010) 1471 #define MSC_RDTO (MSC_BASE + 0x014) 1472 #define MSC_BLKLEN (MSC_BASE + 0x018) 1473 #define MSC_NOB (MSC_BASE + 0x01C) 1474 #define MSC_SNOB (MSC_BASE + 0x020) 1475 #define MSC_IMASK (MSC_BASE + 0x024) 1476 #define MSC_IREG (MSC_BASE + 0x028) 1477 #define MSC_CMD (MSC_BASE + 0x02C) 1478 #define MSC_ARG (MSC_BASE + 0x030) 1479 #define MSC_RES (MSC_BASE + 0x034) 1480 #define MSC_RXFIFO (MSC_BASE + 0x038) 1481 #define MSC_TXFIFO (MSC_BASE + 0x03C) 1482 1483 #define REG_MSC_STRPCL REG16(MSC_STRPCL) 1484 #define REG_MSC_STAT REG32(MSC_STAT) 1485 #define REG_MSC_CLKRT REG16(MSC_CLKRT) 1486 #define REG_MSC_CMDAT REG32(MSC_CMDAT) 1487 #define REG_MSC_RESTO REG16(MSC_RESTO) 1488 #define REG_MSC_RDTO REG16(MSC_RDTO) 1489 #define REG_MSC_BLKLEN REG16(MSC_BLKLEN) 1490 #define REG_MSC_NOB REG16(MSC_NOB) 1491 #define REG_MSC_SNOB REG16(MSC_SNOB) 1492 #define REG_MSC_IMASK REG16(MSC_IMASK) 1493 #define REG_MSC_IREG REG16(MSC_IREG) 1494 #define REG_MSC_CMD REG8(MSC_CMD) 1495 #define REG_MSC_ARG REG32(MSC_ARG) 1496 #define REG_MSC_RES REG16(MSC_RES) 1497 #define REG_MSC_RXFIFO REG32(MSC_RXFIFO) 1498 #define REG_MSC_TXFIFO REG32(MSC_TXFIFO) 1499 1500 /* MSC Clock and Control Register (MSC_STRPCL) */ 1501 1502 #define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) 1503 #define MSC_STRPCL_EXIT_TRANSFER (1 << 6) 1504 #define MSC_STRPCL_START_READWAIT (1 << 5) 1505 #define MSC_STRPCL_STOP_READWAIT (1 << 4) 1506 #define MSC_STRPCL_RESET (1 << 3) 1507 #define MSC_STRPCL_START_OP (1 << 2) 1508 #define MSC_STRPCL_CLOCK_CONTROL_BIT 0 1509 #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) 1510 #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ 1511 #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ 1512 1513 /* MSC Status Register (MSC_STAT) */ 1514 1515 #define MSC_STAT_IS_RESETTING (1 << 15) 1516 #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) 1517 #define MSC_STAT_PRG_DONE (1 << 13) 1518 #define MSC_STAT_DATA_TRAN_DONE (1 << 12) 1519 #define MSC_STAT_END_CMD_RES (1 << 11) 1520 #define MSC_STAT_DATA_FIFO_AFULL (1 << 10) 1521 #define MSC_STAT_IS_READWAIT (1 << 9) 1522 #define MSC_STAT_CLK_EN (1 << 8) 1523 #define MSC_STAT_DATA_FIFO_FULL (1 << 7) 1524 #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) 1525 #define MSC_STAT_CRC_RES_ERR (1 << 5) 1526 #define MSC_STAT_CRC_READ_ERROR (1 << 4) 1527 #define MSC_STAT_CRC_WRITE_ERROR_BIT 2 1528 #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) 1529 #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ 1530 #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ 1531 #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ 1532 #define MSC_STAT_TIME_OUT_RES (1 << 1) 1533 #define MSC_STAT_TIME_OUT_READ (1 << 0) 1534 1535 /* MSC Bus Clock Control Register (MSC_CLKRT) */ 1536 1537 #define MSC_CLKRT_CLK_RATE_BIT 0 1538 #define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) 1539 #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ 1540 #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ 1541 #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ 1542 #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ 1543 #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ 1544 #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ 1545 #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ 1546 #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ 1547 1548 /* MSC Command Sequence Control Register (MSC_CMDAT) */ 1549 1550 #define MSC_CMDAT_IO_ABORT (1 << 11) 1551 #define MSC_CMDAT_BUS_WIDTH_BIT 9 1552 #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) 1553 #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) 1554 #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) 1555 #define MSC_CMDAT_DMA_EN (1 << 8) 1556 #define MSC_CMDAT_INIT (1 << 7) 1557 #define MSC_CMDAT_BUSY (1 << 6) 1558 #define MSC_CMDAT_STREAM_BLOCK (1 << 5) 1559 #define MSC_CMDAT_WRITE (1 << 4) 1560 #define MSC_CMDAT_READ (0 << 4) 1561 #define MSC_CMDAT_DATA_EN (1 << 3) 1562 #define MSC_CMDAT_RESPONSE_BIT 0 1563 #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) 1564 #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) 1565 #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) 1566 #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) 1567 #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) 1568 #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) 1569 #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) 1570 #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) 1571 1572 /* MSC Interrupts Mask Register (MSC_IMASK) */ 1573 #define MSC_IMASK_SDIO (1 << 7) 1574 #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) 1575 #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) 1576 #define MSC_IMASK_END_CMD_RES (1 << 2) 1577 #define MSC_IMASK_PRG_DONE (1 << 1) 1578 #define MSC_IMASK_DATA_TRAN_DONE (1 << 0) 1579 1580 1581 /* MSC Interrupts Status Register (MSC_IREG) */ 1582 #define MSC_IREG_SDIO (1 << 7) 1583 #define MSC_IREG_TXFIFO_WR_REQ (1 << 6) 1584 #define MSC_IREG_RXFIFO_RD_REQ (1 << 5) 1585 #define MSC_IREG_END_CMD_RES (1 << 2) 1586 #define MSC_IREG_PRG_DONE (1 << 1) 1587 #define MSC_IREG_DATA_TRAN_DONE (1 << 0) 1588 1589 1590 /* 1591 * EMC (External Memory Controller) 1592 */ 1593 #define EMC_BCR (EMC_BASE + 0x0) /* BCR */ 1594 1595 #define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */ 1596 #define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */ 1597 #define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */ 1598 #define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */ 1599 #define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */ 1600 #define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */ 1601 #define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */ 1602 #define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */ 1603 #define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */ 1604 #define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */ 1605 1606 #define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */ 1607 #define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */ 1608 #define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */ 1609 #define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */ 1610 #define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */ 1611 #define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */ 1612 #define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */ 1613 #define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */ 1614 #define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */ 1615 #define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */ 1616 #define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */ 1617 #define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */ 1618 1619 #define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */ 1620 #define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */ 1621 #define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */ 1622 #define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */ 1623 #define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */ 1624 #define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */ 1625 1626 #define REG_EMC_BCR REG32(EMC_BCR) 1627 1628 #define REG_EMC_SMCR0 REG32(EMC_SMCR0) 1629 #define REG_EMC_SMCR1 REG32(EMC_SMCR1) 1630 #define REG_EMC_SMCR2 REG32(EMC_SMCR2) 1631 #define REG_EMC_SMCR3 REG32(EMC_SMCR3) 1632 #define REG_EMC_SMCR4 REG32(EMC_SMCR4) 1633 #define REG_EMC_SACR0 REG32(EMC_SACR0) 1634 #define REG_EMC_SACR1 REG32(EMC_SACR1) 1635 #define REG_EMC_SACR2 REG32(EMC_SACR2) 1636 #define REG_EMC_SACR3 REG32(EMC_SACR3) 1637 #define REG_EMC_SACR4 REG32(EMC_SACR4) 1638 1639 #define REG_EMC_NFCSR REG32(EMC_NFCSR) 1640 #define REG_EMC_NFECR REG32(EMC_NFECR) 1641 #define REG_EMC_NFECC REG32(EMC_NFECC) 1642 #define REG_EMC_NFPAR0 REG32(EMC_NFPAR0) 1643 #define REG_EMC_NFPAR1 REG32(EMC_NFPAR1) 1644 #define REG_EMC_NFPAR2 REG32(EMC_NFPAR2) 1645 #define REG_EMC_NFINTS REG32(EMC_NFINTS) 1646 #define REG_EMC_NFINTE REG32(EMC_NFINTE) 1647 #define REG_EMC_NFERR0 REG32(EMC_NFERR0) 1648 #define REG_EMC_NFERR1 REG32(EMC_NFERR1) 1649 #define REG_EMC_NFERR2 REG32(EMC_NFERR2) 1650 #define REG_EMC_NFERR3 REG32(EMC_NFERR3) 1651 1652 #define REG_EMC_DMCR REG32(EMC_DMCR) 1653 #define REG_EMC_RTCSR REG16(EMC_RTCSR) 1654 #define REG_EMC_RTCNT REG16(EMC_RTCNT) 1655 #define REG_EMC_RTCOR REG16(EMC_RTCOR) 1656 #define REG_EMC_DMAR0 REG32(EMC_DMAR0) 1657 1658 /* Static Memory Control Register */ 1659 #define EMC_SMCR_STRV_BIT 24 1660 #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) 1661 #define EMC_SMCR_TAW_BIT 20 1662 #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) 1663 #define EMC_SMCR_TBP_BIT 16 1664 #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) 1665 #define EMC_SMCR_TAH_BIT 12 1666 #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) 1667 #define EMC_SMCR_TAS_BIT 8 1668 #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) 1669 #define EMC_SMCR_BW_BIT 6 1670 #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) 1671 #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) 1672 #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) 1673 #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) 1674 #define EMC_SMCR_BCM (1 << 3) 1675 #define EMC_SMCR_BL_BIT 1 1676 #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) 1677 #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) 1678 #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) 1679 #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) 1680 #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) 1681 #define EMC_SMCR_SMT (1 << 0) 1682 1683 /* Static Memory Bank Addr Config Reg */ 1684 #define EMC_SACR_BASE_BIT 8 1685 #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) 1686 #define EMC_SACR_MASK_BIT 0 1687 #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) 1688 1689 /* NAND Flash Control/Status Register */ 1690 #define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ 1691 #define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ 1692 #define EMC_NFCSR_NFCE3 (1 << 5) 1693 #define EMC_NFCSR_NFE3 (1 << 4) 1694 #define EMC_NFCSR_NFCE2 (1 << 3) 1695 #define EMC_NFCSR_NFE2 (1 << 2) 1696 #define EMC_NFCSR_NFCE1 (1 << 1) 1697 #define EMC_NFCSR_NFE1 (1 << 0) 1698 1699 /* NAND Flash ECC Control Register */ 1700 #define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */ 1701 #define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */ 1702 #define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */ 1703 #define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */ 1704 #define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */ 1705 #define EMC_NFECR_ERST (1 << 1) /* ECC Reset */ 1706 #define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */ 1707 1708 /* NAND Flash ECC Data Register */ 1709 #define EMC_NFECC_ECC2_BIT 16 1710 #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) 1711 #define EMC_NFECC_ECC1_BIT 8 1712 #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) 1713 #define EMC_NFECC_ECC0_BIT 0 1714 #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) 1715 1716 /* NAND Flash Interrupt Status Register */ 1717 #define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */ 1718 #define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) 1719 #define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */ 1720 #define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */ 1721 #define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */ 1722 #define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */ 1723 #define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */ 1724 1725 /* NAND Flash Interrupt Enable Register */ 1726 #define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */ 1727 #define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */ 1728 #define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */ 1729 #define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */ 1730 #define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */ 1731 1732 /* NAND Flash RS Error Report Register */ 1733 #define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */ 1734 #define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT) 1735 #define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */ 1736 #define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT) 1737 1738 1739 /* DRAM Control Register */ 1740 #define EMC_DMCR_BW_BIT 31 1741 #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) 1742 #define EMC_DMCR_CA_BIT 26 1743 #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) 1744 #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) 1745 #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) 1746 #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) 1747 #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) 1748 #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) 1749 #define EMC_DMCR_RMODE (1 << 25) 1750 #define EMC_DMCR_RFSH (1 << 24) 1751 #define EMC_DMCR_MRSET (1 << 23) 1752 #define EMC_DMCR_RA_BIT 20 1753 #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) 1754 #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) 1755 #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) 1756 #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) 1757 #define EMC_DMCR_BA_BIT 19 1758 #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) 1759 #define EMC_DMCR_PDM (1 << 18) 1760 #define EMC_DMCR_EPIN (1 << 17) 1761 #define EMC_DMCR_TRAS_BIT 13 1762 #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) 1763 #define EMC_DMCR_RCD_BIT 11 1764 #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) 1765 #define EMC_DMCR_TPC_BIT 8 1766 #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) 1767 #define EMC_DMCR_TRWL_BIT 5 1768 #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) 1769 #define EMC_DMCR_TRC_BIT 2 1770 #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) 1771 #define EMC_DMCR_TCL_BIT 0 1772 #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) 1773 1774 /* Refresh Time Control/Status Register */ 1775 #define EMC_RTCSR_CMF (1 << 7) 1776 #define EMC_RTCSR_CKS_BIT 0 1777 #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) 1778 #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) 1779 #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) 1780 #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) 1781 #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) 1782 #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) 1783 #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) 1784 #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) 1785 #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) 1786 1787 /* SDRAM Bank Address Configuration Register */ 1788 #define EMC_DMAR_BASE_BIT 8 1789 #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) 1790 #define EMC_DMAR_MASK_BIT 0 1791 #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) 1792 1793 /* Mode Register of SDRAM bank 0 */ 1794 #define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ 1795 #define EMC_SDMR_OM_BIT 7 /* Operating Mode */ 1796 #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) 1797 #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) 1798 #define EMC_SDMR_CAS_BIT 4 /* CAS Latency */ 1799 #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) 1800 #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) 1801 #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) 1802 #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) 1803 #define EMC_SDMR_BT_BIT 3 /* Burst Type */ 1804 #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) 1805 #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */ 1806 #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */ 1807 #define EMC_SDMR_BL_BIT 0 /* Burst Length */ 1808 #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) 1809 #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) 1810 #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) 1811 #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) 1812 #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) 1813 1814 #define EMC_SDMR_CAS2_16BIT \ 1815 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) 1816 #define EMC_SDMR_CAS2_32BIT \ 1817 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) 1818 #define EMC_SDMR_CAS3_16BIT \ 1819 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) 1820 #define EMC_SDMR_CAS3_32BIT \ 1821 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) 1822 1823 /************************************************************************* 1824 * CIM 1825 *************************************************************************/ 1826 #define CIM_CFG (CIM_BASE + 0x0000) 1827 #define CIM_CTRL (CIM_BASE + 0x0004) 1828 #define CIM_STATE (CIM_BASE + 0x0008) 1829 #define CIM_IID (CIM_BASE + 0x000C) 1830 #define CIM_RXFIFO (CIM_BASE + 0x0010) 1831 #define CIM_DA (CIM_BASE + 0x0020) 1832 #define CIM_FA (CIM_BASE + 0x0024) 1833 #define CIM_FID (CIM_BASE + 0x0028) 1834 #define CIM_CMD (CIM_BASE + 0x002C) 1835 1836 #define REG_CIM_CFG REG32(CIM_CFG) 1837 #define REG_CIM_CTRL REG32(CIM_CTRL) 1838 #define REG_CIM_STATE REG32(CIM_STATE) 1839 #define REG_CIM_IID REG32(CIM_IID) 1840 #define REG_CIM_RXFIFO REG32(CIM_RXFIFO) 1841 #define REG_CIM_DA REG32(CIM_DA) 1842 #define REG_CIM_FA REG32(CIM_FA) 1843 #define REG_CIM_FID REG32(CIM_FID) 1844 #define REG_CIM_CMD REG32(CIM_CMD) 1845 1846 /* CIM Configuration Register (CIM_CFG) */ 1847 1848 #define CIM_CFG_INV_DAT (1 << 15) 1849 #define CIM_CFG_VSP (1 << 14) 1850 #define CIM_CFG_HSP (1 << 13) 1851 #define CIM_CFG_PCP (1 << 12) 1852 #define CIM_CFG_DUMMY_ZERO (1 << 9) 1853 #define CIM_CFG_EXT_VSYNC (1 << 8) 1854 #define CIM_CFG_PACK_BIT 4 1855 #define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) 1856 #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) 1857 #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) 1858 #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) 1859 #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) 1860 #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) 1861 #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) 1862 #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) 1863 #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) 1864 #define CIM_CFG_DSM_BIT 0 1865 #define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) 1866 #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ 1867 #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ 1868 #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ 1869 #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ 1870 1871 /* CIM Control Register (CIM_CTRL) */ 1872 1873 #define CIM_CTRL_MCLKDIV_BIT 24 1874 #define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) 1875 #define CIM_CTRL_FRC_BIT 16 1876 #define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) 1877 #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ 1878 #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ 1879 #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ 1880 #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ 1881 #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ 1882 #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ 1883 #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ 1884 #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ 1885 #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ 1886 #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ 1887 #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ 1888 #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ 1889 #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ 1890 #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ 1891 #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ 1892 #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ 1893 #define CIM_CTRL_VDDM (1 << 13) 1894 #define CIM_CTRL_DMA_SOFM (1 << 12) 1895 #define CIM_CTRL_DMA_EOFM (1 << 11) 1896 #define CIM_CTRL_DMA_STOPM (1 << 10) 1897 #define CIM_CTRL_RXF_TRIGM (1 << 9) 1898 #define CIM_CTRL_RXF_OFM (1 << 8) 1899 #define CIM_CTRL_RXF_TRIG_BIT 4 1900 #define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) 1901 #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ 1902 #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ 1903 #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ 1904 #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ 1905 #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ 1906 #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ 1907 #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ 1908 #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ 1909 #define CIM_CTRL_DMA_EN (1 << 2) 1910 #define CIM_CTRL_RXF_RST (1 << 1) 1911 #define CIM_CTRL_ENA (1 << 0) 1912 1913 /* CIM State Register (CIM_STATE) */ 1914 1915 #define CIM_STATE_DMA_SOF (1 << 6) 1916 #define CIM_STATE_DMA_EOF (1 << 5) 1917 #define CIM_STATE_DMA_STOP (1 << 4) 1918 #define CIM_STATE_RXF_OF (1 << 3) 1919 #define CIM_STATE_RXF_TRIG (1 << 2) 1920 #define CIM_STATE_RXF_EMPTY (1 << 1) 1921 #define CIM_STATE_VDD (1 << 0) 1922 1923 /* CIM DMA Command Register (CIM_CMD) */ 1924 1925 #define CIM_CMD_SOFINT (1 << 31) 1926 #define CIM_CMD_EOFINT (1 << 30) 1927 #define CIM_CMD_STOP (1 << 28) 1928 #define CIM_CMD_LEN_BIT 0 1929 #define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) 1930 1931 1932 /************************************************************************* 1933 * SADC (Smart A/D Controller) 1934 *************************************************************************/ 1935 1936 #define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */ 1937 #define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */ 1938 #define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */ 1939 #define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/ 1940 #define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */ 1941 #define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */ 1942 #define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */ 1943 #define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */ 1944 #define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */ 1945 1946 #define REG_SADC_ENA REG8(SADC_ENA) 1947 #define REG_SADC_CFG REG32(SADC_CFG) 1948 #define REG_SADC_CTRL REG8(SADC_CTRL) 1949 #define REG_SADC_STATE REG8(SADC_STATE) 1950 #define REG_SADC_SAMETIME REG16(SADC_SAMETIME) 1951 #define REG_SADC_WAITTIME REG16(SADC_WAITTIME) 1952 #define REG_SADC_TSDAT REG32(SADC_TSDAT) 1953 #define REG_SADC_BATDAT REG16(SADC_BATDAT) 1954 #define REG_SADC_SADDAT REG16(SADC_SADDAT) 1955 1956 /* ADC Enable Register */ 1957 #define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */ 1958 #define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */ 1959 #define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */ 1960 #define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */ 1961 1962 /* ADC Configure Register */ 1963 #define SADC_CFG_CLKOUT_NUM_BIT 16 1964 #define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT) 1965 #define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */ 1966 #define SADC_CFG_XYZ_BIT 13 /* XYZ selection */ 1967 #define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT) 1968 #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT) 1969 #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT) 1970 #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT) 1971 #define SADC_CFG_SNUM_BIT 10 /* Sample Number */ 1972 #define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT) 1973 #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT) 1974 #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT) 1975 #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT) 1976 #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT) 1977 #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT) 1978 #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT) 1979 #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT) 1980 #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT) 1981 #define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */ 1982 #define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT) 1983 #define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */ 1984 #define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */ 1985 #define SADC_CFG_CMD_BIT 0 /* ADC Command */ 1986 #define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT) 1987 #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */ 1988 #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */ 1989 #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */ 1990 #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */ 1991 #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */ 1992 #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */ 1993 #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */ 1994 #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */ 1995 #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */ 1996 #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */ 1997 #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */ 1998 #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */ 1999 #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */ 2000 2001 /* ADC Control Register */ 2002 #define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */ 2003 #define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */ 2004 #define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */ 2005 #define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */ 2006 #define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */ 2007 2008 /* ADC Status Register */ 2009 #define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */ 2010 #define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */ 2011 #define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */ 2012 #define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */ 2013 #define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */ 2014 #define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */ 2015 #define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */ 2016 #define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */ 2017 2018 /* ADC Touch Screen Data Register */ 2019 #define SADC_TSDAT_DATA0_BIT 0 2020 #define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT) 2021 #define SADC_TSDAT_TYPE0 (1 << 15) 2022 #define SADC_TSDAT_DATA1_BIT 16 2023 #define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT) 2024 #define SADC_TSDAT_TYPE1 (1 << 31) 2025 2026 2027 /************************************************************************* 2028 * SLCD (Smart LCD Controller) 2029 *************************************************************************/ 2030 2031 #define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */ 2032 #define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */ 2033 #define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */ 2034 #define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */ 2035 #define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */ 2036 2037 #define REG_SLCD_CFG REG32(SLCD_CFG) 2038 #define REG_SLCD_CTRL REG8(SLCD_CTRL) 2039 #define REG_SLCD_STATE REG8(SLCD_STATE) 2040 #define REG_SLCD_DATA REG32(SLCD_DATA) 2041 #define REG_SLCD_FIFO REG32(SLCD_FIFO) 2042 2043 /* SLCD Configure Register */ 2044 #define SLCD_CFG_BURST_BIT 14 2045 #define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT) 2046 #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT) 2047 #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT) 2048 #define SLCD_CFG_DWIDTH_BIT 10 2049 #define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT) 2050 #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT) 2051 #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT) 2052 #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT) 2053 #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT) 2054 #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT) 2055 #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT) 2056 #define SLCD_CFG_CWIDTH_16BIT (0 << 8) 2057 #define SLCD_CFG_CWIDTH_8BIT (1 << 8) 2058 #define SLCD_CFG_CWIDTH_18BIT (2 << 8) 2059 #define SLCD_CFG_CS_ACTIVE_LOW (0 << 4) 2060 #define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4) 2061 #define SLCD_CFG_RS_CMD_LOW (0 << 3) 2062 #define SLCD_CFG_RS_CMD_HIGH (1 << 3) 2063 #define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1) 2064 #define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1) 2065 #define SLCD_CFG_TYPE_PARALLEL (0 << 0) 2066 #define SLCD_CFG_TYPE_SERIAL (1 << 0) 2067 2068 /* SLCD Control Register */ 2069 #define SLCD_CTRL_DMA_EN (1 << 0) 2070 2071 /* SLCD Status Register */ 2072 #define SLCD_STATE_BUSY (1 << 0) 2073 2074 /* SLCD Data Register */ 2075 #define SLCD_DATA_RS_DATA (0 << 31) 2076 #define SLCD_DATA_RS_COMMAND (1 << 31) 2077 2078 /* SLCD FIFO Register */ 2079 #define SLCD_FIFO_RS_DATA (0 << 31) 2080 #define SLCD_FIFO_RS_COMMAND (1 << 31) 2081 2082 2083 /************************************************************************* 2084 * LCD (LCD Controller) 2085 *************************************************************************/ 2086 2087 /* Register definitions with absolute positioning have been removed. */ 2088 2089 /* LCD Configure Register */ 2090 #define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */ 2091 #define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT) 2092 #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT) 2093 #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT) 2094 #define LCD_CFG_PSM (1 << 23) /* PS signal mode */ 2095 #define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */ 2096 #define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */ 2097 #define LCD_CFG_REVM (1 << 20) /* REV signal mode */ 2098 #define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */ 2099 #define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */ 2100 #define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */ 2101 #define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */ 2102 #define LCD_CFG_PSP (1 << 15) /* PS pin reset state */ 2103 #define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */ 2104 #define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */ 2105 #define LCD_CFG_REVP (1 << 12) /* REV pin reset state */ 2106 #define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */ 2107 #define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */ 2108 #define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */ 2109 #define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */ 2110 #define LCD_CFG_PDW_BIT 4 /* STN pins utilization */ 2111 #define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT) 2112 #define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */ 2113 #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */ 2114 #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */ 2115 #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */ 2116 #define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */ 2117 #define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT) 2118 #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */ 2119 #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT) 2120 #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT) 2121 #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT) 2122 #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT) 2123 #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT) 2124 #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT) 2125 #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT) 2126 #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT) 2127 #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT) 2128 #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT) 2129 #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT) 2130 /* JZ47XX defines */ 2131 #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT) 2132 #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT) 2133 #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT) 2134 2135 2136 2137 /* Vertical Synchronize Register */ 2138 #define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */ 2139 #define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) 2140 #define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */ 2141 #define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) 2142 2143 /* Horizontal Synchronize Register */ 2144 #define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */ 2145 #define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) 2146 #define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */ 2147 #define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) 2148 2149 /* Virtual Area Setting Register */ 2150 #define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */ 2151 #define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) 2152 #define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */ 2153 #define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) 2154 2155 /* Display Area Horizontal Start/End Point Register */ 2156 #define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */ 2157 #define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) 2158 #define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */ 2159 #define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) 2160 2161 /* Display Area Vertical Start/End Point Register */ 2162 #define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */ 2163 #define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) 2164 #define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */ 2165 #define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) 2166 2167 /* PS Signal Setting */ 2168 #define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */ 2169 #define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT) 2170 #define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */ 2171 #define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT) 2172 2173 /* CLS Signal Setting */ 2174 #define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */ 2175 #define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT) 2176 #define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */ 2177 #define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT) 2178 2179 /* SPL Signal Setting */ 2180 #define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */ 2181 #define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT) 2182 #define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */ 2183 #define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT) 2184 2185 /* REV Signal Setting */ 2186 #define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */ 2187 #define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT) 2188 2189 /* LCD Control Register */ 2190 #define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */ 2191 #define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) 2192 #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */ 2193 #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */ 2194 #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */ 2195 #define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */ 2196 #define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */ 2197 #define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */ 2198 #define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */ 2199 #define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) 2200 #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */ 2201 #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */ 2202 #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */ 2203 #define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */ 2204 #define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) 2205 #define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */ 2206 #define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */ 2207 #define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */ 2208 #define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */ 2209 #define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */ 2210 #define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */ 2211 #define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */ 2212 #define LCD_CTRL_BEDN (1 << 6) /* Endian selection */ 2213 #define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */ 2214 #define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */ 2215 #define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */ 2216 #define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */ 2217 #define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) 2218 #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */ 2219 #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */ 2220 #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */ 2221 #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */ 2222 #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */ 2223 #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */ 2224 2225 /* LCD Status Register */ 2226 #define LCD_STATE_QD (1 << 7) /* Quick Disable Done */ 2227 #define LCD_STATE_EOF (1 << 5) /* EOF Flag */ 2228 #define LCD_STATE_SOF (1 << 4) /* SOF Flag */ 2229 #define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */ 2230 #define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */ 2231 #define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */ 2232 #define LCD_STATE_LDD (1 << 0) /* LCD Disabled */ 2233 2234 /* DMA Command Register */ 2235 #define LCD_CMD_SOFINT (1 << 31) 2236 #define LCD_CMD_EOFINT (1 << 30) 2237 #define LCD_CMD_PAL (1 << 28) 2238 #define LCD_CMD_LEN_BIT 0 2239 #define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) 2240 2241 2242 /************************************************************************* 2243 * USB Device 2244 *************************************************************************/ 2245 #define USB_BASE UDC_BASE 2246 2247 #define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */ 2248 #define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */ 2249 #define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */ 2250 #define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */ 2251 #define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */ 2252 #define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */ 2253 #define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */ 2254 #define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */ 2255 #define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */ 2256 #define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */ 2257 #define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */ 2258 2259 #define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */ 2260 #define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */ 2261 #define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */ 2262 #define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */ 2263 #define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */ 2264 #define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */ 2265 #define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */ 2266 #define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */ 2267 2268 #define USB_FIFO_EP0 (USB_BASE + 0x20) 2269 #define USB_FIFO_EP1 (USB_BASE + 0x24) 2270 #define USB_FIFO_EP2 (USB_BASE + 0x28) 2271 2272 #define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */ 2273 #define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */ 2274 2275 #define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */ 2276 #define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */ 2277 #define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */ 2278 #define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */ 2279 #define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */ 2280 #define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */ 2281 #define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */ 2282 2283 2284 /* Power register bit masks */ 2285 #define USB_POWER_SUSPENDM 0x01 2286 #define USB_POWER_RESUME 0x04 2287 #define USB_POWER_HSMODE 0x10 2288 #define USB_POWER_HSENAB 0x20 2289 #define USB_POWER_SOFTCONN 0x40 2290 2291 /* Interrupt register bit masks */ 2292 #define USB_INTR_SUSPEND 0x01 2293 #define USB_INTR_RESUME 0x02 2294 #define USB_INTR_RESET 0x04 2295 2296 #define USB_INTR_EP0 0x0001 2297 #define USB_INTR_INEP1 0x0002 2298 #define USB_INTR_INEP2 0x0004 2299 #define USB_INTR_OUTEP1 0x0002 2300 2301 /* CSR0 bit masks */ 2302 #define USB_CSR0_OUTPKTRDY 0x01 2303 #define USB_CSR0_INPKTRDY 0x02 2304 #define USB_CSR0_SENTSTALL 0x04 2305 #define USB_CSR0_DATAEND 0x08 2306 #define USB_CSR0_SETUPEND 0x10 2307 #define USB_CSR0_SENDSTALL 0x20 2308 #define USB_CSR0_SVDOUTPKTRDY 0x40 2309 #define USB_CSR0_SVDSETUPEND 0x80 2310 2311 /* Endpoint CSR register bits */ 2312 #define USB_INCSRH_AUTOSET 0x80 2313 #define USB_INCSRH_ISO 0x40 2314 #define USB_INCSRH_MODE 0x20 2315 #define USB_INCSRH_DMAREQENAB 0x10 2316 #define USB_INCSRH_DMAREQMODE 0x04 2317 #define USB_INCSR_CDT 0x40 2318 #define USB_INCSR_SENTSTALL 0x20 2319 #define USB_INCSR_SENDSTALL 0x10 2320 #define USB_INCSR_FF 0x08 2321 #define USB_INCSR_UNDERRUN 0x04 2322 #define USB_INCSR_FFNOTEMPT 0x02 2323 #define USB_INCSR_INPKTRDY 0x01 2324 #define USB_OUTCSRH_AUTOCLR 0x80 2325 #define USB_OUTCSRH_ISO 0x40 2326 #define USB_OUTCSRH_DMAREQENAB 0x20 2327 #define USB_OUTCSRH_DNYT 0x10 2328 #define USB_OUTCSRH_DMAREQMODE 0x08 2329 #define USB_OUTCSR_CDT 0x80 2330 #define USB_OUTCSR_SENTSTALL 0x40 2331 #define USB_OUTCSR_SENDSTALL 0x20 2332 #define USB_OUTCSR_FF 0x10 2333 #define USB_OUTCSR_DATAERR 0x08 2334 #define USB_OUTCSR_OVERRUN 0x04 2335 #define USB_OUTCSR_FFFULL 0x02 2336 #define USB_OUTCSR_OUTPKTRDY 0x01 2337 2338 /* Testmode register bits */ 2339 #define USB_TEST_SE0NAK 0x01 2340 #define USB_TEST_J 0x02 2341 #define USB_TEST_K 0x04 2342 #define USB_TEST_PACKET 0x08 2343 2344 /* DMA control bits */ 2345 #define USB_CNTL_ENA 0x01 2346 #define USB_CNTL_DIR_IN 0x02 2347 #define USB_CNTL_MODE_1 0x04 2348 #define USB_CNTL_INTR_EN 0x08 2349 #define USB_CNTL_EP(n) ((n) << 4) 2350 #define USB_CNTL_BURST_0 (0 << 9) 2351 #define USB_CNTL_BURST_4 (1 << 9) 2352 #define USB_CNTL_BURST_8 (2 << 9) 2353 #define USB_CNTL_BURST_16 (3 << 9) 2354 2355 2356 2357 /* Module Operation Definitions */ 2358 #ifndef __ASSEMBLY__ 2359 2360 2361 /* GPIO Pins Description */ 2362 /* PORT 0: */ 2363 /* PIN/BIT N FUNC0 FUNC1 */ 2364 /* 0 D0 - */ 2365 /* 1 D1 - */ 2366 /* 2 D2 - */ 2367 /* 3 D3 - */ 2368 /* 4 D4 - */ 2369 /* 5 D5 - */ 2370 /* 6 D6 - */ 2371 /* 7 D7 - */ 2372 /* 8 D8 - */ 2373 /* 9 D9 - */ 2374 /* 10 D10 - */ 2375 /* 11 D11 - */ 2376 /* 12 D12 - */ 2377 /* 13 D13 - */ 2378 /* 14 D14 - */ 2379 /* 15 D15 - */ 2380 /* 16 D16 - */ 2381 /* 17 D17 - */ 2382 /* 18 D18 - */ 2383 /* 19 D19 - */ 2384 /* 20 D20 - */ 2385 /* 21 D21 - */ 2386 /* 22 D22 - */ 2387 /* 23 D23 - */ 2388 /* 24 D24 - */ 2389 /* 25 D25 - */ 2390 /* 26 D26 - */ 2391 /* 27 D27 - */ 2392 /* 28 D28 - */ 2393 /* 29 D29 - */ 2394 /* 30 D30 - */ 2395 /* 31 D31 - */ 2396 /*------------------------------------------------------ */ 2397 /* PORT 1: */ 2398 /* */ 2399 /* PIN/BIT N FUNC0 FUNC1 */ 2400 /* 0 A0 - */ 2401 /* 1 A1 - */ 2402 /* 2 A2 - */ 2403 /* 3 A3 - */ 2404 /* 4 A4 - */ 2405 /* 5 A5 - */ 2406 /* 6 A6 - */ 2407 /* 7 A7 - */ 2408 /* 8 A8 - */ 2409 /* 9 A9 - */ 2410 /* 10 A10 - */ 2411 /* 11 A11 - */ 2412 /* 12 A12 - */ 2413 /* 13 A13 - */ 2414 /* 14 A14 - */ 2415 /* 15 A15/CL - */ 2416 /* 16 A16/AL - */ 2417 /* 17 LCD_CLS A21 */ 2418 /* 18 LCD_SPL A22 */ 2419 /* 19 DCS# - */ 2420 /* 20 RAS# - */ 2421 /* 21 CAS# - */ 2422 /* 22 RDWE#/BUFD# - */ 2423 /* 23 CKE - */ 2424 /* 24 CKO - */ 2425 /* 25 CS1# - */ 2426 /* 26 CS2# - */ 2427 /* 27 CS3# - */ 2428 /* 28 CS4# - */ 2429 /* 29 RD# - */ 2430 /* 30 WR# - */ 2431 /* 31 WE0# - */ 2432 /* Note: PIN15&16 are CL&AL when connecting to NAND flash. */ 2433 /*------------------------------------------------------ */ 2434 /* PORT 2: */ 2435 /* */ 2436 /* PIN/BIT N FUNC0 FUNC1 */ 2437 /* 0 LCD_D0 - */ 2438 /* 1 LCD_D1 - */ 2439 /* 2 LCD_D2 - */ 2440 /* 3 LCD_D3 - */ 2441 /* 4 LCD_D4 - */ 2442 /* 5 LCD_D5 - */ 2443 /* 6 LCD_D6 - */ 2444 /* 7 LCD_D7 - */ 2445 /* 8 LCD_D8 - */ 2446 /* 9 LCD_D9 - */ 2447 /* 10 LCD_D10 - */ 2448 /* 11 LCD_D11 - */ 2449 /* 12 LCD_D12 - */ 2450 /* 13 LCD_D13 - */ 2451 /* 14 LCD_D14 - */ 2452 /* 15 LCD_D15 - */ 2453 /* 16 LCD_D16 - */ 2454 /* 17 LCD_D17 - */ 2455 /* 18 LCD_PCLK - */ 2456 /* 19 LCD_HSYNC - */ 2457 /* 20 LCD_VSYNC - */ 2458 /* 21 LCD_DE - */ 2459 /* 22 LCD_PS A19 */ 2460 /* 23 LCD_REV A20 */ 2461 /* 24 WE1# - */ 2462 /* 25 WE2# - */ 2463 /* 26 WE3# - */ 2464 /* 27 WAIT# - */ 2465 /* 28 FRE# - */ 2466 /* 29 FWE# - */ 2467 /* 30(NOTE:FRB#) - - */ 2468 /* 31 - - */ 2469 /* NOTE(1): PIN30 is used for FRB# when connecting to NAND flash. */ 2470 /*------------------------------------------------------ */ 2471 /* PORT 3: */ 2472 /* */ 2473 /* PIN/BIT N FUNC0 FUNC1 */ 2474 /* 0 CIM_D0 - */ 2475 /* 1 CIM_D1 - */ 2476 /* 2 CIM_D2 - */ 2477 /* 3 CIM_D3 - */ 2478 /* 4 CIM_D4 - */ 2479 /* 5 CIM_D5 - */ 2480 /* 6 CIM_D6 - */ 2481 /* 7 CIM_D7 - */ 2482 /* 8 MSC_CMD - */ 2483 /* 9 MSC_CLK - */ 2484 /* 10 MSC_D0 - */ 2485 /* 11 MSC_D1 - */ 2486 /* 12 MSC_D2 - */ 2487 /* 13 MSC_D3 - */ 2488 /* 14 CIM_MCLK - */ 2489 /* 15 CIM_PCLK - */ 2490 /* 16 CIM_VSYNC - */ 2491 /* 17 CIM_HSYNC - */ 2492 /* 18 SSI_CLK SCLK_RSTN */ 2493 /* 19 SSI_CE0# BIT_CLK(AIC) */ 2494 /* 20 SSI_DT SDATA_OUT(AIC) */ 2495 /* 21 SSI_DR SDATA_IN(AIC) */ 2496 /* 22 SSI_CE1#&GPC SYNC(AIC) */ 2497 /* 23 PWM0 I2C_SDA */ 2498 /* 24 PWM1 I2C_SCK */ 2499 /* 25 PWM2 UART0_TxD */ 2500 /* 26 PWM3 UART0_RxD */ 2501 /* 27 PWM4 A17 */ 2502 /* 28 PWM5 A18 */ 2503 /* 29 - - */ 2504 /* 30 PWM6 UART0_CTS/UART1_RxD */ 2505 /* 31 PWM7 UART0_RTS/UART1_TxD */ 2506 /* 2507 * p is the port number (0,1,2,3) 2508 * o is the pin offset (0-31) inside the port 2509 * n is the absolute number of a pin (0-127), regardless of the port 2510 */ 2511 2512 /* Function Pins Mode */ 2513 2514 #define __gpio_as_func0(n) \ 2515 do { \ 2516 unsigned int p, o; \ 2517 p = (n) / 32; \ 2518 o = (n) % 32; \ 2519 REG_GPIO_PXFUNS(p) = (1 << o); \ 2520 REG_GPIO_PXSELC(p) = (1 << o); \ 2521 } while (0) 2522 2523 #define __gpio_as_func1(n) \ 2524 do { \ 2525 unsigned int p, o; \ 2526 p = (n) / 32; \ 2527 o = (n) % 32; \ 2528 REG_GPIO_PXFUNS(p) = (1 << o); \ 2529 REG_GPIO_PXSELS(p) = (1 << o); \ 2530 } while (0) 2531 2532 /* 2533 * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, 2534 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3# 2535 */ 2536 #define __gpio_as_sdram_32bit() \ 2537 do { \ 2538 REG_GPIO_PXFUNS(0) = 0xffffffff; \ 2539 REG_GPIO_PXSELC(0) = 0xffffffff; \ 2540 REG_GPIO_PXPES(0) = 0xffffffff; \ 2541 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ 2542 REG_GPIO_PXSELC(1) = 0x81f9ffff; \ 2543 REG_GPIO_PXPES(1) = 0x81f9ffff; \ 2544 REG_GPIO_PXFUNS(2) = 0x07000000; \ 2545 REG_GPIO_PXSELC(2) = 0x07000000; \ 2546 REG_GPIO_PXPES(2) = 0x07000000; \ 2547 } while (0) 2548 2549 /* 2550 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, 2551 * RDWE#, CKO#, WE0#, WE1# 2552 */ 2553 #define __gpio_as_sdram_16bit_4720() \ 2554 do { \ 2555 REG_GPIO_PXFUNS(0) = 0x5442bfaa; \ 2556 REG_GPIO_PXSELC(0) = 0x5442bfaa; \ 2557 REG_GPIO_PXPES(0) = 0x5442bfaa; \ 2558 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ 2559 REG_GPIO_PXSELC(1) = 0x81f9ffff; \ 2560 REG_GPIO_PXPES(1) = 0x81f9ffff; \ 2561 REG_GPIO_PXFUNS(2) = 0x01000000; \ 2562 REG_GPIO_PXSELC(2) = 0x01000000; \ 2563 REG_GPIO_PXPES(2) = 0x01000000; \ 2564 } while (0) 2565 2566 /* 2567 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#, 2568 * RDWE#, CKO#, WE0#, WE1# 2569 */ 2570 #define __gpio_as_sdram_16bit_4725() \ 2571 do { \ 2572 REG_GPIO_PXFUNS(0) = 0x0000ffff; \ 2573 REG_GPIO_PXSELC(0) = 0x0000ffff; \ 2574 REG_GPIO_PXPES(0) = 0x0000ffff; \ 2575 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \ 2576 REG_GPIO_PXSELC(1) = 0x81f9ffff; \ 2577 REG_GPIO_PXPES(1) = 0x81f9ffff; \ 2578 REG_GPIO_PXFUNS(2) = 0x01000000; \ 2579 REG_GPIO_PXSELC(2) = 0x01000000; \ 2580 REG_GPIO_PXPES(2) = 0x01000000; \ 2581 } while (0) 2582 2583 2584 /* 2585 * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD# 2586 */ 2587 #define __gpio_as_nand() \ 2588 do { \ 2589 REG_GPIO_PXFUNS(1) = 0x02018000; \ 2590 REG_GPIO_PXSELC(1) = 0x02018000; \ 2591 REG_GPIO_PXPES(1) = 0x02018000; \ 2592 REG_GPIO_PXFUNS(2) = 0x30000000; \ 2593 REG_GPIO_PXSELC(2) = 0x30000000; \ 2594 REG_GPIO_PXPES(2) = 0x30000000; \ 2595 REG_GPIO_PXFUNC(2) = 0x40000000; \ 2596 REG_GPIO_PXSELC(2) = 0x40000000; \ 2597 REG_GPIO_PXDIRC(2) = 0x40000000; \ 2598 REG_GPIO_PXPES(2) = 0x40000000; \ 2599 REG_GPIO_PXFUNS(1) = 0x00400000; \ 2600 REG_GPIO_PXSELC(1) = 0x00400000; \ 2601 } while (0) 2602 2603 /* 2604 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7 2605 */ 2606 #define __gpio_as_nor_8bit() \ 2607 do { \ 2608 REG_GPIO_PXFUNS(0) = 0x000000ff; \ 2609 REG_GPIO_PXSELC(0) = 0x000000ff; \ 2610 REG_GPIO_PXPES(0) = 0x000000ff; \ 2611 REG_GPIO_PXFUNS(1) = 0x7041ffff; \ 2612 REG_GPIO_PXSELC(1) = 0x7041ffff; \ 2613 REG_GPIO_PXPES(1) = 0x7041ffff; \ 2614 REG_GPIO_PXFUNS(1) = 0x00060000; \ 2615 REG_GPIO_PXSELS(1) = 0x00060000; \ 2616 REG_GPIO_PXPES(1) = 0x00060000; \ 2617 REG_GPIO_PXFUNS(2) = 0x08000000; \ 2618 REG_GPIO_PXSELC(2) = 0x08000000; \ 2619 REG_GPIO_PXPES(2) = 0x08000000; \ 2620 REG_GPIO_PXFUNS(2) = 0x00c00000; \ 2621 REG_GPIO_PXSELS(2) = 0x00c00000; \ 2622 REG_GPIO_PXPES(2) = 0x00c00000; \ 2623 REG_GPIO_PXFUNS(3) = 0x18000000; \ 2624 REG_GPIO_PXSELS(3) = 0x18000000; \ 2625 REG_GPIO_PXPES(3) = 0x18000000; \ 2626 } while (0) 2627 2628 /* 2629 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15 2630 */ 2631 #define __gpio_as_nor_16bit() \ 2632 do { \ 2633 REG_GPIO_PXFUNS(0) = 0x0000ffff; \ 2634 REG_GPIO_PXSELC(0) = 0x0000ffff; \ 2635 REG_GPIO_PXPES(0) = 0x0000ffff; \ 2636 REG_GPIO_PXFUNS(1) = 0x7041ffff; \ 2637 REG_GPIO_PXSELC(1) = 0x7041ffff; \ 2638 REG_GPIO_PXPES(1) = 0x7041ffff; \ 2639 REG_GPIO_PXFUNS(1) = 0x00060000; \ 2640 REG_GPIO_PXSELS(1) = 0x00060000; \ 2641 REG_GPIO_PXPES(1) = 0x00060000; \ 2642 REG_GPIO_PXFUNS(2) = 0x08000000; \ 2643 REG_GPIO_PXSELC(2) = 0x08000000; \ 2644 REG_GPIO_PXPES(2) = 0x08000000; \ 2645 REG_GPIO_PXFUNS(2) = 0x00c00000; \ 2646 REG_GPIO_PXSELS(2) = 0x00c00000; \ 2647 REG_GPIO_PXPES(2) = 0x00c00000; \ 2648 REG_GPIO_PXFUNS(3) = 0x18000000; \ 2649 REG_GPIO_PXSELS(3) = 0x18000000; \ 2650 REG_GPIO_PXPES(3) = 0x18000000; \ 2651 } while (0) 2652 2653 /* 2654 * UART0_TxD, UART_RxD0 2655 */ 2656 #define __gpio_as_uart0() \ 2657 do { \ 2658 REG_GPIO_PXFUNS(3) = 0x06000000; \ 2659 REG_GPIO_PXSELS(3) = 0x06000000; \ 2660 REG_GPIO_PXPES(3) = 0x06000000; \ 2661 } while (0) 2662 2663 #define __gpio_jtag_to_uart0() \ 2664 do { \ 2665 REG_GPIO_PXSELS(2) = 0x80000000; \ 2666 } while (0) 2667 2668 /* 2669 * UART0_CTS, UART0_RTS 2670 */ 2671 #define __gpio_as_ctsrts() \ 2672 do { \ 2673 REG_GPIO_PXFUNS(3) = 0xc0000000; \ 2674 REG_GPIO_PXSELS(3) = 0xc0000000; \ 2675 REG_GPIO_PXTRGC(3) = 0xc0000000; \ 2676 REG_GPIO_PXPES(3) = 0xc0000000; \ 2677 } while (0) 2678 2679 /* 2680 * UART1_TxD, UART1_RxD1 2681 */ 2682 #define __gpio_as_uart1() \ 2683 do { \ 2684 REG_GPIO_PXFUNS(3) = 0xc0000000; \ 2685 REG_GPIO_PXSELC(3) = 0xc0000000; \ 2686 REG_GPIO_PXTRGS(3) = 0xc0000000; \ 2687 REG_GPIO_PXPES(3) = 0xc0000000; \ 2688 } while (0) 2689 2690 /* 2691 * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE 2692 */ 2693 #define __gpio_as_lcd_16bit() \ 2694 do { \ 2695 REG_GPIO_PXFUNS(2) = 0x003cffff; \ 2696 REG_GPIO_PXSELC(2) = 0x003cffff; \ 2697 REG_GPIO_PXPES(2) = 0x003cffff; \ 2698 } while (0) 2699 2700 /* 2701 * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE 2702 */ 2703 #define __gpio_as_lcd_18bit() \ 2704 do { \ 2705 REG_GPIO_PXFUNS(2) = 0x003fffff; \ 2706 REG_GPIO_PXSELC(2) = 0x003fffff; \ 2707 REG_GPIO_PXPES(2) = 0x003fffff; \ 2708 } while (0) 2709 2710 2711 /* LCD_D0~LCD_D7, SLCD_CLK, SLCD_RS, SLCD_CS, LCD_DE */ 2712 #define __gpio_as_slcd_8bit() \ 2713 do { \ 2714 REG_GPIO_PXFUNS(2) = 0x003c00ff; \ 2715 REG_GPIO_PXSELC(2) = 0x003c00ff; \ 2716 } while (0) 2717 2718 /* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */ 2719 #define __gpio_as_slcd_9bit() \ 2720 do { \ 2721 REG_GPIO_PXFUNS(2) = 0x001801ff; \ 2722 REG_GPIO_PXSELC(2) = 0x001801ff; \ 2723 } while (0) 2724 2725 /* LCD_D0~LCD_D15, SLCD_RS, SLCD_CS */ 2726 #define __gpio_as_slcd_16bit() \ 2727 do { \ 2728 REG_GPIO_PXFUNS(2) = 0x0018ffff; \ 2729 REG_GPIO_PXSELC(2) = 0x0018ffff; \ 2730 } while (0) 2731 2732 /* LCD_D0~LCD_D17, SLCD_RS, SLCD_CS */ 2733 #define __gpio_as_slcd_18bit() \ 2734 do { \ 2735 REG_GPIO_PXFUNS(2) = 0x001bffff; \ 2736 REG_GPIO_PXSELC(2) = 0x001bffff; \ 2737 } while (0) 2738 /* 2739 * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC 2740 */ 2741 #define __gpio_as_cim() \ 2742 do { \ 2743 REG_GPIO_PXFUNS(3) = 0x0003c0ff; \ 2744 REG_GPIO_PXSELC(3) = 0x0003c0ff; \ 2745 REG_GPIO_PXPES(3) = 0x0003c0ff; \ 2746 } while (0) 2747 2748 /* 2749 * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET 2750 */ 2751 #define __gpio_as_aic() \ 2752 do { \ 2753 REG_GPIO_PXFUNS(3) = 0x007c0000; \ 2754 REG_GPIO_PXSELS(3) = 0x007c0000; \ 2755 REG_GPIO_PXPES(3) = 0x007c0000; \ 2756 } while (0) 2757 2758 /* 2759 * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 2760 */ 2761 #define __gpio_as_msc() \ 2762 do { \ 2763 REG_GPIO_PXFUNS(3) = 0x00003f00; \ 2764 REG_GPIO_PXSELC(3) = 0x00003f00; \ 2765 REG_GPIO_PXPES(3) = 0x00003f00; \ 2766 } while (0) 2767 2768 /* 2769 * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR 2770 */ 2771 #define __gpio_as_ssi() \ 2772 do { \ 2773 REG_GPIO_PXFUNS(3) = 0x003c0000; \ 2774 REG_GPIO_PXSELC(3) = 0x003c0000; \ 2775 REG_GPIO_PXPES(3) = 0x003c0000; \ 2776 } while (0) 2777 2778 /* 2779 * I2C_SCK, I2C_SDA 2780 */ 2781 #define __gpio_as_i2c() \ 2782 do { \ 2783 REG_GPIO_PXFUNS(3) = 0x01800000; \ 2784 REG_GPIO_PXSELS(3) = 0x01800000; \ 2785 REG_GPIO_PXPES(3) = 0x01800000; \ 2786 } while (0) 2787 2788 /* 2789 * PWM0 2790 */ 2791 #define __gpio_as_pwm0() \ 2792 do { \ 2793 REG_GPIO_PXFUNS(3) = 0x00800000; \ 2794 REG_GPIO_PXSELC(3) = 0x00800000; \ 2795 REG_GPIO_PXPES(3) = 0x00800000; \ 2796 } while (0) 2797 2798 /* 2799 * PWM1 2800 */ 2801 #define __gpio_as_pwm1() \ 2802 do { \ 2803 REG_GPIO_PXFUNS(3) = 0x01000000; \ 2804 REG_GPIO_PXSELC(3) = 0x01000000; \ 2805 REG_GPIO_PXPES(3) = 0x01000000; \ 2806 } while (0) 2807 2808 /* 2809 * PWM2 2810 */ 2811 #define __gpio_as_pwm2() \ 2812 do { \ 2813 REG_GPIO_PXFUNS(3) = 0x02000000; \ 2814 REG_GPIO_PXSELC(3) = 0x02000000; \ 2815 REG_GPIO_PXPES(3) = 0x02000000; \ 2816 } while (0) 2817 2818 /* 2819 * PWM3 2820 */ 2821 #define __gpio_as_pwm3() \ 2822 do { \ 2823 REG_GPIO_PXFUNS(3) = 0x04000000; \ 2824 REG_GPIO_PXSELC(3) = 0x04000000; \ 2825 REG_GPIO_PXPES(3) = 0x04000000; \ 2826 } while (0) 2827 2828 /* 2829 * PWM4 2830 */ 2831 #define __gpio_as_pwm4() \ 2832 do { \ 2833 REG_GPIO_PXFUNS(3) = 0x08000000; \ 2834 REG_GPIO_PXSELC(3) = 0x08000000; \ 2835 REG_GPIO_PXPES(3) = 0x08000000; \ 2836 } while (0) 2837 2838 /* 2839 * PWM5 2840 */ 2841 #define __gpio_as_pwm5() \ 2842 do { \ 2843 REG_GPIO_PXFUNS(3) = 0x10000000; \ 2844 REG_GPIO_PXSELC(3) = 0x10000000; \ 2845 REG_GPIO_PXPES(3) = 0x10000000; \ 2846 } while (0) 2847 2848 /* 2849 * PWM6 2850 */ 2851 #define __gpio_as_pwm6() \ 2852 do { \ 2853 REG_GPIO_PXFUNS(3) = 0x40000000; \ 2854 REG_GPIO_PXSELC(3) = 0x40000000; \ 2855 REG_GPIO_PXPES(3) = 0x40000000; \ 2856 } while (0) 2857 2858 /* 2859 * PWM7 2860 */ 2861 #define __gpio_as_pwm7() \ 2862 do { \ 2863 REG_GPIO_PXFUNS(3) = 0x80000000; \ 2864 REG_GPIO_PXSELC(3) = 0x80000000; \ 2865 REG_GPIO_PXPES(3) = 0x80000000; \ 2866 } while (0) 2867 2868 /* 2869 * n = 0 ~ 7 2870 */ 2871 #define __gpio_as_pwm(n) __gpio_as_pwm##n() 2872 2873 /* GPIO or Interrupt Mode */ 2874 2875 #define __gpio_get_port(p) (REG_GPIO_PXPIN(p)) 2876 2877 #define __gpio_port_as_output(p, o) \ 2878 do { \ 2879 REG_GPIO_PXFUNC(p) = (1 << (o)); \ 2880 REG_GPIO_PXSELC(p) = (1 << (o)); \ 2881 REG_GPIO_PXDIRS(p) = (1 << (o)); \ 2882 } while (0) 2883 2884 #define __gpio_port_as_input(p, o) \ 2885 do { \ 2886 REG_GPIO_PXFUNC(p) = (1 << (o)); \ 2887 REG_GPIO_PXSELC(p) = (1 << (o)); \ 2888 REG_GPIO_PXDIRC(p) = (1 << (o)); \ 2889 } while (0) 2890 2891 #define __gpio_as_output(n) \ 2892 do { \ 2893 unsigned int p, o; \ 2894 p = (n) / 32; \ 2895 o = (n) % 32; \ 2896 __gpio_port_as_output(p, o); \ 2897 } while (0) 2898 2899 #define __gpio_as_input(n) \ 2900 do { \ 2901 unsigned int p, o; \ 2902 p = (n) / 32; \ 2903 o = (n) % 32; \ 2904 __gpio_port_as_input(p, o); \ 2905 } while (0) 2906 2907 #define __gpio_set_pin(n) \ 2908 do { \ 2909 unsigned int p, o; \ 2910 p = (n) / 32; \ 2911 o = (n) % 32; \ 2912 REG_GPIO_PXDATS(p) = (1 << o); \ 2913 } while (0) 2914 2915 #define __gpio_clear_pin(n) \ 2916 do { \ 2917 unsigned int p, o; \ 2918 p = (n) / 32; \ 2919 o = (n) % 32; \ 2920 REG_GPIO_PXDATC(p) = (1 << o); \ 2921 } while (0) 2922 2923 #define __gpio_get_pin(n) \ 2924 ({ \ 2925 unsigned int p, o, v; \ 2926 p = (n) / 32; \ 2927 o = (n) % 32; \ 2928 if (__gpio_get_port(p) & (1 << o)) \ 2929 v = 1; \ 2930 else \ 2931 v = 0; \ 2932 v; \ 2933 }) 2934 2935 #define __gpio_as_irq_high_level(n) \ 2936 do { \ 2937 unsigned int p, o; \ 2938 p = (n) / 32; \ 2939 o = (n) % 32; \ 2940 REG_GPIO_PXIMS(p) = (1 << o); \ 2941 REG_GPIO_PXTRGC(p) = (1 << o); \ 2942 REG_GPIO_PXFUNC(p) = (1 << o); \ 2943 REG_GPIO_PXSELS(p) = (1 << o); \ 2944 REG_GPIO_PXDIRS(p) = (1 << o); \ 2945 REG_GPIO_PXFLGC(p) = (1 << o); \ 2946 REG_GPIO_PXIMC(p) = (1 << o); \ 2947 } while (0) 2948 2949 #define __gpio_as_irq_low_level(n) \ 2950 do { \ 2951 unsigned int p, o; \ 2952 p = (n) / 32; \ 2953 o = (n) % 32; \ 2954 REG_GPIO_PXIMS(p) = (1 << o); \ 2955 REG_GPIO_PXTRGC(p) = (1 << o); \ 2956 REG_GPIO_PXFUNC(p) = (1 << o); \ 2957 REG_GPIO_PXSELS(p) = (1 << o); \ 2958 REG_GPIO_PXDIRC(p) = (1 << o); \ 2959 REG_GPIO_PXFLGC(p) = (1 << o); \ 2960 REG_GPIO_PXIMC(p) = (1 << o); \ 2961 } while (0) 2962 2963 #define __gpio_as_irq_rise_edge(n) \ 2964 do { \ 2965 unsigned int p, o; \ 2966 p = (n) / 32; \ 2967 o = (n) % 32; \ 2968 REG_GPIO_PXIMS(p) = (1 << o); \ 2969 REG_GPIO_PXTRGS(p) = (1 << o); \ 2970 REG_GPIO_PXFUNC(p) = (1 << o); \ 2971 REG_GPIO_PXSELS(p) = (1 << o); \ 2972 REG_GPIO_PXDIRS(p) = (1 << o); \ 2973 REG_GPIO_PXFLGC(p) = (1 << o); \ 2974 REG_GPIO_PXIMC(p) = (1 << o); \ 2975 } while (0) 2976 2977 #define __gpio_as_irq_fall_edge(n) \ 2978 do { \ 2979 unsigned int p, o; \ 2980 p = (n) / 32; \ 2981 o = (n) % 32; \ 2982 REG_GPIO_PXIMS(p) = (1 << o); \ 2983 REG_GPIO_PXTRGS(p) = (1 << o); \ 2984 REG_GPIO_PXFUNC(p) = (1 << o); \ 2985 REG_GPIO_PXSELS(p) = (1 << o); \ 2986 REG_GPIO_PXDIRC(p) = (1 << o); \ 2987 REG_GPIO_PXFLGC(p) = (1 << o); \ 2988 REG_GPIO_PXIMC(p) = (1 << o); \ 2989 } while (0) 2990 2991 #define __gpio_mask_irq(n) \ 2992 do { \ 2993 unsigned int p, o; \ 2994 p = (n) / 32; \ 2995 o = (n) % 32; \ 2996 REG_GPIO_PXIMS(p) = (1 << o); \ 2997 } while (0) 2998 2999 #define __gpio_unmask_irq(n) \ 3000 do { \ 3001 unsigned int p, o; \ 3002 p = (n) / 32; \ 3003 o = (n) % 32; \ 3004 REG_GPIO_PXIMC(p) = (1 << o); \ 3005 } while (0) 3006 3007 #define __gpio_ack_irq(n) \ 3008 do { \ 3009 unsigned int p, o; \ 3010 p = (n) / 32; \ 3011 o = (n) % 32; \ 3012 REG_GPIO_PXFLGC(p) = (1 << o); \ 3013 } while (0) 3014 3015 #define __gpio_get_irq() \ 3016 ({ \ 3017 unsigned int p, i, tmp, v = 0; \ 3018 for (p = 3; p >= 0; p--) { \ 3019 tmp = REG_GPIO_PXFLG(p); \ 3020 for (i = 0; i < 32; i++) \ 3021 if (tmp & (1 << i)) \ 3022 v = (32*p + i); \ 3023 } \ 3024 v; \ 3025 }) 3026 3027 #define __gpio_group_irq(n) \ 3028 ({ \ 3029 register int tmp, i; \ 3030 tmp = REG_GPIO_PXFLG((n)); \ 3031 for (i=31;i>=0;i--) \ 3032 if (tmp & (1 << i)) \ 3033 break; \ 3034 i; \ 3035 }) 3036 3037 #define __gpio_enable_pull(n) \ 3038 do { \ 3039 unsigned int p, o; \ 3040 p = (n) / 32; \ 3041 o = (n) % 32; \ 3042 REG_GPIO_PXPEC(p) = (1 << o); \ 3043 } while (0) 3044 3045 #define __gpio_disable_pull(n) \ 3046 do { \ 3047 unsigned int p, o; \ 3048 p = (n) / 32; \ 3049 o = (n) % 32; \ 3050 REG_GPIO_PXPES(p) = (1 << o); \ 3051 } while (0) 3052 3053 3054 /*************************************************************************** 3055 * CPM 3056 ***************************************************************************/ 3057 #define __cpm_get_pllm() \ 3058 ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT) 3059 #define __cpm_get_plln() \ 3060 ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT) 3061 #define __cpm_get_pllod() \ 3062 ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT) 3063 3064 #define __cpm_get_cdiv() \ 3065 ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT) 3066 #define __cpm_get_hdiv() \ 3067 ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT) 3068 #define __cpm_get_pdiv() \ 3069 ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT) 3070 #define __cpm_get_mdiv() \ 3071 ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT) 3072 #define __cpm_get_ldiv() \ 3073 ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT) 3074 #define __cpm_get_udiv() \ 3075 ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT) 3076 #define __cpm_get_i2sdiv() \ 3077 ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT) 3078 #define __cpm_get_pixdiv() \ 3079 ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT) 3080 #define __cpm_get_mscdiv() \ 3081 ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT) 3082 3083 #define __cpm_set_cdiv(v) \ 3084 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT))) 3085 #define __cpm_set_hdiv(v) \ 3086 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT))) 3087 #define __cpm_set_pdiv(v) \ 3088 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT))) 3089 #define __cpm_set_mdiv(v) \ 3090 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT))) 3091 #define __cpm_set_ldiv(v) \ 3092 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT))) 3093 #define __cpm_set_udiv(v) \ 3094 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT))) 3095 #define __cpm_set_i2sdiv(v) \ 3096 (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT))) 3097 #define __cpm_set_pixdiv(v) \ 3098 (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT))) 3099 #define __cpm_set_mscdiv(v) \ 3100 (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT))) 3101 3102 #define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS) 3103 #define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS) 3104 #define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN) 3105 #define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS) 3106 #define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS) 3107 #define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE) 3108 #define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS) 3109 #define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS) 3110 3111 #define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS) 3112 #define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP) 3113 #define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN) 3114 3115 #define __cpm_get_cclk_doze_duty() \ 3116 ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT) 3117 #define __cpm_set_cclk_doze_duty(v) \ 3118 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT))) 3119 3120 #define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON) 3121 #define __cpm_idle_mode() \ 3122 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE) 3123 #define __cpm_sleep_mode() \ 3124 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP) 3125 3126 #define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff) 3127 #define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1) 3128 #define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC) 3129 #define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU) 3130 #define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC) 3131 #define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC) 3132 #define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD) 3133 #define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM) 3134 #define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC) 3135 #define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC) 3136 #define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1) 3137 #define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2) 3138 #define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI) 3139 #define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C) 3140 #define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC) 3141 #define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU) 3142 #define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0) 3143 3144 #define __cpm_start_all() (REG_CPM_CLKGR = 0x0) 3145 #define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1) 3146 #define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC) 3147 #define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU) 3148 #define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC) 3149 #define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC) 3150 #define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD) 3151 #define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM) 3152 #define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC) 3153 #define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC) 3154 #define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1) 3155 #define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2) 3156 #define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI) 3157 #define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C) 3158 #define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC) 3159 #define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU) 3160 #define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0) 3161 3162 #define __cpm_get_o1st() \ 3163 ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT) 3164 #define __cpm_set_o1st(v) \ 3165 (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT))) 3166 #define __cpm_suspend_udcphy() (REG_CPM_SCR &= ~CPM_SCR_UDCPHY_ENABLE) 3167 #define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_DISABLE) 3168 #define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE) 3169 3170 #define JZ_EXTAL CONFIG_SYS_EXTAL 3171 #define JZ_EXTAL2 32768 /* RTC clock */ 3172 3173 /* PLL output frequency */ 3174 static __inline__ unsigned int __cpm_get_pllout(void) 3175 { 3176 unsigned long m, n, no, pllout; 3177 unsigned long cppcr = REG_CPM_CPPCR; 3178 unsigned long od[4] = {1, 2, 2, 4}; 3179 if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) { 3180 m = __cpm_get_pllm() + 2; 3181 n = __cpm_get_plln() + 2; 3182 no = od[__cpm_get_pllod()]; 3183 pllout = ((JZ_EXTAL) / (n * no)) * m; 3184 } else 3185 pllout = JZ_EXTAL; 3186 return pllout; 3187 } 3188 3189 /* PLL output frequency for MSC/I2S/LCD/USB */ 3190 static __inline__ unsigned int __cpm_get_pllout2(void) 3191 { 3192 if (REG_CPM_CPCCR & CPM_CPCCR_PCS) 3193 return __cpm_get_pllout(); 3194 else 3195 return __cpm_get_pllout()/2; 3196 } 3197 3198 /* CPU core clock */ 3199 static __inline__ unsigned int __cpm_get_cclk(void) 3200 { 3201 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 3202 3203 return __cpm_get_pllout() / div[__cpm_get_cdiv()]; 3204 } 3205 3206 /* AHB system bus clock */ 3207 static __inline__ unsigned int __cpm_get_hclk(void) 3208 { 3209 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 3210 3211 return __cpm_get_pllout() / div[__cpm_get_hdiv()]; 3212 } 3213 3214 /* Memory bus clock */ 3215 static __inline__ unsigned int __cpm_get_mclk(void) 3216 { 3217 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 3218 3219 return __cpm_get_pllout() / div[__cpm_get_mdiv()]; 3220 } 3221 3222 /* APB peripheral bus clock */ 3223 static __inline__ unsigned int __cpm_get_pclk(void) 3224 { 3225 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 3226 3227 return __cpm_get_pllout() / div[__cpm_get_pdiv()]; 3228 } 3229 3230 /* LCDC module clock */ 3231 static __inline__ unsigned int __cpm_get_lcdclk(void) 3232 { 3233 return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1); 3234 } 3235 3236 /* LCD pixel clock */ 3237 static __inline__ unsigned int __cpm_get_pixclk(void) 3238 { 3239 return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1); 3240 } 3241 3242 /* I2S clock */ 3243 static __inline__ unsigned int __cpm_get_i2sclk(void) 3244 { 3245 if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) { 3246 return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1); 3247 } 3248 else { 3249 return JZ_EXTAL; 3250 } 3251 } 3252 3253 /* USB clock */ 3254 static __inline__ unsigned int __cpm_get_usbclk(void) 3255 { 3256 if (REG_CPM_CPCCR & CPM_CPCCR_UCS) { 3257 return __cpm_get_pllout2() / (__cpm_get_udiv() + 1); 3258 } 3259 else { 3260 return JZ_EXTAL; 3261 } 3262 } 3263 3264 /* MSC clock */ 3265 static __inline__ unsigned int __cpm_get_mscclk(void) 3266 { 3267 return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1); 3268 } 3269 3270 /* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */ 3271 static __inline__ unsigned int __cpm_get_extalclk(void) 3272 { 3273 return JZ_EXTAL; 3274 } 3275 3276 /* RTC clock for CPM,INTC,RTC,TCU,WDT */ 3277 static __inline__ unsigned int __cpm_get_rtcclk(void) 3278 { 3279 return JZ_EXTAL2; 3280 } 3281 3282 /* 3283 * Output 24MHz for SD and 16MHz for MMC. 3284 */ 3285 static inline void __cpm_select_msc_clk(int sd) 3286 { 3287 unsigned int pllout2 = __cpm_get_pllout2(); 3288 unsigned int div = 0; 3289 3290 if (sd) { 3291 div = pllout2 / 24000000; 3292 } 3293 else { 3294 div = pllout2 / 16000000; 3295 } 3296 3297 REG_CPM_MSCCDR = div - 1; 3298 } 3299 3300 /* 3301 * TCU 3302 */ 3303 /* where 'n' is the TCU channel */ 3304 #define __tcu_select_extalclk(n) \ 3305 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN) 3306 #define __tcu_select_rtcclk(n) \ 3307 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN) 3308 #define __tcu_select_pclk(n) \ 3309 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN) 3310 3311 #define __tcu_select_clk_div1(n) \ 3312 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1) 3313 #define __tcu_select_clk_div4(n) \ 3314 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4) 3315 #define __tcu_select_clk_div16(n) \ 3316 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16) 3317 #define __tcu_select_clk_div64(n) \ 3318 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64) 3319 #define __tcu_select_clk_div256(n) \ 3320 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256) 3321 #define __tcu_select_clk_div1024(n) \ 3322 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024) 3323 3324 #define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN ) 3325 #define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN ) 3326 3327 #define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH ) 3328 #define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH ) 3329 3330 #define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD ) 3331 #define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD ) 3332 3333 #define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) ) 3334 #define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) ) 3335 3336 #define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) ) 3337 #define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) ) 3338 #define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) ) 3339 #define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) ) 3340 #define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) ) 3341 #define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) ) 3342 #define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) ) 3343 #define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) ) 3344 #define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) ) 3345 #define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) ) 3346 3347 #define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC ) 3348 #define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) ) 3349 3350 #define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC ) 3351 #define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) ) 3352 3353 #define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC ) 3354 #define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) ) 3355 3356 #define __tcu_get_count(n) ( REG_TCU_TCNT((n)) ) 3357 #define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) ) 3358 #define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) ) 3359 #define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) ) 3360 3361 3362 /*************************************************************************** 3363 * WDT 3364 ***************************************************************************/ 3365 #define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN ) 3366 #define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN ) 3367 #define __wdt_set_count(v) ( REG_WDT_TCNT = (v) ) 3368 #define __wdt_set_data(v) ( REG_WDT_TDR = (v) ) 3369 3370 #define __wdt_select_extalclk() \ 3371 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN) 3372 #define __wdt_select_rtcclk() \ 3373 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN) 3374 #define __wdt_select_pclk() \ 3375 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN) 3376 3377 #define __wdt_select_clk_div1() \ 3378 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1) 3379 #define __wdt_select_clk_div4() \ 3380 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4) 3381 #define __wdt_select_clk_div16() \ 3382 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16) 3383 #define __wdt_select_clk_div64() \ 3384 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64) 3385 #define __wdt_select_clk_div256() \ 3386 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256) 3387 #define __wdt_select_clk_div1024() \ 3388 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024) 3389 3390 3391 /*************************************************************************** 3392 * UART 3393 ***************************************************************************/ 3394 3395 #define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE ) 3396 #define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE ) 3397 3398 #define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE ) 3399 #define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE ) 3400 3401 #define __uart_enable_receive_irq() \ 3402 ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) 3403 #define __uart_disable_receive_irq() \ 3404 ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) 3405 3406 #define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP ) 3407 #define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP ) 3408 3409 #define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 ) 3410 3411 #define __uart_set_baud(devclk, baud) \ 3412 do { \ 3413 REG8(UART0_LCR) |= UARTLCR_DLAB; \ 3414 REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \ 3415 REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ 3416 REG8(UART0_LCR) &= ~UARTLCR_DLAB; \ 3417 } while (0) 3418 3419 #define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 ) 3420 #define __uart_clear_errors() \ 3421 ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) ) 3422 3423 #define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 ) 3424 #define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 ) 3425 #define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) ) 3426 #define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) 3427 #define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 ) 3428 #define __uart_receive_char() REG8(UART0_RDR) 3429 #define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) 3430 #define __uart_enable_irda() \ 3431 /* Tx high pulse as 0, Rx low pulse as 0 */ \ 3432 ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) 3433 3434 3435 /*************************************************************************** 3436 * DMAC 3437 ***************************************************************************/ 3438 3439 /* n is the DMA channel (0 - 5) */ 3440 3441 #define __dmac_enable_module() \ 3442 ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR ) 3443 #define __dmac_disable_module() \ 3444 ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE ) 3445 3446 /* p=0,1,2,3 */ 3447 #define __dmac_set_priority(p) \ 3448 do { \ 3449 REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ 3450 REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ 3451 } while (0) 3452 3453 #define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT ) 3454 #define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR ) 3455 3456 #define __dmac_enable_descriptor(n) \ 3457 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES ) 3458 #define __dmac_disable_descriptor(n) \ 3459 ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES ) 3460 3461 #define __dmac_enable_channel(n) \ 3462 ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN ) 3463 #define __dmac_disable_channel(n) \ 3464 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN ) 3465 #define __dmac_channel_enabled(n) \ 3466 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN ) 3467 3468 #define __dmac_channel_enable_irq(n) \ 3469 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE ) 3470 #define __dmac_channel_disable_irq(n) \ 3471 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE ) 3472 3473 #define __dmac_channel_transmit_halt_detected(n) \ 3474 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT ) 3475 #define __dmac_channel_transmit_end_detected(n) \ 3476 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT ) 3477 #define __dmac_channel_address_error_detected(n) \ 3478 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR ) 3479 #define __dmac_channel_count_terminated_detected(n) \ 3480 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT ) 3481 #define __dmac_channel_descriptor_invalid_detected(n) \ 3482 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV ) 3483 3484 #define __dmac_channel_clear_transmit_halt(n) \ 3485 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) 3486 #define __dmac_channel_clear_transmit_end(n) \ 3487 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT ) 3488 #define __dmac_channel_clear_address_error(n) \ 3489 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) 3490 #define __dmac_channel_clear_count_terminated(n) \ 3491 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT ) 3492 #define __dmac_channel_clear_descriptor_invalid(n) \ 3493 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV ) 3494 3495 #define __dmac_channel_set_single_mode(n) \ 3496 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM ) 3497 #define __dmac_channel_set_block_mode(n) \ 3498 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM ) 3499 3500 #define __dmac_channel_set_transfer_unit_32bit(n) \ 3501 do { \ 3502 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3503 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \ 3504 } while (0) 3505 3506 #define __dmac_channel_set_transfer_unit_16bit(n) \ 3507 do { \ 3508 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3509 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \ 3510 } while (0) 3511 3512 #define __dmac_channel_set_transfer_unit_8bit(n) \ 3513 do { \ 3514 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3515 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \ 3516 } while (0) 3517 3518 #define __dmac_channel_set_transfer_unit_16byte(n) \ 3519 do { \ 3520 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3521 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \ 3522 } while (0) 3523 3524 #define __dmac_channel_set_transfer_unit_32byte(n) \ 3525 do { \ 3526 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \ 3527 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \ 3528 } while (0) 3529 3530 /* w=8,16,32 */ 3531 #define __dmac_channel_set_dest_port_width(n,w) \ 3532 do { \ 3533 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \ 3534 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \ 3535 } while (0) 3536 3537 /* w=8,16,32 */ 3538 #define __dmac_channel_set_src_port_width(n,w) \ 3539 do { \ 3540 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \ 3541 REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \ 3542 } while (0) 3543 3544 /* v=0-15 */ 3545 #define __dmac_channel_set_rdil(n,v) \ 3546 do { \ 3547 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \ 3548 REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \ 3549 } while (0) 3550 3551 #define __dmac_channel_dest_addr_fixed(n) \ 3552 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI ) 3553 #define __dmac_channel_dest_addr_increment(n) \ 3554 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI ) 3555 3556 #define __dmac_channel_src_addr_fixed(n) \ 3557 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI ) 3558 #define __dmac_channel_src_addr_increment(n) \ 3559 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI ) 3560 3561 #define __dmac_channel_set_doorbell(n) \ 3562 ( REG_DMAC_DMADBSR = (1 << (n)) ) 3563 3564 #define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) ) 3565 #define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) ) 3566 3567 static __inline__ int __dmac_get_irq(void) 3568 { 3569 int i; 3570 for (i = 0; i < MAX_DMA_NUM; i++) 3571 if (__dmac_channel_irq_detected(i)) 3572 return i; 3573 return -1; 3574 } 3575 3576 3577 /*************************************************************************** 3578 * AIC (AC'97 & I2S Controller) 3579 ***************************************************************************/ 3580 3581 #define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) 3582 #define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) 3583 3584 #define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) 3585 #define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) 3586 3587 #define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) 3588 #define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) 3589 #define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST ) 3590 3591 #define __aic_reset() \ 3592 do { \ 3593 REG_AIC_FR |= AIC_FR_RST; \ 3594 } while(0) 3595 3596 3597 #define __aic_set_transmit_trigger(n) \ 3598 do { \ 3599 REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ 3600 REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \ 3601 } while(0) 3602 3603 #define __aic_set_receive_trigger(n) \ 3604 do { \ 3605 REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ 3606 REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \ 3607 } while(0) 3608 3609 #define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) 3610 #define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) 3611 #define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) 3612 #define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) 3613 #define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) 3614 #define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) 3615 3616 #define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH ) 3617 #define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH ) 3618 3619 #define __aic_enable_transmit_intr() \ 3620 ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) 3621 #define __aic_disable_transmit_intr() \ 3622 ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) 3623 #define __aic_enable_receive_intr() \ 3624 ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) 3625 #define __aic_disable_receive_intr() \ 3626 ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) 3627 3628 #define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) 3629 #define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) 3630 #define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) 3631 #define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) 3632 3633 #define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S ) 3634 #define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S ) 3635 #define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW ) 3636 #define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW ) 3637 #define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU ) 3638 #define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU ) 3639 3640 #define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3 3641 #define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4 3642 #define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6 3643 #define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7 3644 #define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8 3645 #define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9 3646 3647 #define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3 3648 #define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4 3649 #define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6 3650 #define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7 3651 #define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8 3652 #define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9 3653 3654 #define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) 3655 #define __ac97_set_xs_mono() \ 3656 do { \ 3657 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ 3658 REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ 3659 } while(0) 3660 #define __ac97_set_xs_stereo() \ 3661 do { \ 3662 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ 3663 REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ 3664 } while(0) 3665 3666 /* In fact, only stereo is support now. */ 3667 #define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) 3668 #define __ac97_set_rs_mono() \ 3669 do { \ 3670 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ 3671 REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ 3672 } while(0) 3673 #define __ac97_set_rs_stereo() \ 3674 do { \ 3675 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ 3676 REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ 3677 } while(0) 3678 3679 #define __ac97_warm_reset_codec() \ 3680 do { \ 3681 REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ 3682 REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ 3683 udelay(2); \ 3684 REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ 3685 REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ 3686 } while (0) 3687 3688 #define __ac97_cold_reset_codec() \ 3689 do { \ 3690 REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ 3691 udelay(2); \ 3692 REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ 3693 } while (0) 3694 3695 /* n=8,16,18,20 */ 3696 #define __ac97_set_iass(n) \ 3697 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) 3698 #define __ac97_set_oass(n) \ 3699 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) 3700 3701 #define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) 3702 #define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) 3703 3704 /* n=8,16,18,20,24 */ 3705 /*#define __i2s_set_sample_size(n) \ 3706 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/ 3707 3708 #define __i2s_set_oss_sample_size(n) \ 3709 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT ) 3710 #define __i2s_set_iss_sample_size(n) \ 3711 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT ) 3712 3713 #define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) 3714 #define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) 3715 3716 #define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) 3717 #define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) 3718 #define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) 3719 #define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) 3720 3721 #define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) 3722 3723 #define __aic_get_transmit_resident() \ 3724 ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT ) 3725 #define __aic_get_receive_count() \ 3726 ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) 3727 3728 #define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) 3729 #define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) 3730 #define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) 3731 #define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) 3732 #define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) 3733 #define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR ) 3734 #define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR ) 3735 3736 #define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) 3737 3738 #define CODEC_READ_CMD (1 << 19) 3739 #define CODEC_WRITE_CMD (0 << 19) 3740 #define CODEC_REG_INDEX_BIT 12 3741 #define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */ 3742 #define CODEC_REG_DATA_BIT 4 3743 #define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */ 3744 3745 #define __ac97_out_rcmd_addr(reg) \ 3746 do { \ 3747 REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ 3748 } while (0) 3749 3750 #define __ac97_out_wcmd_addr(reg) \ 3751 do { \ 3752 REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ 3753 } while (0) 3754 3755 #define __ac97_out_data(value) \ 3756 do { \ 3757 REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \ 3758 } while (0) 3759 3760 #define __ac97_in_data() \ 3761 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) 3762 3763 #define __ac97_in_status_addr() \ 3764 ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) 3765 3766 #define __i2s_set_sample_rate(i2sclk, sync) \ 3767 ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) 3768 3769 #define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) 3770 #define __aic_read_rfifo() ( REG_AIC_DR ) 3771 3772 #define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC ) 3773 #define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC ) 3774 3775 /* Define next ops for AC97 compatible */ 3776 3777 #define AC97_ACSR AIC_ACSR 3778 3779 #define __ac97_enable() __aic_enable(); __aic_select_ac97() 3780 #define __ac97_disable() __aic_disable() 3781 #define __ac97_reset() __aic_reset() 3782 3783 #define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) 3784 #define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) 3785 3786 #define __ac97_enable_record() __aic_enable_record() 3787 #define __ac97_disable_record() __aic_disable_record() 3788 #define __ac97_enable_replay() __aic_enable_replay() 3789 #define __ac97_disable_replay() __aic_disable_replay() 3790 #define __ac97_enable_loopback() __aic_enable_loopback() 3791 #define __ac97_disable_loopback() __aic_disable_loopback() 3792 3793 #define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() 3794 #define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() 3795 #define __ac97_enable_receive_dma() __aic_enable_receive_dma() 3796 #define __ac97_disable_receive_dma() __aic_disable_receive_dma() 3797 3798 #define __ac97_transmit_request() __aic_transmit_request() 3799 #define __ac97_receive_request() __aic_receive_request() 3800 #define __ac97_transmit_underrun() __aic_transmit_underrun() 3801 #define __ac97_receive_overrun() __aic_receive_overrun() 3802 3803 #define __ac97_clear_errors() __aic_clear_errors() 3804 3805 #define __ac97_get_transmit_resident() __aic_get_transmit_resident() 3806 #define __ac97_get_receive_count() __aic_get_receive_count() 3807 3808 #define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() 3809 #define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() 3810 #define __ac97_enable_receive_intr() __aic_enable_receive_intr() 3811 #define __ac97_disable_receive_intr() __aic_disable_receive_intr() 3812 3813 #define __ac97_write_tfifo(v) __aic_write_tfifo(v) 3814 #define __ac97_read_rfifo() __aic_read_rfifo() 3815 3816 /* Define next ops for I2S compatible */ 3817 3818 #define I2S_ACSR AIC_I2SSR 3819 3820 #define __i2s_enable() __aic_enable(); __aic_select_i2s() 3821 #define __i2s_disable() __aic_disable() 3822 #define __i2s_reset() __aic_reset() 3823 3824 #define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) 3825 #define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) 3826 3827 #define __i2s_enable_record() __aic_enable_record() 3828 #define __i2s_disable_record() __aic_disable_record() 3829 #define __i2s_enable_replay() __aic_enable_replay() 3830 #define __i2s_disable_replay() __aic_disable_replay() 3831 #define __i2s_enable_loopback() __aic_enable_loopback() 3832 #define __i2s_disable_loopback() __aic_disable_loopback() 3833 3834 #define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() 3835 #define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() 3836 #define __i2s_enable_receive_dma() __aic_enable_receive_dma() 3837 #define __i2s_disable_receive_dma() __aic_disable_receive_dma() 3838 3839 #define __i2s_transmit_request() __aic_transmit_request() 3840 #define __i2s_receive_request() __aic_receive_request() 3841 #define __i2s_transmit_underrun() __aic_transmit_underrun() 3842 #define __i2s_receive_overrun() __aic_receive_overrun() 3843 3844 #define __i2s_clear_errors() __aic_clear_errors() 3845 3846 #define __i2s_get_transmit_resident() __aic_get_transmit_resident() 3847 #define __i2s_get_receive_count() __aic_get_receive_count() 3848 3849 #define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() 3850 #define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() 3851 #define __i2s_enable_receive_intr() __aic_enable_receive_intr() 3852 #define __i2s_disable_receive_intr() __aic_disable_receive_intr() 3853 3854 #define __i2s_write_tfifo(v) __aic_write_tfifo(v) 3855 #define __i2s_read_rfifo() __aic_read_rfifo() 3856 3857 #define __i2s_reset_codec() \ 3858 do { \ 3859 } while (0) 3860 3861 3862 /*************************************************************************** 3863 * ICDC 3864 ***************************************************************************/ 3865 #define __i2s_internal_codec() __aic_internal_codec() 3866 #define __i2s_external_codec() __aic_external_codec() 3867 3868 /*************************************************************************** 3869 * INTC 3870 ***************************************************************************/ 3871 #define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) 3872 #define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) 3873 #define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) 3874 3875 3876 /*************************************************************************** 3877 * I2C 3878 ***************************************************************************/ 3879 3880 #define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE ) 3881 #define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE ) 3882 3883 #define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA ) 3884 #define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO ) 3885 #define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC ) 3886 #define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC ) 3887 3888 #define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF ) 3889 #define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF ) 3890 #define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF ) 3891 3892 #define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) ) 3893 #define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY ) 3894 #define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND ) 3895 3896 #define __i2c_set_clk(dev_clk, i2c_clk) \ 3897 ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) 3898 3899 #define __i2c_read() ( REG_I2C_DR ) 3900 #define __i2c_write(val) ( REG_I2C_DR = (val) ) 3901 3902 3903 /*************************************************************************** 3904 * MSC 3905 ***************************************************************************/ 3906 3907 #define __msc_start_op() \ 3908 ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) 3909 3910 #define __msc_set_resto(to) ( REG_MSC_RESTO = to ) 3911 #define __msc_set_rdto(to) ( REG_MSC_RDTO = to ) 3912 #define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd ) 3913 #define __msc_set_arg(arg) ( REG_MSC_ARG = arg ) 3914 #define __msc_set_nob(nob) ( REG_MSC_NOB = nob ) 3915 #define __msc_get_nob() ( REG_MSC_NOB ) 3916 #define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len ) 3917 #define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat ) 3918 #define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) 3919 #define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) 3920 3921 #define __msc_set_cmdat_bus_width1() \ 3922 do { \ 3923 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ 3924 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \ 3925 } while(0) 3926 3927 #define __msc_set_cmdat_bus_width4() \ 3928 do { \ 3929 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ 3930 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \ 3931 } while(0) 3932 3933 #define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN ) 3934 #define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT ) 3935 #define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY ) 3936 #define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) 3937 #define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) 3938 #define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) 3939 #define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) 3940 #define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN ) 3941 3942 /* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ 3943 #define __msc_set_cmdat_res_format(r) \ 3944 do { \ 3945 REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ 3946 REG_MSC_CMDAT |= (r); \ 3947 } while(0) 3948 3949 #define __msc_clear_cmdat() \ 3950 REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ 3951 MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ 3952 MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ) 3953 3954 #define __msc_get_imask() ( REG_MSC_IMASK ) 3955 #define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff ) 3956 #define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 ) 3957 #define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) 3958 #define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) 3959 #define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) 3960 #define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) 3961 #define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES ) 3962 #define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) 3963 #define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) 3964 #define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) 3965 #define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE ) 3966 #define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) 3967 3968 /* n=0,1,2,3,4,5,6,7 */ 3969 #define __msc_set_clkrt(n) \ 3970 do { \ 3971 REG_MSC_CLKRT = n; \ 3972 } while(0) 3973 3974 #define __msc_get_ireg() ( REG_MSC_IREG ) 3975 #define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) 3976 #define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) 3977 #define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES ) 3978 #define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) 3979 #define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE ) 3980 #define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES ) 3981 #define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) 3982 #define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE ) 3983 3984 #define __msc_get_stat() ( REG_MSC_STAT ) 3985 #define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0) 3986 #define __msc_stat_crc_err() \ 3987 ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) 3988 #define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR ) 3989 #define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR ) 3990 #define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) 3991 #define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES ) 3992 #define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ ) 3993 3994 #define __msc_rd_resfifo() ( REG_MSC_RES ) 3995 #define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) 3996 #define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) 3997 3998 #define __msc_reset() \ 3999 do { \ 4000 REG_MSC_STRPCL = MSC_STRPCL_RESET; \ 4001 while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ 4002 } while (0) 4003 4004 #define __msc_start_clk() \ 4005 do { \ 4006 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \ 4007 } while (0) 4008 4009 #define __msc_stop_clk() \ 4010 do { \ 4011 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \ 4012 } while (0) 4013 4014 #define MMC_CLK 19169200 4015 #define SD_CLK 24576000 4016 4017 /* msc_clk should little than pclk and little than clk retrieve from card */ 4018 #define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ 4019 do { \ 4020 unsigned int rate, pclk, i; \ 4021 pclk = dev_clk; \ 4022 rate = type?SD_CLK:MMC_CLK; \ 4023 if (msc_clk && msc_clk < pclk) \ 4024 pclk = msc_clk; \ 4025 i = 0; \ 4026 while (pclk < rate) \ 4027 { \ 4028 i ++; \ 4029 rate >>= 1; \ 4030 } \ 4031 lv = i; \ 4032 } while(0) 4033 4034 /* divide rate to little than or equal to 400kHz */ 4035 #define __msc_calc_slow_clk_divisor(type, lv) \ 4036 do { \ 4037 unsigned int rate, i; \ 4038 rate = (type?SD_CLK:MMC_CLK)/1000/400; \ 4039 i = 0; \ 4040 while (rate > 0) \ 4041 { \ 4042 rate >>= 1; \ 4043 i ++; \ 4044 } \ 4045 lv = i; \ 4046 } while(0) 4047 4048 4049 /*************************************************************************** 4050 * SSI 4051 ***************************************************************************/ 4052 4053 #define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE ) 4054 #define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE ) 4055 #define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL ) 4056 4057 #define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) 4058 4059 #define __ssi_select_ce2() \ 4060 do { \ 4061 REG_SSI_CR0 |= SSI_CR0_FSEL; \ 4062 REG_SSI_CR1 &= ~SSI_CR1_MULTS; \ 4063 } while (0) 4064 4065 #define __ssi_select_gpc() \ 4066 do { \ 4067 REG_SSI_CR0 &= ~SSI_CR0_FSEL; \ 4068 REG_SSI_CR1 |= SSI_CR1_MULTS; \ 4069 } while (0) 4070 4071 #define __ssi_enable_tx_intr() \ 4072 ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) 4073 4074 #define __ssi_disable_tx_intr() \ 4075 ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) 4076 4077 #define __ssi_enable_rx_intr() \ 4078 ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) 4079 4080 #define __ssi_disable_rx_intr() \ 4081 ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) 4082 4083 #define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP ) 4084 #define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP ) 4085 4086 #define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV ) 4087 #define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV ) 4088 4089 #define __ssi_finish_receive() \ 4090 ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) 4091 4092 #define __ssi_disable_recvfinish() \ 4093 ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) 4094 4095 #define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH ) 4096 #define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH ) 4097 4098 #define __ssi_flush_fifo() \ 4099 ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) 4100 4101 #define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN ) 4102 4103 #define __ssi_spi_format() \ 4104 do { \ 4105 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ 4106 REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \ 4107 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ 4108 REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ 4109 } while (0) 4110 4111 /* TI's SSP format, must clear SSI_CR1.UNFIN */ 4112 #define __ssi_ssp_format() \ 4113 do { \ 4114 REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ 4115 REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \ 4116 } while (0) 4117 4118 /* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ 4119 #define __ssi_microwire_format() \ 4120 do { \ 4121 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ 4122 REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \ 4123 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ 4124 REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ 4125 REG_SSI_CR0 &= ~SSI_CR0_RFINE; \ 4126 } while (0) 4127 4128 /* CE# level (FRMHL), CE# in interval time (ITFRM), 4129 clock phase and polarity (PHA POL), 4130 interval time (SSIITR), interval characters/frame (SSIICR) */ 4131 4132 /* frmhl,endian,mcom,flen,pha,pol MASK */ 4133 #define SSICR1_MISC_MASK \ 4134 ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ 4135 | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \ 4136 4137 #define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \ 4138 do { \ 4139 REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \ 4140 REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \ 4141 (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ 4142 ((pha) << 1) | (pol); \ 4143 } while(0) 4144 4145 /* Transfer with MSB or LSB first */ 4146 #define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST ) 4147 #define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST ) 4148 4149 #define __ssi_set_frame_length(n) \ 4150 REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4) 4151 4152 /* n = 1 - 16 */ 4153 #define __ssi_set_microwire_command_length(n) \ 4154 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) 4155 4156 /* Set the clock phase for SPI */ 4157 #define __ssi_set_spi_clock_phase(n) \ 4158 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) ) 4159 4160 /* Set the clock polarity for SPI */ 4161 #define __ssi_set_spi_clock_polarity(n) \ 4162 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) 4163 4164 /* n = ix8 */ 4165 #define __ssi_set_tx_trigger(n) \ 4166 do { \ 4167 REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \ 4168 REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \ 4169 } while (0) 4170 4171 /* n = ix8 */ 4172 #define __ssi_set_rx_trigger(n) \ 4173 do { \ 4174 REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \ 4175 REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \ 4176 } while (0) 4177 4178 #define __ssi_get_txfifo_count() \ 4179 ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) 4180 4181 #define __ssi_get_rxfifo_count() \ 4182 ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) 4183 4184 #define __ssi_clear_errors() \ 4185 ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) 4186 4187 #define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END ) 4188 #define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY ) 4189 4190 #define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF ) 4191 #define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE ) 4192 #define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF ) 4193 4194 #define __ssi_set_clk(dev_clk, ssi_clk) \ 4195 ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) 4196 4197 #define __ssi_receive_data() REG_SSI_DR 4198 #define __ssi_transmit_data(v) ( REG_SSI_DR = (v) ) 4199 4200 4201 /*************************************************************************** 4202 * CIM 4203 ***************************************************************************/ 4204 4205 #define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) 4206 #define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) 4207 4208 #define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) 4209 #define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) 4210 4211 #define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) 4212 #define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) 4213 4214 #define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) 4215 #define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) 4216 4217 #define __cim_sample_data_at_pclk_falling_edge() \ 4218 ( REG_CIM_CFG |= CIM_CFG_PCP ) 4219 #define __cim_sample_data_at_pclk_rising_edge() \ 4220 ( REG_CIM_CFG &= ~CIM_CFG_PCP ) 4221 4222 #define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) 4223 #define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) 4224 4225 #define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) 4226 #define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) 4227 4228 /* n=0-7 */ 4229 #define __cim_set_data_packing_mode(n) \ 4230 do { \ 4231 REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ 4232 REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ 4233 } while (0) 4234 4235 #define __cim_enable_ccir656_progressive_mode() \ 4236 do { \ 4237 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 4238 REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ 4239 } while (0) 4240 4241 #define __cim_enable_ccir656_interlace_mode() \ 4242 do { \ 4243 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 4244 REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ 4245 } while (0) 4246 4247 #define __cim_enable_gated_clock_mode() \ 4248 do { \ 4249 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 4250 REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ 4251 } while (0) 4252 4253 #define __cim_enable_nongated_clock_mode() \ 4254 do { \ 4255 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 4256 REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ 4257 } while (0) 4258 4259 /* sclk:system bus clock 4260 * mclk: CIM master clock 4261 */ 4262 #define __cim_set_master_clk(sclk, mclk) \ 4263 do { \ 4264 REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \ 4265 REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \ 4266 } while (0) 4267 4268 #define __cim_enable_sof_intr() \ 4269 ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) 4270 #define __cim_disable_sof_intr() \ 4271 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) 4272 4273 #define __cim_enable_eof_intr() \ 4274 ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) 4275 #define __cim_disable_eof_intr() \ 4276 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) 4277 4278 #define __cim_enable_stop_intr() \ 4279 ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) 4280 #define __cim_disable_stop_intr() \ 4281 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) 4282 4283 #define __cim_enable_trig_intr() \ 4284 ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) 4285 #define __cim_disable_trig_intr() \ 4286 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) 4287 4288 #define __cim_enable_rxfifo_overflow_intr() \ 4289 ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) 4290 #define __cim_disable_rxfifo_overflow_intr() \ 4291 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) 4292 4293 /* n=1-16 */ 4294 #define __cim_set_frame_rate(n) \ 4295 do { \ 4296 REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ 4297 REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ 4298 } while (0) 4299 4300 #define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) 4301 #define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) 4302 4303 #define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) 4304 #define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) 4305 4306 /* n=4,8,12,16,20,24,28,32 */ 4307 #define __cim_set_rxfifo_trigger(n) \ 4308 do { \ 4309 REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \ 4310 REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \ 4311 } while (0) 4312 4313 #define __cim_clear_state() ( REG_CIM_STATE = 0 ) 4314 4315 #define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) 4316 #define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) 4317 #define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) 4318 #define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) 4319 #define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) 4320 #define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) 4321 #define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) 4322 #define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) 4323 4324 #define __cim_get_iid() ( REG_CIM_IID ) 4325 #define __cim_get_image_data() ( REG_CIM_RXFIFO ) 4326 #define __cim_get_dam_cmd() ( REG_CIM_CMD ) 4327 4328 #define __cim_set_da(a) ( REG_CIM_DA = (a) ) 4329 4330 /*************************************************************************** 4331 * LCD 4332 ***************************************************************************/ 4333 4334 /* Register operations using absolute positioning have been removed. */ 4335 4336 /*************************************************************************** 4337 * RTC ops 4338 ***************************************************************************/ 4339 4340 #define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY ) 4341 #define __rtc_enabled() \ 4342 do{ \ 4343 while(!__rtc_write_ready()); \ 4344 REG_RTC_RCR |= RTC_RCR_RTCE ; \ 4345 }while(0) \ 4346 4347 #define __rtc_disabled() \ 4348 do{ \ 4349 while(!__rtc_write_ready()); \ 4350 REG_RTC_RCR &= ~RTC_RCR_RTCE; \ 4351 }while(0) 4352 #define __rtc_enable_alarm() \ 4353 do{ \ 4354 while(!__rtc_write_ready()); \ 4355 REG_RTC_RCR |= RTC_RCR_AE; \ 4356 }while(0) 4357 4358 #define __rtc_disable_alarm() \ 4359 do{ \ 4360 while(!__rtc_write_ready()); \ 4361 REG_RTC_RCR &= ~RTC_RCR_AE; \ 4362 }while(0) 4363 4364 #define __rtc_enable_alarm_irq() \ 4365 do{ \ 4366 while(!__rtc_write_ready()); \ 4367 REG_RTC_RCR |= RTC_RCR_AIE; \ 4368 }while(0) 4369 4370 #define __rtc_disable_alarm_irq() \ 4371 do{ \ 4372 while(!__rtc_write_ready()); \ 4373 REG_RTC_RCR &= ~RTC_RCR_AIE; \ 4374 }while(0) 4375 #define __rtc_enable_Hz_irq() \ 4376 do{ \ 4377 while(!__rtc_write_ready()); \ 4378 REG_RTC_RCR |= RTC_RCR_HZIE; \ 4379 }while(0) 4380 4381 #define __rtc_disable_Hz_irq() \ 4382 do{ \ 4383 while(!__rtc_write_ready()); \ 4384 REG_RTC_RCR &= ~RTC_RCR_HZIE; \ 4385 }while(0) 4386 #define __rtc_get_1Hz_flag() \ 4387 do{ \ 4388 while(!__rtc_write_ready()); \ 4389 ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \ 4390 }while(0) 4391 #define __rtc_clear_1Hz_flag() \ 4392 do{ \ 4393 while(!__rtc_write_ready()); \ 4394 REG_RTC_RCR &= ~RTC_RCR_HZ; \ 4395 }while(0) 4396 #define __rtc_get_alarm_flag() \ 4397 do{ \ 4398 while(!__rtc_write_ready()); \ 4399 ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1) \ 4400 while(0) 4401 #define __rtc_clear_alarm_flag() \ 4402 do{ \ 4403 while(!__rtc_write_ready()); \ 4404 REG_RTC_RCR &= ~RTC_RCR_AF; \ 4405 }while(0) 4406 #define __rtc_get_second() \ 4407 do{ \ 4408 while(!__rtc_write_ready());\ 4409 REG_RTC_RSR; \ 4410 }while(0) 4411 4412 #define __rtc_set_second(v) \ 4413 do{ \ 4414 while(!__rtc_write_ready()); \ 4415 REG_RTC_RSR = v; \ 4416 }while(0) 4417 4418 #define __rtc_get_alarm_second() \ 4419 do{ \ 4420 while(!__rtc_write_ready()); \ 4421 REG_RTC_RSAR; \ 4422 }while(0) 4423 4424 4425 #define __rtc_set_alarm_second(v) \ 4426 do{ \ 4427 while(!__rtc_write_ready()); \ 4428 REG_RTC_RSAR = v; \ 4429 }while(0) 4430 4431 #define __rtc_RGR_is_locked() \ 4432 do{ \ 4433 while(!__rtc_write_ready()); \ 4434 REG_RTC_RGR >> RTC_RGR_LOCK; \ 4435 }while(0) 4436 #define __rtc_lock_RGR() \ 4437 do{ \ 4438 while(!__rtc_write_ready()); \ 4439 REG_RTC_RGR |= RTC_RGR_LOCK; \ 4440 }while(0) 4441 4442 #define __rtc_unlock_RGR() \ 4443 do{ \ 4444 while(!__rtc_write_ready()); \ 4445 REG_RTC_RGR &= ~RTC_RGR_LOCK; \ 4446 }while(0) 4447 4448 #define __rtc_get_adjc_val() \ 4449 do{ \ 4450 while(!__rtc_write_ready()); \ 4451 ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \ 4452 }while(0) 4453 #define __rtc_set_adjc_val(v) \ 4454 do{ \ 4455 while(!__rtc_write_ready()); \ 4456 ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) )) \ 4457 }while(0) 4458 4459 #define __rtc_get_nc1Hz_val() \ 4460 while(!__rtc_write_ready()); \ 4461 ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT ) 4462 4463 #define __rtc_set_nc1Hz_val(v) \ 4464 do{ \ 4465 while(!__rtc_write_ready()); \ 4466 ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) )) \ 4467 }while(0) 4468 #define __rtc_power_down() \ 4469 do{ \ 4470 while(!__rtc_write_ready()); \ 4471 REG_RTC_HCR |= RTC_HCR_PD; \ 4472 }while(0) 4473 4474 #define __rtc_get_hwfcr_val() \ 4475 do{ \ 4476 while(!__rtc_write_ready()); \ 4477 REG_RTC_HWFCR & RTC_HWFCR_MASK; \ 4478 }while(0) 4479 #define __rtc_set_hwfcr_val(v) \ 4480 do{ \ 4481 while(!__rtc_write_ready()); \ 4482 REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \ 4483 }while(0) 4484 4485 #define __rtc_get_hrcr_val() \ 4486 do{ \ 4487 while(!__rtc_write_ready()); \ 4488 ( REG_RTC_HRCR & RTC_HRCR_MASK ); \ 4489 }while(0) 4490 #define __rtc_set_hrcr_val(v) \ 4491 do{ \ 4492 while(!__rtc_write_ready()); \ 4493 ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \ 4494 }while(0) 4495 4496 #define __rtc_enable_alarm_wakeup() \ 4497 do{ \ 4498 while(!__rtc_write_ready()); \ 4499 ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \ 4500 }while(0) 4501 4502 #define __rtc_disable_alarm_wakeup() \ 4503 do{ \ 4504 while(!__rtc_write_ready()); \ 4505 ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \ 4506 }while(0) 4507 4508 #define __rtc_status_hib_reset_occur() \ 4509 do{ \ 4510 while(!__rtc_write_ready()); \ 4511 ( (REG_RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 ); \ 4512 }while(0) 4513 #define __rtc_status_ppr_reset_occur() \ 4514 do{ \ 4515 while(!__rtc_write_ready()); \ 4516 ( (REG_RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 ); \ 4517 }while(0) 4518 #define __rtc_status_wakeup_pin_waken_up() \ 4519 do{ \ 4520 while(!__rtc_write_ready()); \ 4521 ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \ 4522 }while(0) 4523 #define __rtc_status_alarm_waken_up() \ 4524 do{ \ 4525 while(!__rtc_write_ready()); \ 4526 ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \ 4527 }while(0) 4528 #define __rtc_clear_hib_stat_all() \ 4529 do{ \ 4530 while(!__rtc_write_ready()); \ 4531 ( REG_RTC_HWRSR = 0 ); \ 4532 }while(0) 4533 4534 #define __rtc_get_scratch_pattern() \ 4535 while(!__rtc_write_ready()); \ 4536 (REG_RTC_HSPR) 4537 #define __rtc_set_scratch_pattern(n) \ 4538 do{ \ 4539 while(!__rtc_write_ready()); \ 4540 (REG_RTC_HSPR = n ); \ 4541 }while(0) 4542 4543 4544 #endif /* !__ASSEMBLY__ */ 4545 4546 #endif /* __JZ4740_H__ */