1 /* 2 * Include file for Ingenic Semiconductor's JZ4730 CPU. 3 * 4 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc. 5 * Copyright (C) 2009 Qi Hardware Inc. 6 * Author: Xiangfu Liu <xiangfu@sharism.cc> 7 * Copyright (C) 2015, 2017 Paul Boddie <paul@boddie.org.uk> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 22 * Boston, MA 02110-1301, USA 23 */ 24 25 #ifndef __JZ4730_H__ 26 #define __JZ4730_H__ 27 28 #include "xburst_types.h" 29 30 /* NOTE: Independent of usbboot parameters. */ 31 32 #define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ 33 #define CONFIG_SYS_EXTAL 3686400 /* EXTAL freq: 3.7 MHz */ 34 #define CONFIG_SYS_HZ (CONFIG_SYS_CPU_SPEED / (3*256)) /* incrementer freq */ 35 36 #define HARB_BASE 0xB3000000 37 #define EMC_BASE 0xB3010000 38 #define DMAC_BASE 0xB3020000 39 #define UHC_BASE 0xB3030000 40 #define UDC_BASE 0xB3040000 41 #define LCD_BASE 0xB3050000 42 #define CIM_BASE 0xB3060000 43 #define ETH_BASE 0xB3100000 44 #define NBM_BASE 0xB3F00000 45 46 #define CPM_BASE 0xB0000000 47 #define INTC_BASE 0xB0001000 48 #define OST_BASE 0xB0002000 49 #define RTC_BASE 0xB0003000 50 #define WDT_BASE 0xB0004000 51 #define GPIO_BASE 0xB0010000 52 #define AIC_BASE 0xB0020000 53 #define MSC_BASE 0xB0021000 54 #define UART0_BASE 0xB0030000 55 #define UART1_BASE 0xB0031000 56 #define UART2_BASE 0xB0032000 57 #define UART3_BASE 0xB0033000 58 #define FIR_BASE 0xB0040000 59 #define SCC_BASE 0xB0041000 60 #define SCC0_BASE 0xB0041000 61 #define I2C_BASE 0xB0042000 62 #define SSI_BASE 0xB0043000 63 #define SCC1_BASE 0xB0044000 64 #define PWM0_BASE 0xB0050000 65 #define PWM1_BASE 0xB0051000 66 #define DES_BASE 0xB0060000 67 #define UPRT_BASE 0xB0061000 68 #define KBC_BASE 0xB0062000 69 70 71 72 73 /************************************************************************* 74 * MSC 75 *************************************************************************/ 76 #define MSC_STRPCL (MSC_BASE + 0x000) 77 #define MSC_STAT (MSC_BASE + 0x004) 78 #define MSC_CLKRT (MSC_BASE + 0x008) 79 #define MSC_CMDAT (MSC_BASE + 0x00C) 80 #define MSC_RESTO (MSC_BASE + 0x010) 81 #define MSC_RDTO (MSC_BASE + 0x014) 82 #define MSC_BLKLEN (MSC_BASE + 0x018) 83 #define MSC_NOB (MSC_BASE + 0x01C) 84 #define MSC_SNOB (MSC_BASE + 0x020) 85 #define MSC_IMASK (MSC_BASE + 0x024) 86 #define MSC_IREG (MSC_BASE + 0x028) 87 #define MSC_CMD (MSC_BASE + 0x02C) 88 #define MSC_ARG (MSC_BASE + 0x030) 89 #define MSC_RES (MSC_BASE + 0x034) 90 #define MSC_RXFIFO (MSC_BASE + 0x038) 91 #define MSC_TXFIFO (MSC_BASE + 0x03C) 92 93 #define REG_MSC_STRPCL REG16(MSC_STRPCL) 94 #define REG_MSC_STAT REG32(MSC_STAT) 95 #define REG_MSC_CLKRT REG16(MSC_CLKRT) 96 #define REG_MSC_CMDAT REG32(MSC_CMDAT) 97 #define REG_MSC_RESTO REG16(MSC_RESTO) 98 #define REG_MSC_RDTO REG16(MSC_RDTO) 99 #define REG_MSC_BLKLEN REG16(MSC_BLKLEN) 100 #define REG_MSC_NOB REG16(MSC_NOB) 101 #define REG_MSC_SNOB REG16(MSC_SNOB) 102 #define REG_MSC_IMASK REG16(MSC_IMASK) 103 #define REG_MSC_IREG REG16(MSC_IREG) 104 #define REG_MSC_CMD REG8(MSC_CMD) 105 #define REG_MSC_ARG REG32(MSC_ARG) 106 #define REG_MSC_RES REG16(MSC_RES) 107 #define REG_MSC_RXFIFO REG32(MSC_RXFIFO) 108 #define REG_MSC_TXFIFO REG32(MSC_TXFIFO) 109 110 /* MSC Clock and Control Register (MSC_STRPCL) */ 111 112 #define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) 113 #define MSC_STRPCL_EXIT_TRANSFER (1 << 6) 114 #define MSC_STRPCL_START_READWAIT (1 << 5) 115 #define MSC_STRPCL_STOP_READWAIT (1 << 4) 116 #define MSC_STRPCL_RESET (1 << 3) 117 #define MSC_STRPCL_START_OP (1 << 2) 118 #define MSC_STRPCL_CLOCK_CONTROL_BIT 0 119 #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) 120 #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */ 121 #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */ 122 123 /* MSC Status Register (MSC_STAT) */ 124 125 #define MSC_STAT_IS_RESETTING (1 << 15) 126 #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) 127 #define MSC_STAT_PRG_DONE (1 << 13) 128 #define MSC_STAT_DATA_TRAN_DONE (1 << 12) 129 #define MSC_STAT_END_CMD_RES (1 << 11) 130 #define MSC_STAT_DATA_FIFO_AFULL (1 << 10) 131 #define MSC_STAT_IS_READWAIT (1 << 9) 132 #define MSC_STAT_CLK_EN (1 << 8) 133 #define MSC_STAT_DATA_FIFO_FULL (1 << 7) 134 #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) 135 #define MSC_STAT_CRC_RES_ERR (1 << 5) 136 #define MSC_STAT_CRC_READ_ERROR (1 << 4) 137 #define MSC_STAT_CRC_WRITE_ERROR_BIT 2 138 #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) 139 #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */ 140 #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */ 141 #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */ 142 #define MSC_STAT_TIME_OUT_RES (1 << 1) 143 #define MSC_STAT_TIME_OUT_READ (1 << 0) 144 145 /* MSC Bus Clock Control Register (MSC_CLKRT) */ 146 147 #define MSC_CLKRT_CLK_RATE_BIT 0 148 #define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) 149 #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */ 150 #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */ 151 #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */ 152 #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */ 153 #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */ 154 #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */ 155 #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */ 156 #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */ 157 158 /* MSC Command Sequence Control Register (MSC_CMDAT) */ 159 160 #define MSC_CMDAT_IO_ABORT (1 << 11) 161 #define MSC_CMDAT_BUS_WIDTH_BIT 9 162 #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) 163 #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */ 164 #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */ 165 #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) 166 #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) 167 #define MSC_CMDAT_DMA_EN (1 << 8) 168 #define MSC_CMDAT_INIT (1 << 7) 169 #define MSC_CMDAT_BUSY (1 << 6) 170 #define MSC_CMDAT_STREAM_BLOCK (1 << 5) 171 #define MSC_CMDAT_WRITE (1 << 4) 172 #define MSC_CMDAT_READ (0 << 4) 173 #define MSC_CMDAT_DATA_EN (1 << 3) 174 #define MSC_CMDAT_RESPONSE_BIT 0 175 #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) 176 #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */ 177 #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */ 178 #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */ 179 #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */ 180 #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */ 181 #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */ 182 #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */ 183 184 #define CMDAT_DMA_EN (1 << 8) 185 #define CMDAT_INIT (1 << 7) 186 #define CMDAT_BUSY (1 << 6) 187 #define CMDAT_STREAM (1 << 5) 188 #define CMDAT_WRITE (1 << 4) 189 #define CMDAT_DATA_EN (1 << 3) 190 191 /* MSC Interrupts Mask Register (MSC_IMASK) */ 192 193 #define MSC_IMASK_SDIO (1 << 7) 194 #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) 195 #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) 196 #define MSC_IMASK_END_CMD_RES (1 << 2) 197 #define MSC_IMASK_PRG_DONE (1 << 1) 198 #define MSC_IMASK_DATA_TRAN_DONE (1 << 0) 199 200 201 /* MSC Interrupts Status Register (MSC_IREG) */ 202 203 #define MSC_IREG_SDIO (1 << 7) 204 #define MSC_IREG_TXFIFO_WR_REQ (1 << 6) 205 #define MSC_IREG_RXFIFO_RD_REQ (1 << 5) 206 #define MSC_IREG_END_CMD_RES (1 << 2) 207 #define MSC_IREG_PRG_DONE (1 << 1) 208 #define MSC_IREG_DATA_TRAN_DONE (1 << 0) 209 210 /************************************************************************* 211 * RTC 212 *************************************************************************/ 213 #define RTC_RCR (RTC_BASE + 0x00) 214 #define RTC_RSR (RTC_BASE + 0x04) 215 #define RTC_RSAR (RTC_BASE + 0x08) 216 #define RTC_RGR (RTC_BASE + 0x0c) 217 218 #define REG_RTC_RCR REG32(RTC_RCR) 219 #define REG_RTC_RSR REG32(RTC_RSR) 220 #define REG_RTC_RSAR REG32(RTC_RSAR) 221 #define REG_RTC_RGR REG32(RTC_RGR) 222 223 #define RTC_RCR_HZ (1 << 6) 224 #define RTC_RCR_HZIE (1 << 5) 225 #define RTC_RCR_AF (1 << 4) 226 #define RTC_RCR_AIE (1 << 3) 227 #define RTC_RCR_AE (1 << 2) 228 #define RTC_RCR_START (1 << 0) 229 230 #define RTC_RGR_LOCK (1 << 31) 231 #define RTC_RGR_ADJ_BIT 16 232 #define RTC_RGR_ADJ_MASK (0x3ff << RTC_RGR_ADJ_BIT) 233 #define RTC_RGR_DIV_BIT 0 234 #define RTC_REG_DIV_MASK (0xff << RTC_RGR_DIV_BIT) 235 236 237 238 239 /************************************************************************* 240 * FIR 241 *************************************************************************/ 242 #define FIR_TDR (FIR_BASE + 0x000) 243 #define FIR_RDR (FIR_BASE + 0x004) 244 #define FIR_TFLR (FIR_BASE + 0x008) 245 #define FIR_AR (FIR_BASE + 0x00C) 246 #define FIR_CR1 (FIR_BASE + 0x010) 247 #define FIR_CR2 (FIR_BASE + 0x014) 248 #define FIR_SR (FIR_BASE + 0x018) 249 250 #define REG_FIR_TDR REG8(FIR_TDR) 251 #define REG_FIR_RDR REG8(FIR_RDR) 252 #define REG_FIR_TFLR REG16(FIR_TFLR) 253 #define REG_FIR_AR REG8(FIR_AR) 254 #define REG_FIR_CR1 REG8(FIR_CR1) 255 #define REG_FIR_CR2 REG16(FIR_CR2) 256 #define REG_FIR_SR REG16(FIR_SR) 257 258 /* FIR Control Register 1 (FIR_CR1) */ 259 260 #define FIR_CR1_FIRUE (1 << 7) 261 #define FIR_CR1_ACE (1 << 6) 262 #define FIR_CR1_EOUS (1 << 5) 263 #define FIR_CR1_TIIE (1 << 4) 264 #define FIR_CR1_TFIE (1 << 3) 265 #define FIR_CR1_RFIE (1 << 2) 266 #define FIR_CR1_TXE (1 << 1) 267 #define FIR_CR1_RXE (1 << 0) 268 269 /* FIR Control Register 2 (FIR_CR2) */ 270 271 #define FIR_CR2_SIPE (1 << 10) 272 #define FIR_CR2_BCRC (1 << 9) 273 #define FIR_CR2_TFLRS (1 << 8) 274 #define FIR_CR2_ISS (1 << 7) 275 #define FIR_CR2_LMS (1 << 6) 276 #define FIR_CR2_TPPS (1 << 5) 277 #define FIR_CR2_RPPS (1 << 4) 278 #define FIR_CR2_TTRG_BIT 2 279 #define FIR_CR2_TTRG_MASK (0x3 << FIR_CR2_TTRG_BIT) 280 #define FIR_CR2_TTRG_16 (0 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 16 */ 281 #define FIR_CR2_TTRG_32 (1 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 32 */ 282 #define FIR_CR2_TTRG_64 (2 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 64 */ 283 #define FIR_CR2_TTRG_128 (3 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 128 */ 284 #define FIR_CR2_RTRG_BIT 0 285 #define FIR_CR2_RTRG_MASK (0x3 << FIR_CR2_RTRG_BIT) 286 #define FIR_CR2_RTRG_16 (0 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 16 */ 287 #define FIR_CR2_RTRG_32 (1 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 32 */ 288 #define FIR_CR2_RTRG_64 (2 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 64 */ 289 #define FIR_CR2_RTRG_128 (3 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 128 */ 290 291 /* FIR Status Register (FIR_SR) */ 292 293 #define FIR_SR_RFW (1 << 12) 294 #define FIR_SR_RFA (1 << 11) 295 #define FIR_SR_TFRTL (1 << 10) 296 #define FIR_SR_RFRTL (1 << 9) 297 #define FIR_SR_URUN (1 << 8) 298 #define FIR_SR_RFTE (1 << 7) 299 #define FIR_SR_ORUN (1 << 6) 300 #define FIR_SR_CRCE (1 << 5) 301 #define FIR_SR_FEND (1 << 4) 302 #define FIR_SR_TFF (1 << 3) 303 #define FIR_SR_RFE (1 << 2) 304 #define FIR_SR_TIDLE (1 << 1) 305 #define FIR_SR_RB (1 << 0) 306 307 308 309 310 /************************************************************************* 311 * SCC 312 *************************************************************************/ 313 #define SCC_DR(base) ((base) + 0x000) 314 #define SCC_FDR(base) ((base) + 0x004) 315 #define SCC_CR(base) ((base) + 0x008) 316 #define SCC_SR(base) ((base) + 0x00C) 317 #define SCC_TFR(base) ((base) + 0x010) 318 #define SCC_EGTR(base) ((base) + 0x014) 319 #define SCC_ECR(base) ((base) + 0x018) 320 #define SCC_RTOR(base) ((base) + 0x01C) 321 322 #define REG_SCC_DR(base) REG8(SCC_DR(base)) 323 #define REG_SCC_FDR(base) REG8(SCC_FDR(base)) 324 #define REG_SCC_CR(base) REG32(SCC_CR(base)) 325 #define REG_SCC_SR(base) REG16(SCC_SR(base)) 326 #define REG_SCC_TFR(base) REG16(SCC_TFR(base)) 327 #define REG_SCC_EGTR(base) REG8(SCC_EGTR(base)) 328 #define REG_SCC_ECR(base) REG32(SCC_ECR(base)) 329 #define REG_SCC_RTOR(base) REG8(SCC_RTOR(base)) 330 331 /* SCC FIFO Data Count Register (SCC_FDR) */ 332 333 #define SCC_FDR_EMPTY 0x00 334 #define SCC_FDR_FULL 0x10 335 336 /* SCC Control Register (SCC_CR) */ 337 338 #define SCC_CR_SCCE (1 << 31) 339 #define SCC_CR_TRS (1 << 30) 340 #define SCC_CR_T2R (1 << 29) 341 #define SCC_CR_FDIV_BIT 24 342 #define SCC_CR_FDIV_MASK (0x3 << SCC_CR_FDIV_BIT) 343 #define SCC_CR_FDIV_1 (0 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is the same as device clock */ 344 #define SCC_CR_FDIV_2 (1 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is half of device clock */ 345 #define SCC_CR_FLUSH (1 << 23) 346 #define SCC_CR_TRIG_BIT 16 347 #define SCC_CR_TRIG_MASK (0x3 << SCC_CR_TRIG_BIT) 348 #define SCC_CR_TRIG_1 (0 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 1 */ 349 #define SCC_CR_TRIG_4 (1 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 4 */ 350 #define SCC_CR_TRIG_8 (2 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 8 */ 351 #define SCC_CR_TRIG_14 (3 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 14 */ 352 #define SCC_CR_TP (1 << 15) 353 #define SCC_CR_CONV (1 << 14) 354 #define SCC_CR_TXIE (1 << 13) 355 #define SCC_CR_RXIE (1 << 12) 356 #define SCC_CR_TENDIE (1 << 11) 357 #define SCC_CR_RTOIE (1 << 10) 358 #define SCC_CR_ECIE (1 << 9) 359 #define SCC_CR_EPIE (1 << 8) 360 #define SCC_CR_RETIE (1 << 7) 361 #define SCC_CR_EOIE (1 << 6) 362 #define SCC_CR_TSEND (1 << 3) 363 #define SCC_CR_PX_BIT 1 364 #define SCC_CR_PX_MASK (0x3 << SCC_CR_PX_BIT) 365 #define SCC_CR_PX_NOT_SUPPORT (0 << SCC_CR_PX_BIT) /* SCC does not support clock stop */ 366 #define SCC_CR_PX_STOP_LOW (1 << SCC_CR_PX_BIT) /* SCC_CLK stops at state low */ 367 #define SCC_CR_PX_STOP_HIGH (2 << SCC_CR_PX_BIT) /* SCC_CLK stops at state high */ 368 #define SCC_CR_CLKSTP (1 << 0) 369 370 /* SCC Status Register (SCC_SR) */ 371 372 #define SCC_SR_TRANS (1 << 15) 373 #define SCC_SR_ORER (1 << 12) 374 #define SCC_SR_RTO (1 << 11) 375 #define SCC_SR_PER (1 << 10) 376 #define SCC_SR_TFTG (1 << 9) 377 #define SCC_SR_RFTG (1 << 8) 378 #define SCC_SR_TEND (1 << 7) 379 #define SCC_SR_RETR_3 (1 << 4) 380 #define SCC_SR_ECNTO (1 << 0) 381 382 383 384 385 /************************************************************************* 386 * ETH 387 *************************************************************************/ 388 #define ETH_BMR (ETH_BASE + 0x1000) 389 #define ETH_TPDR (ETH_BASE + 0x1004) 390 #define ETH_RPDR (ETH_BASE + 0x1008) 391 #define ETH_RAR (ETH_BASE + 0x100C) 392 #define ETH_TAR (ETH_BASE + 0x1010) 393 #define ETH_SR (ETH_BASE + 0x1014) 394 #define ETH_CR (ETH_BASE + 0x1018) 395 #define ETH_IER (ETH_BASE + 0x101C) 396 #define ETH_MFCR (ETH_BASE + 0x1020) 397 #define ETH_CTAR (ETH_BASE + 0x1050) 398 #define ETH_CRAR (ETH_BASE + 0x1054) 399 #define ETH_MCR (ETH_BASE + 0x0000) 400 #define ETH_MAHR (ETH_BASE + 0x0004) 401 #define ETH_MALR (ETH_BASE + 0x0008) 402 #define ETH_HTHR (ETH_BASE + 0x000C) 403 #define ETH_HTLR (ETH_BASE + 0x0010) 404 #define ETH_MIAR (ETH_BASE + 0x0014) 405 #define ETH_MIDR (ETH_BASE + 0x0018) 406 #define ETH_FCR (ETH_BASE + 0x001C) 407 #define ETH_VTR1 (ETH_BASE + 0x0020) 408 #define ETH_VTR2 (ETH_BASE + 0x0024) 409 #define ETH_WKFR (ETH_BASE + 0x0028) 410 #define ETH_PMTR (ETH_BASE + 0x002C) 411 412 #define REG_ETH_BMR REG32(ETH_BMR) 413 #define REG_ETH_TPDR REG32(ETH_TPDR) 414 #define REG_ETH_RPDR REG32(ETH_RPDR) 415 #define REG_ETH_RAR REG32(ETH_RAR) 416 #define REG_ETH_TAR REG32(ETH_TAR) 417 #define REG_ETH_SR REG32(ETH_SR) 418 #define REG_ETH_CR REG32(ETH_CR) 419 #define REG_ETH_IER REG32(ETH_IER) 420 #define REG_ETH_MFCR REG32(ETH_MFCR) 421 #define REG_ETH_CTAR REG32(ETH_CTAR) 422 #define REG_ETH_CRAR REG32(ETH_CRAR) 423 #define REG_ETH_MCR REG32(ETH_MCR) 424 #define REG_ETH_MAHR REG32(ETH_MAHR) 425 #define REG_ETH_MALR REG32(ETH_MALR) 426 #define REG_ETH_HTHR REG32(ETH_HTHR) 427 #define REG_ETH_HTLR REG32(ETH_HTLR) 428 #define REG_ETH_MIAR REG32(ETH_MIAR) 429 #define REG_ETH_MIDR REG32(ETH_MIDR) 430 #define REG_ETH_FCR REG32(ETH_FCR) 431 #define REG_ETH_VTR1 REG32(ETH_VTR1) 432 #define REG_ETH_VTR2 REG32(ETH_VTR2) 433 #define REG_ETH_WKFR REG32(ETH_WKFR) 434 #define REG_ETH_PMTR REG32(ETH_PMTR) 435 436 /* Bus Mode Register (ETH_BMR) */ 437 438 #define ETH_BMR_DBO (1 << 20) 439 #define ETH_BMR_PBL_BIT 8 440 #define ETH_BMR_PBL_MASK (0x3f << ETH_BMR_PBL_BIT) 441 #define ETH_BMR_PBL_1 (0x1 << ETH_BMR_PBL_BIT) 442 #define ETH_BMR_PBL_4 (0x4 << ETH_BMR_PBL_BIT) 443 #define ETH_BMR_BLE (1 << 7) 444 #define ETH_BMR_DSL_BIT 2 445 #define ETH_BMR_DSL_MASK (0x1f << ETH_BMR_DSL_BIT) 446 #define ETH_BMR_DSL_0 (0x0 << ETH_BMR_DSL_BIT) 447 #define ETH_BMR_DSL_1 (0x1 << ETH_BMR_DSL_BIT) 448 #define ETH_BMR_DSL_2 (0x2 << ETH_BMR_DSL_BIT) 449 #define ETH_BMR_DSL_4 (0x4 << ETH_BMR_DSL_BIT) 450 #define ETH_BMR_DSL_8 (0x8 << ETH_BMR_DSL_BIT) 451 #define ETH_BMR_SWR (1 << 0) 452 453 /* DMA Status Register (ETH_SR) */ 454 455 #define ETH_SR_EB_BIT 23 456 #define ETH_SR_EB_MASK (0x7 << ETH_SR_EB_BIT) 457 #define ETH_SR_EB_TX_ABORT (0x1 << ETH_SR_EB_BIT) 458 #define ETH_SR_EB_RX_ABORT (0x2 << ETH_SR_EB_BIT) 459 #define ETH_SR_TS_BIT 20 460 #define ETH_SR_TS_MASK (0x7 << ETH_SR_TS_BIT) 461 #define ETH_SR_TS_STOP (0x0 << ETH_SR_TS_BIT) 462 #define ETH_SR_TS_FTD (0x1 << ETH_SR_TS_BIT) 463 #define ETH_SR_TS_WEOT (0x2 << ETH_SR_TS_BIT) 464 #define ETH_SR_TS_QDAT (0x3 << ETH_SR_TS_BIT) 465 #define ETH_SR_TS_SUSPEND (0x6 << ETH_SR_TS_BIT) 466 #define ETH_SR_TS_CTD (0x7 << ETH_SR_TS_BIT) 467 #define ETH_SR_RS_BIT 17 468 #define ETH_SR_RS_MASK (0x7 << ETH_SR_RS_BIT) 469 #define ETH_SR_RS_STOP (0x0 << ETH_SR_RS_BIT) 470 #define ETH_SR_RS_FRD (0x1 << ETH_SR_RS_BIT) 471 #define ETH_SR_RS_CEOR (0x2 << ETH_SR_RS_BIT) 472 #define ETH_SR_RS_WRP (0x3 << ETH_SR_RS_BIT) 473 #define ETH_SR_RS_SUSPEND (0x4 << ETH_SR_RS_BIT) 474 #define ETH_SR_RS_CRD (0x5 << ETH_SR_RS_BIT) 475 #define ETH_SR_RS_FCF (0x6 << ETH_SR_RS_BIT) 476 #define ETH_SR_RS_QRF (0x7 << ETH_SR_RS_BIT) 477 #define ETH_SR_NIS (1 << 16) 478 #define ETH_SR_AIS (1 << 15) 479 #define ETH_SR_ERI (1 << 14) 480 #define ETH_SR_FBE (1 << 13) 481 #define ETH_SR_ETI (1 << 10) 482 #define ETH_SR_RWT (1 << 9) 483 #define ETH_SR_RPS (1 << 8) 484 #define ETH_SR_RU (1 << 7) 485 #define ETH_SR_RI (1 << 6) 486 #define ETH_SR_UNF (1 << 5) 487 #define ETH_SR_TJT (1 << 3) 488 #define ETH_SR_TU (1 << 2) 489 #define ETH_SR_TPS (1 << 1) 490 #define ETH_SR_TI (1 << 0) 491 492 /* Control (Operation Mode) Register (ETH_CR) */ 493 494 #define ETH_CR_TTM (1 << 22) 495 #define ETH_CR_SF (1 << 21) 496 #define ETH_CR_TR_BIT 14 497 #define ETH_CR_TR_MASK (0x3 << ETH_CR_TR_BIT) 498 #define ETH_CR_ST (1 << 13) 499 #define ETH_CR_OSF (1 << 2) 500 #define ETH_CR_SR (1 << 1) 501 502 /* Interrupt Enable Register (ETH_IER) */ 503 504 #define ETH_IER_NI (1 << 16) 505 #define ETH_IER_AI (1 << 15) 506 #define ETH_IER_ERE (1 << 14) 507 #define ETH_IER_FBE (1 << 13) 508 #define ETH_IER_ET (1 << 10) 509 #define ETH_IER_RWE (1 << 9) 510 #define ETH_IER_RS (1 << 8) 511 #define ETH_IER_RU (1 << 7) 512 #define ETH_IER_RI (1 << 6) 513 #define ETH_IER_UN (1 << 5) 514 #define ETH_IER_TJ (1 << 3) 515 #define ETH_IER_TU (1 << 2) 516 #define ETH_IER_TS (1 << 1) 517 #define ETH_IER_TI (1 << 0) 518 519 /* Missed Frame and Buffer Overflow Counter Register (ETH_MFCR) */ 520 521 #define ETH_MFCR_OVERFLOW_BIT 17 522 #define ETH_MFCR_OVERFLOW_MASK (0x7ff << ETH_MFCR_OVERFLOW_BIT) 523 #define ETH_MFCR_MFC_BIT 0 524 #define ETH_MFCR_MFC_MASK (0xffff << ETH_MFCR_MFC_BIT) 525 526 /* MAC Control Register (ETH_MCR) */ 527 528 #define ETH_MCR_RA (1 << 31) 529 #define ETH_MCR_HBD (1 << 28) 530 #define ETH_MCR_PS (1 << 27) 531 #define ETH_MCR_DRO (1 << 23) 532 #define ETH_MCR_OM_BIT 21 533 #define ETH_MCR_OM_MASK (0x3 << ETH_MCR_OM_BIT) 534 #define ETH_MCR_OM_NORMAL (0x0 << ETH_MCR_OM_BIT) 535 #define ETH_MCR_OM_INTERNAL (0x1 << ETH_MCR_OM_BIT) 536 #define ETH_MCR_OM_EXTERNAL (0x2 << ETH_MCR_OM_BIT) 537 #define ETH_MCR_F (1 << 20) 538 #define ETH_MCR_PM (1 << 19) 539 #define ETH_MCR_PR (1 << 18) 540 #define ETH_MCR_IF (1 << 17) 541 #define ETH_MCR_PB (1 << 16) 542 #define ETH_MCR_HO (1 << 15) 543 #define ETH_MCR_HP (1 << 13) 544 #define ETH_MCR_LCC (1 << 12) 545 #define ETH_MCR_DBF (1 << 11) 546 #define ETH_MCR_DTRY (1 << 10) 547 #define ETH_MCR_ASTP (1 << 8) 548 #define ETH_MCR_BOLMT_BIT 6 549 #define ETH_MCR_BOLMT_MASK (0x3 << ETH_MCR_BOLMT_BIT) 550 #define ETH_MCR_BOLMT_10 (0 << ETH_MCR_BOLMT_BIT) 551 #define ETH_MCR_BOLMT_8 (1 << ETH_MCR_BOLMT_BIT) 552 #define ETH_MCR_BOLMT_4 (2 << ETH_MCR_BOLMT_BIT) 553 #define ETH_MCR_BOLMT_1 (3 << ETH_MCR_BOLMT_BIT) 554 #define ETH_MCR_DC (1 << 5) 555 #define ETH_MCR_TE (1 << 3) 556 #define ETH_MCR_RE (1 << 2) 557 558 /* MII Address Register (ETH_MIAR) */ 559 560 #define ETH_MIAR_PHY_ADDR_BIT 11 561 #define ETH_MIAR_PHY_ADDR_MASK (0x1f << ETH_MIAR_PHY_ADDR_BIT) 562 #define ETH_MIAR_MII_REG_BIT 6 563 #define ETH_MIAR_MII_REG_MASK (0x1f << ETH_MIAR_MII_REG_BIT) 564 #define ETH_MIAR_MII_WRITE (1 << 1) 565 #define ETH_MIAR_MII_BUSY (1 << 0) 566 567 /* Flow Control Register (ETH_FCR) */ 568 569 #define ETH_FCR_PAUSE_TIME_BIT 16 570 #define ETH_FCR_PAUSE_TIME_MASK (0xffff << ETH_FCR_PAUSE_TIME_BIT) 571 #define ETH_FCR_PCF (1 << 2) 572 #define ETH_FCR_FCE (1 << 1) 573 #define ETH_FCR_BUSY (1 << 0) 574 575 /* PMT Control and Status Register (ETH_PMTR) */ 576 577 #define ETH_PMTR_GU (1 << 9) 578 #define ETH_PMTR_RF (1 << 6) 579 #define ETH_PMTR_MF (1 << 5) 580 #define ETH_PMTR_RWK (1 << 2) 581 #define ETH_PMTR_MPK (1 << 1) 582 583 /* Receive Descriptor 0 (ETH_RD0) Bits */ 584 585 #define ETH_RD0_OWN (1 << 31) 586 #define ETH_RD0_FF (1 << 30) 587 #define ETH_RD0_FL_BIT 16 588 #define ETH_RD0_FL_MASK (0x3fff << ETH_RD0_FL_BIT) 589 #define ETH_RD0_ES (1 << 15) 590 #define ETH_RD0_DE (1 << 14) 591 #define ETH_RD0_LE (1 << 12) 592 #define ETH_RD0_RF (1 << 11) 593 #define ETH_RD0_MF (1 << 10) 594 #define ETH_RD0_FD (1 << 9) 595 #define ETH_RD0_LD (1 << 8) 596 #define ETH_RD0_TL (1 << 7) 597 #define ETH_RD0_CS (1 << 6) 598 #define ETH_RD0_FT (1 << 5) 599 #define ETH_RD0_WT (1 << 4) 600 #define ETH_RD0_ME (1 << 3) 601 #define ETH_RD0_DB (1 << 2) 602 #define ETH_RD0_CE (1 << 1) 603 604 /* Receive Descriptor 1 (ETH_RD1) Bits */ 605 606 #define ETH_RD1_RER (1 << 25) 607 #define ETH_RD1_RCH (1 << 24) 608 #define ETH_RD1_RBS2_BIT 11 609 #define ETH_RD1_RBS2_MASK (0x7ff << ETH_RD1_RBS2_BIT) 610 #define ETH_RD1_RBS1_BIT 0 611 #define ETH_RD1_RBS1_MASK (0x7ff << ETH_RD1_RBS1_BIT) 612 613 /* Transmit Descriptor 0 (ETH_TD0) Bits */ 614 615 #define ETH_TD0_OWN (1 << 31) 616 #define ETH_TD0_FA (1 << 15) 617 #define ETH_TD0_LOC (1 << 11) 618 #define ETH_TD0_NC (1 << 10) 619 #define ETH_TD0_LC (1 << 9) 620 #define ETH_TD0_EC (1 << 8) 621 #define ETH_TD0_HBF (1 << 7) 622 #define ETH_TD0_CC_BIT 3 623 #define ETH_TD0_CC_MASK (0xf << ETH_TD0_CC_BIT) 624 #define ETH_TD0_ED (1 << 2) 625 #define ETH_TD0_UF (1 << 1) 626 #define ETH_TD0_DF (1 << 0) 627 628 /* Transmit Descriptor 1 (ETH_TD1) Bits */ 629 630 #define ETH_TD1_IC (1 << 31) 631 #define ETH_TD1_LS (1 << 30) 632 #define ETH_TD1_FS (1 << 29) 633 #define ETH_TD1_AC (1 << 26) 634 #define ETH_TD1_TER (1 << 25) 635 #define ETH_TD1_TCH (1 << 24) 636 #define ETH_TD1_DPD (1 << 23) 637 #define ETH_TD1_TBS2_BIT 11 638 #define ETH_TD1_TBS2_MASK (0x7ff << ETH_TD1_TBS2_BIT) 639 #define ETH_TD1_TBS1_BIT 0 640 #define ETH_TD1_TBS1_MASK (0x7ff << ETH_TD1_TBS1_BIT) 641 642 643 644 645 /************************************************************************* 646 * WDT 647 *************************************************************************/ 648 #define WDT_WTCSR (WDT_BASE + 0x00) 649 #define WDT_WTCNT (WDT_BASE + 0x04) 650 651 #define REG_WDT_WTCSR REG8(WDT_WTCSR) 652 #define REG_WDT_WTCNT REG32(WDT_WTCNT) 653 654 #define WDT_WTCSR_START (1 << 4) 655 656 657 658 659 /************************************************************************* 660 * OST 661 *************************************************************************/ 662 #define OST_TER (OST_BASE + 0x00) 663 #define OST_TRDR(n) (OST_BASE + 0x10 + ((n) * 0x20)) 664 #define OST_TCNT(n) (OST_BASE + 0x14 + ((n) * 0x20)) 665 #define OST_TCSR(n) (OST_BASE + 0x18 + ((n) * 0x20)) 666 #define OST_TCRB(n) (OST_BASE + 0x1c + ((n) * 0x20)) 667 668 #define REG_OST_TER REG8(OST_TER) 669 #define REG_OST_TRDR(n) REG32(OST_TRDR((n))) 670 #define REG_OST_TCNT(n) REG32(OST_TCNT((n))) 671 #define REG_OST_TCSR(n) REG16(OST_TCSR((n))) 672 #define REG_OST_TCRB(n) REG32(OST_TCRB((n))) 673 674 #define OST_TCSR_BUSY (1 << 7) 675 #define OST_TCSR_UF (1 << 6) 676 #define OST_TCSR_UIE (1 << 5) 677 #define OST_TCSR_CKS_BIT 0 678 #define OST_TCSR_CKS_MASK (0x07 << OST_TCSR_CKS_BIT) 679 #define OST_TCSR_CKS_PCLK_4 (0 << OST_TCSR_CKS_BIT) 680 #define OST_TCSR_CKS_PCLK_16 (1 << OST_TCSR_CKS_BIT) 681 #define OST_TCSR_CKS_PCLK_64 (2 << OST_TCSR_CKS_BIT) 682 #define OST_TCSR_CKS_PCLK_256 (3 << OST_TCSR_CKS_BIT) 683 #define OST_TCSR_CKS_RTCCLK (4 << OST_TCSR_CKS_BIT) 684 #define OST_TCSR_CKS_EXTAL (5 << OST_TCSR_CKS_BIT) 685 686 #define OST_TCSR0 OST_TCSR(0) 687 #define OST_TCSR1 OST_TCSR(1) 688 #define OST_TCSR2 OST_TCSR(2) 689 #define OST_TRDR0 OST_TRDR(0) 690 #define OST_TRDR1 OST_TRDR(1) 691 #define OST_TRDR2 OST_TRDR(2) 692 #define OST_TCNT0 OST_TCNT(0) 693 #define OST_TCNT1 OST_TCNT(1) 694 #define OST_TCNT2 OST_TCNT(2) 695 #define OST_TCRB0 OST_TCRB(0) 696 #define OST_TCRB1 OST_TCRB(1) 697 #define OST_TCRB2 OST_TCRB(2) 698 699 /************************************************************************* 700 * UART 701 *************************************************************************/ 702 703 #define IRDA_BASE UART0_BASE 704 #define UART_BASE UART0_BASE 705 #define UART_OFF 0x1000 706 707 /* register offset */ 708 #define OFF_RDR (0x00) /* R 8b H'xx */ 709 #define OFF_TDR (0x00) /* W 8b H'xx */ 710 #define OFF_DLLR (0x00) /* RW 8b H'00 */ 711 #define OFF_DLHR (0x04) /* RW 8b H'00 */ 712 #define OFF_IER (0x04) /* RW 8b H'00 */ 713 #define OFF_ISR (0x08) /* R 8b H'01 */ 714 #define OFF_FCR (0x08) /* W 8b H'00 */ 715 #define OFF_LCR (0x0C) /* RW 8b H'00 */ 716 #define OFF_MCR (0x10) /* RW 8b H'00 */ 717 #define OFF_LSR (0x14) /* R 8b H'00 */ 718 #define OFF_MSR (0x18) /* R 8b H'00 */ 719 #define OFF_SPR (0x1C) /* RW 8b H'00 */ 720 #define OFF_MCR (0x10) /* RW 8b H'00 */ 721 #define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ 722 723 /* register address */ 724 #define UART0_RDR (UART0_BASE + OFF_RDR) 725 #define UART0_TDR (UART0_BASE + OFF_TDR) 726 #define UART0_DLLR (UART0_BASE + OFF_DLLR) 727 #define UART0_DLHR (UART0_BASE + OFF_DLHR) 728 #define UART0_IER (UART0_BASE + OFF_IER) 729 #define UART0_ISR (UART0_BASE + OFF_ISR) 730 #define UART0_FCR (UART0_BASE + OFF_FCR) 731 #define UART0_LCR (UART0_BASE + OFF_LCR) 732 #define UART0_MCR (UART0_BASE + OFF_MCR) 733 #define UART0_LSR (UART0_BASE + OFF_LSR) 734 #define UART0_MSR (UART0_BASE + OFF_MSR) 735 #define UART0_SPR (UART0_BASE + OFF_SPR) 736 #define UART0_SIRCR (UART0_BASE + OFF_SIRCR) 737 738 #define UART1_RDR (UART1_BASE + OFF_RDR) 739 #define UART1_TDR (UART1_BASE + OFF_TDR) 740 #define UART1_DLLR (UART1_BASE + OFF_DLLR) 741 #define UART1_DLHR (UART1_BASE + OFF_DLHR) 742 #define UART1_IER (UART1_BASE + OFF_IER) 743 #define UART1_ISR (UART1_BASE + OFF_ISR) 744 #define UART1_FCR (UART1_BASE + OFF_FCR) 745 #define UART1_LCR (UART1_BASE + OFF_LCR) 746 #define UART1_MCR (UART1_BASE + OFF_MCR) 747 #define UART1_LSR (UART1_BASE + OFF_LSR) 748 #define UART1_MSR (UART1_BASE + OFF_MSR) 749 #define UART1_SPR (UART1_BASE + OFF_SPR) 750 #define UART1_SIRCR (UART1_BASE + OFF_SIRCR) 751 752 #define UART2_RDR (UART2_BASE + OFF_RDR) 753 #define UART2_TDR (UART2_BASE + OFF_TDR) 754 #define UART2_DLLR (UART2_BASE + OFF_DLLR) 755 #define UART2_DLHR (UART2_BASE + OFF_DLHR) 756 #define UART2_IER (UART2_BASE + OFF_IER) 757 #define UART2_ISR (UART2_BASE + OFF_ISR) 758 #define UART2_FCR (UART2_BASE + OFF_FCR) 759 #define UART2_LCR (UART2_BASE + OFF_LCR) 760 #define UART2_MCR (UART2_BASE + OFF_MCR) 761 #define UART2_LSR (UART2_BASE + OFF_LSR) 762 #define UART2_MSR (UART2_BASE + OFF_MSR) 763 #define UART2_SPR (UART2_BASE + OFF_SPR) 764 #define UART2_SIRCR (UART2_BASE + OFF_SIRCR) 765 766 #define UART3_RDR (UART3_BASE + OFF_RDR) 767 #define UART3_TDR (UART3_BASE + OFF_TDR) 768 #define UART3_DLLR (UART3_BASE + OFF_DLLR) 769 #define UART3_DLHR (UART3_BASE + OFF_DLHR) 770 #define UART3_IER (UART3_BASE + OFF_IER) 771 #define UART3_ISR (UART3_BASE + OFF_ISR) 772 #define UART3_FCR (UART3_BASE + OFF_FCR) 773 #define UART3_LCR (UART3_BASE + OFF_LCR) 774 #define UART3_MCR (UART3_BASE + OFF_MCR) 775 #define UART3_LSR (UART3_BASE + OFF_LSR) 776 #define UART3_MSR (UART3_BASE + OFF_MSR) 777 #define UART3_SPR (UART3_BASE + OFF_SPR) 778 #define UART3_SIRCR (UART3_BASE + OFF_SIRCR) 779 780 /* 781 * Define macros for UART_IER 782 * UART Interrupt Enable Register 783 */ 784 #define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */ 785 #define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */ 786 #define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ 787 #define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ 788 #define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ 789 790 /* 791 * Define macros for UART_ISR 792 * UART Interrupt Status Register 793 */ 794 #define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ 795 #define UART_ISR_IID (7 << 1) /* Source of Interrupt */ 796 #define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ 797 #define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ 798 #define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ 799 #define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ 800 #define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */ 801 #define UART_ISR_FFMS_NO_FIFO (0 << 6) 802 #define UART_ISR_FFMS_FIFO_MODE (3 << 6) 803 804 /* 805 * Define macros for UART_FCR 806 * UART FIFO Control Register 807 */ 808 #define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ 809 #define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ 810 #define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ 811 #define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ 812 #define UART_FCR_UUE (1 << 4) /* 0: disable UART */ 813 #define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ 814 #define UART_FCR_RTRG_1 (0 << 6) 815 #define UART_FCR_RTRG_4 (1 << 6) 816 #define UART_FCR_RTRG_8 (2 << 6) 817 #define UART_FCR_RTRG_15 (3 << 6) 818 819 /* 820 * Define macros for UART_LCR 821 * UART Line Control Register 822 */ 823 #define UART_LCR_WLEN (3 << 0) /* word length */ 824 #define UART_LCR_WLEN_5 (0 << 0) 825 #define UART_LCR_WLEN_6 (1 << 0) 826 #define UART_LCR_WLEN_7 (2 << 0) 827 #define UART_LCR_WLEN_8 (3 << 0) 828 #define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 829 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 830 #define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 831 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 832 #define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 833 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ 834 835 #define UART_LCR_PE (1 << 3) /* 0: parity disable */ 836 #define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ 837 #define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ 838 #define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ 839 #define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ 840 841 /* 842 * Define macros for UART_LSR 843 * UART Line Status Register 844 */ 845 #define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ 846 #define UART_LSR_ORER (1 << 1) /* 0: no overrun error */ 847 #define UART_LSR_PER (1 << 2) /* 0: no parity error */ 848 #define UART_LSR_FER (1 << 3) /* 0; no framing error */ 849 #define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ 850 #define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ 851 #define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ 852 #define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ 853 854 /* 855 * Define macros for UART_MCR 856 * UART Modem Control Register 857 */ 858 #define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ 859 #define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ 860 #define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */ 861 #define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ 862 #define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ 863 #define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ 864 865 /* 866 * Define macros for UART_MSR 867 * UART Modem Status Register 868 */ 869 #define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */ 870 #define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */ 871 #define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */ 872 #define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */ 873 #define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ 874 #define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ 875 #define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ 876 #define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ 877 878 /* 879 * Define macros for SIRCR 880 * Slow IrDA Control Register 881 */ 882 #define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */ 883 #define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */ 884 #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length 885 1: 0 pulse width is 1.6us for 115.2Kbps */ 886 #define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ 887 #define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ 888 889 890 891 /************************************************************************* 892 * INTC 893 *************************************************************************/ 894 #define INTC_ISR (INTC_BASE + 0x00) 895 #define INTC_IMR (INTC_BASE + 0x04) 896 #define INTC_IMSR (INTC_BASE + 0x08) 897 #define INTC_IMCR (INTC_BASE + 0x0c) 898 #define INTC_IPR (INTC_BASE + 0x10) 899 900 #define REG_INTC_ISR REG32(INTC_ISR) 901 #define REG_INTC_IMR REG32(INTC_IMR) 902 #define REG_INTC_IMSR REG32(INTC_IMSR) 903 #define REG_INTC_IMCR REG32(INTC_IMCR) 904 #define REG_INTC_IPR REG32(INTC_IPR) 905 906 #define IRQ_I2C 1 907 #define IRQ_PS2 2 908 #define IRQ_UPRT 3 909 #define IRQ_CORE 4 910 #define IRQ_UART3 6 911 #define IRQ_UART2 7 912 #define IRQ_UART1 8 913 #define IRQ_UART0 9 914 #define IRQ_SCC1 10 915 #define IRQ_SCC0 11 916 #define IRQ_UDC 12 917 #define IRQ_UHC 13 918 #define IRQ_MSC 14 919 #define IRQ_RTC 15 920 #define IRQ_FIR 16 921 #define IRQ_SSI 17 922 #define IRQ_CIM 18 923 #define IRQ_ETH 19 924 #define IRQ_AIC 20 925 #define IRQ_DMAC 21 926 #define IRQ_OST2 22 927 #define IRQ_OST1 23 928 #define IRQ_OST0 24 929 #define IRQ_GPIO3 25 930 #define IRQ_GPIO2 26 931 #define IRQ_GPIO1 27 932 #define IRQ_GPIO0 28 933 #define IRQ_LCD 30 934 935 936 937 938 /************************************************************************* 939 * CIM 940 *************************************************************************/ 941 #define CIM_CFG (CIM_BASE + 0x0000) 942 #define CIM_CTRL (CIM_BASE + 0x0004) 943 #define CIM_STATE (CIM_BASE + 0x0008) 944 #define CIM_IID (CIM_BASE + 0x000C) 945 #define CIM_RXFIFO (CIM_BASE + 0x0010) 946 #define CIM_DA (CIM_BASE + 0x0020) 947 #define CIM_FA (CIM_BASE + 0x0024) 948 #define CIM_FID (CIM_BASE + 0x0028) 949 #define CIM_CMD (CIM_BASE + 0x002C) 950 951 #define REG_CIM_CFG REG32(CIM_CFG) 952 #define REG_CIM_CTRL REG32(CIM_CTRL) 953 #define REG_CIM_STATE REG32(CIM_STATE) 954 #define REG_CIM_IID REG32(CIM_IID) 955 #define REG_CIM_RXFIFO REG32(CIM_RXFIFO) 956 #define REG_CIM_DA REG32(CIM_DA) 957 #define REG_CIM_FA REG32(CIM_FA) 958 #define REG_CIM_FID REG32(CIM_FID) 959 #define REG_CIM_CMD REG32(CIM_CMD) 960 961 /* CIM Configuration Register (CIM_CFG) */ 962 963 #define CIM_CFG_INV_DAT (1 << 15) 964 #define CIM_CFG_VSP (1 << 14) 965 #define CIM_CFG_HSP (1 << 13) 966 #define CIM_CFG_PCP (1 << 12) 967 #define CIM_CFG_DUMMY_ZERO (1 << 9) 968 #define CIM_CFG_EXT_VSYNC (1 << 8) 969 #define CIM_CFG_PACK_BIT 4 970 #define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) 971 #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) 972 #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) 973 #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) 974 #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) 975 #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) 976 #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) 977 #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) 978 #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) 979 #define CIM_CFG_DSM_BIT 0 980 #define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) 981 #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */ 982 #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */ 983 #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */ 984 #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */ 985 986 /* CIM Control Register (CIM_CTRL) */ 987 988 #define CIM_CTRL_MCLKDIV_BIT 24 989 #define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) 990 #define CIM_CTRL_FRC_BIT 16 991 #define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) 992 #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */ 993 #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */ 994 #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */ 995 #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */ 996 #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */ 997 #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */ 998 #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */ 999 #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */ 1000 #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */ 1001 #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */ 1002 #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */ 1003 #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */ 1004 #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */ 1005 #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */ 1006 #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */ 1007 #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */ 1008 #define CIM_CTRL_VDDM (1 << 13) 1009 #define CIM_CTRL_DMA_SOFM (1 << 12) 1010 #define CIM_CTRL_DMA_EOFM (1 << 11) 1011 #define CIM_CTRL_DMA_STOPM (1 << 10) 1012 #define CIM_CTRL_RXF_TRIGM (1 << 9) 1013 #define CIM_CTRL_RXF_OFM (1 << 8) 1014 #define CIM_CTRL_RXF_TRIG_BIT 4 1015 #define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) 1016 #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */ 1017 #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */ 1018 #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */ 1019 #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */ 1020 #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */ 1021 #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */ 1022 #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */ 1023 #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */ 1024 #define CIM_CTRL_DMA_EN (1 << 2) 1025 #define CIM_CTRL_RXF_RST (1 << 1) 1026 #define CIM_CTRL_ENA (1 << 0) 1027 1028 /* CIM State Register (CIM_STATE) */ 1029 1030 #define CIM_STATE_DMA_SOF (1 << 6) 1031 #define CIM_STATE_DMA_EOF (1 << 5) 1032 #define CIM_STATE_DMA_STOP (1 << 4) 1033 #define CIM_STATE_RXF_OF (1 << 3) 1034 #define CIM_STATE_RXF_TRIG (1 << 2) 1035 #define CIM_STATE_RXF_EMPTY (1 << 1) 1036 #define CIM_STATE_VDD (1 << 0) 1037 1038 /* CIM DMA Command Register (CIM_CMD) */ 1039 1040 #define CIM_CMD_SOFINT (1 << 31) 1041 #define CIM_CMD_EOFINT (1 << 30) 1042 #define CIM_CMD_STOP (1 << 28) 1043 #define CIM_CMD_LEN_BIT 0 1044 #define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) 1045 1046 1047 1048 1049 /************************************************************************* 1050 * PWM 1051 *************************************************************************/ 1052 #define PWM_CTR(n) (PWM##n##_BASE + 0x000) 1053 #define PWM_PER(n) (PWM##n##_BASE + 0x004) 1054 #define PWM_DUT(n) (PWM##n##_BASE + 0x008) 1055 1056 #define REG_PWM_CTR(n) REG8(PWM_CTR(n)) 1057 #define REG_PWM_PER(n) REG16(PWM_PER(n)) 1058 #define REG_PWM_DUT(n) REG16(PWM_DUT(n)) 1059 1060 /* PWM Control Register (PWM_CTR) */ 1061 1062 #define PWM_CTR_EN (1 << 7) 1063 #define PWM_CTR_SD (1 << 6) 1064 #define PWM_CTR_PRESCALE_BIT 0 1065 #define PWM_CTR_PRESCALE_MASK (0x3f << PWM_CTR_PRESCALE_BIT) 1066 1067 /* PWM Period Register (PWM_PER) */ 1068 1069 #define PWM_PER_PERIOD_BIT 0 1070 #define PWM_PER_PERIOD_MASK (0x3ff << PWM_PER_PERIOD_BIT) 1071 1072 /* PWM Duty Register (PWM_DUT) */ 1073 1074 #define PWM_DUT_FDUTY (1 << 10) 1075 #define PWM_DUT_DUTY_BIT 0 1076 #define PWM_DUT_DUTY_MASK (0x3ff << PWM_DUT_DUTY_BIT) 1077 1078 1079 1080 1081 /************************************************************************* 1082 * EMC 1083 *************************************************************************/ 1084 #define EMC_BCR (EMC_BASE + 0x00) 1085 #define EMC_SMCR0 (EMC_BASE + 0x10) 1086 #define EMC_SMCR1 (EMC_BASE + 0x14) 1087 #define EMC_SMCR2 (EMC_BASE + 0x18) 1088 #define EMC_SMCR3 (EMC_BASE + 0x1c) 1089 #define EMC_SMCR4 (EMC_BASE + 0x20) 1090 #define EMC_SMCR5 (EMC_BASE + 0x24) 1091 #define EMC_SMCR6 (EMC_BASE + 0x28) 1092 #define EMC_SMCR7 (EMC_BASE + 0x2c) 1093 #define EMC_SACR0 (EMC_BASE + 0x30) 1094 #define EMC_SACR1 (EMC_BASE + 0x34) 1095 #define EMC_SACR2 (EMC_BASE + 0x38) 1096 #define EMC_SACR3 (EMC_BASE + 0x3c) 1097 #define EMC_SACR4 (EMC_BASE + 0x40) 1098 #define EMC_SACR5 (EMC_BASE + 0x44) 1099 #define EMC_SACR6 (EMC_BASE + 0x48) 1100 #define EMC_SACR7 (EMC_BASE + 0x4c) 1101 #define EMC_NFCSR (EMC_BASE + 0x50) 1102 #define EMC_NFECC (EMC_BASE + 0x54) 1103 #define EMC_PCCR1 (EMC_BASE + 0x60) 1104 #define EMC_PCCR2 (EMC_BASE + 0x64) 1105 #define EMC_PCCR3 (EMC_BASE + 0x68) 1106 #define EMC_PCCR4 (EMC_BASE + 0x6c) 1107 #define EMC_DMCR (EMC_BASE + 0x80) 1108 #define EMC_RTCSR (EMC_BASE + 0x84) 1109 #define EMC_RTCNT (EMC_BASE + 0x88) 1110 #define EMC_RTCOR (EMC_BASE + 0x8c) 1111 #define EMC_DMAR1 (EMC_BASE + 0x90) 1112 #define EMC_DMAR2 (EMC_BASE + 0x94) 1113 #define EMC_DMAR3 (EMC_BASE + 0x98) 1114 #define EMC_DMAR4 (EMC_BASE + 0x9c) 1115 1116 #define EMC_SDMR0 (EMC_BASE + 0xa000) 1117 #define EMC_SDMR1 (EMC_BASE + 0xb000) 1118 #define EMC_SDMR2 (EMC_BASE + 0xc000) 1119 #define EMC_SDMR3 (EMC_BASE + 0xd000) 1120 1121 /* NAND command/address/data port */ 1122 #define NAND_DATAPORT 0xB4000000 /* read-write area */ 1123 #define NAND_COMMPORT 0xB4040000 /* write only area */ 1124 #define NAND_ADDRPORT 0xB4080000 /* write only area */ 1125 1126 #define REG_EMC_BCR REG32(EMC_BCR) 1127 #define REG_EMC_SMCR0 REG32(EMC_SMCR0) 1128 #define REG_EMC_SMCR1 REG32(EMC_SMCR1) 1129 #define REG_EMC_SMCR2 REG32(EMC_SMCR2) 1130 #define REG_EMC_SMCR3 REG32(EMC_SMCR3) 1131 #define REG_EMC_SMCR4 REG32(EMC_SMCR4) 1132 #define REG_EMC_SMCR5 REG32(EMC_SMCR5) 1133 #define REG_EMC_SMCR6 REG32(EMC_SMCR6) 1134 #define REG_EMC_SMCR7 REG32(EMC_SMCR7) 1135 #define REG_EMC_SACR0 REG32(EMC_SACR0) 1136 #define REG_EMC_SACR1 REG32(EMC_SACR1) 1137 #define REG_EMC_SACR2 REG32(EMC_SACR2) 1138 #define REG_EMC_SACR3 REG32(EMC_SACR3) 1139 #define REG_EMC_SACR4 REG32(EMC_SACR4) 1140 #define REG_EMC_SACR5 REG32(EMC_SACR5) 1141 #define REG_EMC_SACR6 REG32(EMC_SACR6) 1142 #define REG_EMC_SACR7 REG32(EMC_SACR7) 1143 #define REG_EMC_NFCSR REG32(EMC_NFCSR) 1144 #define REG_EMC_NFECC REG32(EMC_NFECC) 1145 #define REG_EMC_DMCR REG32(EMC_DMCR) 1146 #define REG_EMC_RTCSR REG16(EMC_RTCSR) 1147 #define REG_EMC_RTCNT REG16(EMC_RTCNT) 1148 #define REG_EMC_RTCOR REG16(EMC_RTCOR) 1149 #define REG_EMC_DMAR1 REG32(EMC_DMAR1) 1150 #define REG_EMC_DMAR2 REG32(EMC_DMAR2) 1151 #define REG_EMC_DMAR3 REG32(EMC_DMAR3) 1152 #define REG_EMC_DMAR4 REG32(EMC_DMAR4) 1153 #define REG_EMC_PCCR1 REG32(EMC_PCCR1) 1154 #define REG_EMC_PCCR2 REG32(EMC_PCCR2) 1155 #define REG_EMC_PCCR3 REG32(EMC_PCCR3) 1156 #define REG_EMC_PCCR4 REG32(EMC_PCCR4) 1157 1158 1159 #define EMC_BCR_BRE (1 << 1) 1160 1161 #define EMC_SMCR_STRV_BIT 24 1162 #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) 1163 #define EMC_SMCR_TAW_BIT 20 1164 #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) 1165 #define EMC_SMCR_TBP_BIT 16 1166 #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) 1167 #define EMC_SMCR_TAH_BIT 12 1168 #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) 1169 #define EMC_SMCR_TAS_BIT 8 1170 #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) 1171 #define EMC_SMCR_BW_BIT 6 1172 #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) 1173 #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) 1174 #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) 1175 #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) 1176 #define EMC_SMCR_BCM (1 << 3) 1177 #define EMC_SMCR_BL_BIT 1 1178 #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) 1179 #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) 1180 #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) 1181 #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) 1182 #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) 1183 #define EMC_SMCR_SMT (1 << 0) 1184 1185 #define EMC_SACR_BASE_BIT 8 1186 #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) 1187 #define EMC_SACR_MASK_BIT 0 1188 #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) 1189 1190 #define EMC_NFCSR_RB (1 << 7) 1191 #define EMC_NFCSR_BOOT_SEL_BIT 4 1192 #define EMC_NFCSR_BOOT_SEL_MASK (0x07 << EMC_NFCSR_BOOT_SEL_BIT) 1193 #define EMC_NFCSR_ERST (1 << 3) 1194 #define EMC_NFCSR_ECCE (1 << 2) 1195 #define EMC_NFCSR_FCE (1 << 1) 1196 #define EMC_NFCSR_NFE (1 << 0) 1197 1198 #define EMC_NFECC_ECC2_BIT 16 1199 #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) 1200 #define EMC_NFECC_ECC1_BIT 8 1201 #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) 1202 #define EMC_NFECC_ECC0_BIT 0 1203 #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) 1204 1205 #define EMC_DMCR_BW_BIT 31 1206 #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) 1207 #define EMC_DMCR_BW_32 (0 << EMC_DMCR_BW_BIT) 1208 #define EMC_DMCR_BW_16 (1 << EMC_DMCR_BW_BIT) 1209 #define EMC_DMCR_CA_BIT 26 1210 #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) 1211 #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) 1212 #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) 1213 #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) 1214 #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) 1215 #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) 1216 #define EMC_DMCR_RMODE (1 << 25) 1217 #define EMC_DMCR_RFSH (1 << 24) 1218 #define EMC_DMCR_MRSET (1 << 23) 1219 #define EMC_DMCR_RA_BIT 20 1220 #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) 1221 #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) 1222 #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) 1223 #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) 1224 #define EMC_DMCR_BA_BIT 19 1225 #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) 1226 #define EMC_DMCR_BA_2 (0 << EMC_DMCR_BA_BIT) 1227 #define EMC_DMCR_BA_4 (1 << EMC_DMCR_BA_BIT) 1228 #define EMC_DMCR_PDM (1 << 18) 1229 #define EMC_DMCR_EPIN (1 << 17) 1230 #define EMC_DMCR_TRAS_BIT 13 1231 #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) 1232 #define EMC_DMCR_RCD_BIT 11 1233 #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) 1234 #define EMC_DMCR_TPC_BIT 8 1235 #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) 1236 #define EMC_DMCR_TRWL_BIT 5 1237 #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) 1238 #define EMC_DMCR_TRC_BIT 2 1239 #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) 1240 #define EMC_DMCR_TCL_BIT 0 1241 #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) 1242 #define EMC_DMCR_CASL_2 (1 << EMC_DMCR_TCL_BIT) 1243 #define EMC_DMCR_CASL_3 (2 << EMC_DMCR_TCL_BIT) 1244 1245 #define EMC_RTCSR_CMF (1 << 7) 1246 #define EMC_RTCSR_CKS_BIT 0 1247 #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) 1248 #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) 1249 #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) 1250 #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) 1251 #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) 1252 #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) 1253 #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) 1254 #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) 1255 #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) 1256 1257 #define EMC_DMAR_BASE_BIT 8 1258 #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) 1259 #define EMC_DMAR_MASK_BIT 0 1260 #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) 1261 1262 #define EMC_SDMR_BM (1 << 9) 1263 #define EMC_SDMR_OM_BIT 7 1264 #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) 1265 #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) 1266 #define EMC_SDMR_CAS_BIT 4 1267 #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) 1268 #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) 1269 #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) 1270 #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) 1271 #define EMC_SDMR_BT_BIT 3 1272 #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) 1273 #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) 1274 #define EMC_SDMR_BT_INTR (1 << EMC_SDMR_BT_BIT) 1275 #define EMC_SDMR_BL_BIT 0 1276 #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) 1277 #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) 1278 #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) 1279 #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) 1280 #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) 1281 1282 #define EMC_SDMR_CAS2_16BIT \ 1283 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) 1284 #define EMC_SDMR_CAS2_32BIT \ 1285 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) 1286 #define EMC_SDMR_CAS3_16BIT \ 1287 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) 1288 #define EMC_SDMR_CAS3_32BIT \ 1289 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) 1290 1291 #define EMC_PCCR12_AMW (1 << 31) 1292 #define EMC_PCCR12_AMAS_BIT 28 1293 #define EMC_PCCR12_AMAS_MASK (0x07 << EMC_PCCR12_AMAS_BIT) 1294 #define EMC_PCCR12_AMAH_BIT 24 1295 #define EMC_PCCR12_AMAH_MASK (0x07 << EMC_PCCR12_AMAH_BIT) 1296 #define EMC_PCCR12_AMPW_BIT 20 1297 #define EMC_PCCR12_AMPW_MASK (0x0f << EMC_PCCR12_AMPW_BIT) 1298 #define EMC_PCCR12_AMRT_BIT 16 1299 #define EMC_PCCR12_AMRT_MASK (0x0f << EMC_PCCR12_AMRT_BIT) 1300 #define EMC_PCCR12_CMW (1 << 15) 1301 #define EMC_PCCR12_CMAS_BIT 12 1302 #define EMC_PCCR12_CMAS_MASK (0x07 << EMC_PCCR12_CMAS_BIT) 1303 #define EMC_PCCR12_CMAH_BIT 8 1304 #define EMC_PCCR12_CMAH_MASK (0x07 << EMC_PCCR12_CMAH_BIT) 1305 #define EMC_PCCR12_CMPW_BIT 4 1306 #define EMC_PCCR12_CMPW_MASK (0x0f << EMC_PCCR12_CMPW_BIT) 1307 #define EMC_PCCR12_CMRT_BIT 0 1308 #define EMC_PCCR12_CMRT_MASK (0x07 << EMC_PCCR12_CMRT_BIT) 1309 1310 #define EMC_PCCR34_DRS_BIT 16 1311 #define EMC_PCCR34_DRS_MASK (0x03 << EMC_PCCR34_DRS_BIT) 1312 #define EMC_PCCR34_DRS_SPKR (1 << EMC_PCCR34_DRS_BIT) 1313 #define EMC_PCCR34_DRS_IOIS16 (2 << EMC_PCCR34_DRS_BIT) 1314 #define EMC_PCCR34_DRS_INPACK (3 << EMC_PCCR34_DRS_BIT) 1315 #define EMC_PCCR34_IOIS16 (1 << 15) 1316 #define EMC_PCCR34_IOW (1 << 14) 1317 #define EMC_PCCR34_TCB_BIT 12 1318 #define EMC_PCCR34_TCB_MASK (0x03 << EMC_PCCR34_TCB_BIT) 1319 #define EMC_PCCR34_IORT_BIT 8 1320 #define EMC_PCCR34_IORT_MASK (0x07 << EMC_PCCR34_IORT_BIT) 1321 #define EMC_PCCR34_IOAE_BIT 6 1322 #define EMC_PCCR34_IOAE_MASK (0x03 << EMC_PCCR34_IOAE_BIT) 1323 #define EMC_PCCR34_IOAE_NONE (0 << EMC_PCCR34_IOAE_BIT) 1324 #define EMC_PCCR34_IOAE_1 (1 << EMC_PCCR34_IOAE_BIT) 1325 #define EMC_PCCR34_IOAE_2 (2 << EMC_PCCR34_IOAE_BIT) 1326 #define EMC_PCCR34_IOAE_5 (3 << EMC_PCCR34_IOAE_BIT) 1327 #define EMC_PCCR34_IOAH_BIT 4 1328 #define EMC_PCCR34_IOAH_MASK (0x03 << EMC_PCCR34_IOAH_BIT) 1329 #define EMC_PCCR34_IOAH_NONE (0 << EMC_PCCR34_IOAH_BIT) 1330 #define EMC_PCCR34_IOAH_1 (1 << EMC_PCCR34_IOAH_BIT) 1331 #define EMC_PCCR34_IOAH_2 (2 << EMC_PCCR34_IOAH_BIT) 1332 #define EMC_PCCR34_IOAH_5 (3 << EMC_PCCR34_IOAH_BIT) 1333 #define EMC_PCCR34_IOPW_BIT 0 1334 #define EMC_PCCR34_IOPW_MASK (0x0f << EMC_PCCR34_IOPW_BIT) 1335 1336 1337 1338 1339 /************************************************************************* 1340 * GPIO 1341 *************************************************************************/ 1342 #define GPIO_GPDR(n) (GPIO_BASE + (0x00 + (n)*0x30)) 1343 #define GPIO_GPDIR(n) (GPIO_BASE + (0x04 + (n)*0x30)) 1344 #define GPIO_GPODR(n) (GPIO_BASE + (0x08 + (n)*0x30)) 1345 #define GPIO_GPPUR(n) (GPIO_BASE + (0x0c + (n)*0x30)) 1346 #define GPIO_GPALR(n) (GPIO_BASE + (0x10 + (n)*0x30)) 1347 #define GPIO_GPAUR(n) (GPIO_BASE + (0x14 + (n)*0x30)) 1348 #define GPIO_GPIDLR(n) (GPIO_BASE + (0x18 + (n)*0x30)) 1349 #define GPIO_GPIDUR(n) (GPIO_BASE + (0x1c + (n)*0x30)) 1350 #define GPIO_GPIER(n) (GPIO_BASE + (0x20 + (n)*0x30)) 1351 #define GPIO_GPIMR(n) (GPIO_BASE + (0x24 + (n)*0x30)) 1352 #define GPIO_GPFR(n) (GPIO_BASE + (0x28 + (n)*0x30)) 1353 1354 #define REG_GPIO_GPDR(n) REG32(GPIO_GPDR((n))) 1355 #define REG_GPIO_GPDIR(n) REG32(GPIO_GPDIR((n))) 1356 #define REG_GPIO_GPODR(n) REG32(GPIO_GPODR((n))) 1357 #define REG_GPIO_GPPUR(n) REG32(GPIO_GPPUR((n))) 1358 #define REG_GPIO_GPALR(n) REG32(GPIO_GPALR((n))) 1359 #define REG_GPIO_GPAUR(n) REG32(GPIO_GPAUR((n))) 1360 #define REG_GPIO_GPIDLR(n) REG32(GPIO_GPIDLR((n))) 1361 #define REG_GPIO_GPIDUR(n) REG32(GPIO_GPIDUR((n))) 1362 #define REG_GPIO_GPIER(n) REG32(GPIO_GPIER((n))) 1363 #define REG_GPIO_GPIMR(n) REG32(GPIO_GPIMR((n))) 1364 #define REG_GPIO_GPFR(n) REG32(GPIO_GPFR((n))) 1365 1366 #define GPIO_IRQ_LOLEVEL 0 1367 #define GPIO_IRQ_HILEVEL 1 1368 #define GPIO_IRQ_FALLEDG 2 1369 #define GPIO_IRQ_RAISEDG 3 1370 1371 #define IRQ_GPIO_0 48 1372 #define NUM_GPIO 100 1373 1374 #define GPIO_GPDR0 GPIO_GPDR(0) 1375 #define GPIO_GPDR1 GPIO_GPDR(1) 1376 #define GPIO_GPDR2 GPIO_GPDR(2) 1377 #define GPIO_GPDR3 GPIO_GPDR(3) 1378 #define GPIO_GPDIR0 GPIO_GPDIR(0) 1379 #define GPIO_GPDIR1 GPIO_GPDIR(1) 1380 #define GPIO_GPDIR2 GPIO_GPDIR(2) 1381 #define GPIO_GPDIR3 GPIO_GPDIR(3) 1382 #define GPIO_GPODR0 GPIO_GPODR(0) 1383 #define GPIO_GPODR1 GPIO_GPODR(1) 1384 #define GPIO_GPODR2 GPIO_GPODR(2) 1385 #define GPIO_GPODR3 GPIO_GPODR(3) 1386 #define GPIO_GPPUR0 GPIO_GPPUR(0) 1387 #define GPIO_GPPUR1 GPIO_GPPUR(1) 1388 #define GPIO_GPPUR2 GPIO_GPPUR(2) 1389 #define GPIO_GPPUR3 GPIO_GPPUR(3) 1390 #define GPIO_GPALR0 GPIO_GPALR(0) 1391 #define GPIO_GPALR1 GPIO_GPALR(1) 1392 #define GPIO_GPALR2 GPIO_GPALR(2) 1393 #define GPIO_GPALR3 GPIO_GPALR(3) 1394 #define GPIO_GPAUR0 GPIO_GPAUR(0) 1395 #define GPIO_GPAUR1 GPIO_GPAUR(1) 1396 #define GPIO_GPAUR2 GPIO_GPAUR(2) 1397 #define GPIO_GPAUR3 GPIO_GPAUR(3) 1398 #define GPIO_GPIDLR0 GPIO_GPIDLR(0) 1399 #define GPIO_GPIDLR1 GPIO_GPIDLR(1) 1400 #define GPIO_GPIDLR2 GPIO_GPIDLR(2) 1401 #define GPIO_GPIDLR3 GPIO_GPIDLR(3) 1402 #define GPIO_GPIDUR0 GPIO_GPIDUR(0) 1403 #define GPIO_GPIDUR1 GPIO_GPIDUR(1) 1404 #define GPIO_GPIDUR2 GPIO_GPIDUR(2) 1405 #define GPIO_GPIDUR3 GPIO_GPIDUR(3) 1406 #define GPIO_GPIER0 GPIO_GPIER(0) 1407 #define GPIO_GPIER1 GPIO_GPIER(1) 1408 #define GPIO_GPIER2 GPIO_GPIER(2) 1409 #define GPIO_GPIER3 GPIO_GPIER(3) 1410 #define GPIO_GPIMR0 GPIO_GPIMR(0) 1411 #define GPIO_GPIMR1 GPIO_GPIMR(1) 1412 #define GPIO_GPIMR2 GPIO_GPIMR(2) 1413 #define GPIO_GPIMR3 GPIO_GPIMR(3) 1414 #define GPIO_GPFR0 GPIO_GPFR(0) 1415 #define GPIO_GPFR1 GPIO_GPFR(1) 1416 #define GPIO_GPFR2 GPIO_GPFR(2) 1417 #define GPIO_GPFR3 GPIO_GPFR(3) 1418 1419 1420 /************************************************************************* 1421 * HARB 1422 *************************************************************************/ 1423 #define HARB_HAPOR (HARB_BASE + 0x000) 1424 #define HARB_HMCTR (HARB_BASE + 0x010) 1425 #define HARB_HME8H (HARB_BASE + 0x014) 1426 #define HARB_HMCR1 (HARB_BASE + 0x018) 1427 #define HARB_HMER2 (HARB_BASE + 0x01C) 1428 #define HARB_HMER3 (HARB_BASE + 0x020) 1429 #define HARB_HMLTR (HARB_BASE + 0x024) 1430 1431 #define REG_HARB_HAPOR REG32(HARB_HAPOR) 1432 #define REG_HARB_HMCTR REG32(HARB_HMCTR) 1433 #define REG_HARB_HME8H REG32(HARB_HME8H) 1434 #define REG_HARB_HMCR1 REG32(HARB_HMCR1) 1435 #define REG_HARB_HMER2 REG32(HARB_HMER2) 1436 #define REG_HARB_HMER3 REG32(HARB_HMER3) 1437 #define REG_HARB_HMLTR REG32(HARB_HMLTR) 1438 1439 /* HARB Priority Order Register (HARB_HAPOR) */ 1440 1441 #define HARB_HAPOR_UCHSEL (1 << 7) 1442 #define HARB_HAPOR_PRIO_BIT 0 1443 #define HARB_HAPOR_PRIO_MASK (0xf << HARB_HAPOR_PRIO_BIT) 1444 1445 /* AHB Monitor Control Register (HARB_HMCTR) */ 1446 1447 #define HARB_HMCTR_HET3_BIT 20 1448 #define HARB_HMCTR_HET3_MASK (0xf << HARB_HMCTR_HET3_BIT) 1449 #define HARB_HMCTR_HMS3_BIT 16 1450 #define HARB_HMCTR_HMS3_MASK (0xf << HARB_HMCTR_HMS3_BIT) 1451 #define HARB_HMCTR_HET2_BIT 12 1452 #define HARB_HMCTR_HET2_MASK (0xf << HARB_HMCTR_HET2_BIT) 1453 #define HARB_HMCTR_HMS2_BIT 8 1454 #define HARB_HMCTR_HMS2_MASK (0xf << HARB_HMCTR_HMS2_BIT) 1455 #define HARB_HMCTR_HOVF3 (1 << 7) 1456 #define HARB_HMCTR_HOVF2 (1 << 6) 1457 #define HARB_HMCTR_HOVF1 (1 << 5) 1458 #define HARB_HMCTR_HRST (1 << 4) 1459 #define HARB_HMCTR_HEE3 (1 << 2) 1460 #define HARB_HMCTR_HEE2 (1 << 1) 1461 #define HARB_HMCTR_HEE1 (1 << 0) 1462 1463 /* AHB Monitor Event 8bits High Register (HARB_HME8H) */ 1464 1465 #define HARB_HME8H_HC8H1_BIT 16 1466 #define HARB_HME8H_HC8H1_MASK (0xff << HARB_HME8H_HC8H1_BIT) 1467 #define HARB_HME8H_HC8H2_BIT 8 1468 #define HARB_HME8H_HC8H2_MASK (0xff << HARB_HME8H_HC8H2_BIT) 1469 #define HARB_HME8H_HC8H3_BIT 0 1470 #define HARB_HME8H_HC8H3_MASK (0xff << HARB_HME8H_HC8H3_BIT) 1471 1472 /* AHB Monitor Latency Register (HARB_HMLTR) */ 1473 1474 #define HARB_HMLTR_HLT2_BIT 16 1475 #define HARB_HMLTR_HLT2_MASK (0xffff << HARB_HMLTR_HLT2_BIT) 1476 #define HARB_HMLTR_HLT3_BIT 0 1477 #define HARB_HMLTR_HLT3_MASK (0xffff << HARB_HMLTR_HLT3_BIT) 1478 1479 1480 1481 1482 /************************************************************************* 1483 * I2C 1484 *************************************************************************/ 1485 #define I2C_DR (I2C_BASE + 0x000) 1486 #define I2C_CR (I2C_BASE + 0x004) 1487 #define I2C_SR (I2C_BASE + 0x008) 1488 #define I2C_GR (I2C_BASE + 0x00C) 1489 1490 #define REG_I2C_DR REG8(I2C_DR) 1491 #define REG_I2C_CR REG8(I2C_CR) 1492 #define REG_I2C_SR REG8(I2C_SR) 1493 #define REG_I2C_GR REG16(I2C_GR) 1494 1495 /* I2C Control Register (I2C_CR) */ 1496 1497 #define I2C_CR_IEN (1 << 4) 1498 #define I2C_CR_STA (1 << 3) 1499 #define I2C_CR_STO (1 << 2) 1500 #define I2C_CR_AC (1 << 1) 1501 #define I2C_CR_I2CE (1 << 0) 1502 1503 /* I2C Status Register (I2C_SR) */ 1504 1505 #define I2C_SR_STX (1 << 4) 1506 #define I2C_SR_BUSY (1 << 3) 1507 #define I2C_SR_TEND (1 << 2) 1508 #define I2C_SR_DRF (1 << 1) 1509 #define I2C_SR_ACKF (1 << 0) 1510 1511 1512 1513 1514 /************************************************************************* 1515 * UDC 1516 *************************************************************************/ 1517 #define UDC_EP0InCR (UDC_BASE + 0x00) 1518 #define UDC_EP0InSR (UDC_BASE + 0x04) 1519 #define UDC_EP0InBSR (UDC_BASE + 0x08) 1520 #define UDC_EP0InMPSR (UDC_BASE + 0x0c) 1521 #define UDC_EP0InDesR (UDC_BASE + 0x14) 1522 #define UDC_EP1InCR (UDC_BASE + 0x20) 1523 #define UDC_EP1InSR (UDC_BASE + 0x24) 1524 #define UDC_EP1InBSR (UDC_BASE + 0x28) 1525 #define UDC_EP1InMPSR (UDC_BASE + 0x2c) 1526 #define UDC_EP1InDesR (UDC_BASE + 0x34) 1527 #define UDC_EP2InCR (UDC_BASE + 0x40) 1528 #define UDC_EP2InSR (UDC_BASE + 0x44) 1529 #define UDC_EP2InBSR (UDC_BASE + 0x48) 1530 #define UDC_EP2InMPSR (UDC_BASE + 0x4c) 1531 #define UDC_EP2InDesR (UDC_BASE + 0x54) 1532 #define UDC_EP3InCR (UDC_BASE + 0x60) 1533 #define UDC_EP3InSR (UDC_BASE + 0x64) 1534 #define UDC_EP3InBSR (UDC_BASE + 0x68) 1535 #define UDC_EP3InMPSR (UDC_BASE + 0x6c) 1536 #define UDC_EP3InDesR (UDC_BASE + 0x74) 1537 #define UDC_EP4InCR (UDC_BASE + 0x80) 1538 #define UDC_EP4InSR (UDC_BASE + 0x84) 1539 #define UDC_EP4InBSR (UDC_BASE + 0x88) 1540 #define UDC_EP4InMPSR (UDC_BASE + 0x8c) 1541 #define UDC_EP4InDesR (UDC_BASE + 0x94) 1542 1543 #define UDC_EP0OutCR (UDC_BASE + 0x200) 1544 #define UDC_EP0OutSR (UDC_BASE + 0x204) 1545 #define UDC_EP0OutPFNR (UDC_BASE + 0x208) 1546 #define UDC_EP0OutMPSR (UDC_BASE + 0x20c) 1547 #define UDC_EP0OutSBPR (UDC_BASE + 0x210) 1548 #define UDC_EP0OutDesR (UDC_BASE + 0x214) 1549 #define UDC_EP5OutCR (UDC_BASE + 0x2a0) 1550 #define UDC_EP5OutSR (UDC_BASE + 0x2a4) 1551 #define UDC_EP5OutPFNR (UDC_BASE + 0x2a8) 1552 #define UDC_EP5OutMPSR (UDC_BASE + 0x2ac) 1553 #define UDC_EP5OutDesR (UDC_BASE + 0x2b4) 1554 #define UDC_EP6OutCR (UDC_BASE + 0x2c0) 1555 #define UDC_EP6OutSR (UDC_BASE + 0x2c4) 1556 #define UDC_EP6OutPFNR (UDC_BASE + 0x2c8) 1557 #define UDC_EP6OutMPSR (UDC_BASE + 0x2cc) 1558 #define UDC_EP6OutDesR (UDC_BASE + 0x2d4) 1559 #define UDC_EP7OutCR (UDC_BASE + 0x2e0) 1560 #define UDC_EP7OutSR (UDC_BASE + 0x2e4) 1561 #define UDC_EP7OutPFNR (UDC_BASE + 0x2e8) 1562 #define UDC_EP7OutMPSR (UDC_BASE + 0x2ec) 1563 #define UDC_EP7OutDesR (UDC_BASE + 0x2f4) 1564 1565 #define UDC_DevCFGR (UDC_BASE + 0x400) 1566 #define UDC_DevCR (UDC_BASE + 0x404) 1567 #define UDC_DevSR (UDC_BASE + 0x408) 1568 #define UDC_DevIntR (UDC_BASE + 0x40c) 1569 #define UDC_DevIntMR (UDC_BASE + 0x410) 1570 #define UDC_EPIntR (UDC_BASE + 0x414) 1571 #define UDC_EPIntMR (UDC_BASE + 0x418) 1572 1573 #define UDC_STCMAR (UDC_BASE + 0x500) 1574 #define UDC_EP0InfR (UDC_BASE + 0x504) 1575 #define UDC_EP1InfR (UDC_BASE + 0x508) 1576 #define UDC_EP2InfR (UDC_BASE + 0x50c) 1577 #define UDC_EP3InfR (UDC_BASE + 0x510) 1578 #define UDC_EP4InfR (UDC_BASE + 0x514) 1579 #define UDC_EP5InfR (UDC_BASE + 0x518) 1580 #define UDC_EP6InfR (UDC_BASE + 0x51c) 1581 #define UDC_EP7InfR (UDC_BASE + 0x520) 1582 1583 #define UDC_TXCONFIRM (UDC_BASE + 0x41C) 1584 #define UDC_TXZLP (UDC_BASE + 0x420) 1585 #define UDC_RXCONFIRM (UDC_BASE + 0x41C) 1586 1587 #define UDC_RXFIFO (UDC_BASE + 0x800) 1588 #define UDC_TXFIFOEP0 (UDC_BASE + 0x840) 1589 1590 #define REG_UDC_EP0InCR REG32(UDC_EP0InCR) 1591 #define REG_UDC_EP0InSR REG32(UDC_EP0InSR) 1592 #define REG_UDC_EP0InBSR REG32(UDC_EP0InBSR) 1593 #define REG_UDC_EP0InMPSR REG32(UDC_EP0InMPSR) 1594 #define REG_UDC_EP0InDesR REG32(UDC_EP0InDesR) 1595 #define REG_UDC_EP1InCR REG32(UDC_EP1InCR) 1596 #define REG_UDC_EP1InSR REG32(UDC_EP1InSR) 1597 #define REG_UDC_EP1InBSR REG32(UDC_EP1InBSR) 1598 #define REG_UDC_EP1InMPSR REG32(UDC_EP1InMPSR) 1599 #define REG_UDC_EP1InDesR REG32(UDC_EP1InDesR) 1600 #define REG_UDC_EP2InCR REG32(UDC_EP2InCR) 1601 #define REG_UDC_EP2InSR REG32(UDC_EP2InSR) 1602 #define REG_UDC_EP2InBSR REG32(UDC_EP2InBSR) 1603 #define REG_UDC_EP2InMPSR REG32(UDC_EP2InMPSR) 1604 #define REG_UDC_EP2InDesR REG32(UDC_EP2InDesR) 1605 #define REG_UDC_EP3InCR REG32(UDC_EP3InCR) 1606 #define REG_UDC_EP3InSR REG32(UDC_EP3InSR) 1607 #define REG_UDC_EP3InBSR REG32(UDC_EP3InBSR) 1608 #define REG_UDC_EP3InMPSR REG32(UDC_EP3InMPSR) 1609 #define REG_UDC_EP3InDesR REG32(UDC_EP3InDesR) 1610 #define REG_UDC_EP4InCR REG32(UDC_EP4InCR) 1611 #define REG_UDC_EP4InSR REG32(UDC_EP4InSR) 1612 #define REG_UDC_EP4InBSR REG32(UDC_EP4InBSR) 1613 #define REG_UDC_EP4InMPSR REG32(UDC_EP4InMPSR) 1614 #define REG_UDC_EP4InDesR REG32(UDC_EP4InDesR) 1615 1616 #define REG_UDC_EP0OutCR REG32(UDC_EP0OutCR) 1617 #define REG_UDC_EP0OutSR REG32(UDC_EP0OutSR) 1618 #define REG_UDC_EP0OutPFNR REG32(UDC_EP0OutPFNR) 1619 #define REG_UDC_EP0OutMPSR REG32(UDC_EP0OutMPSR) 1620 #define REG_UDC_EP0OutSBPR REG32(UDC_EP0OutSBPR) 1621 #define REG_UDC_EP0OutDesR REG32(UDC_EP0OutDesR) 1622 #define REG_UDC_EP5OutCR REG32(UDC_EP5OutCR) 1623 #define REG_UDC_EP5OutSR REG32(UDC_EP5OutSR) 1624 #define REG_UDC_EP5OutPFNR REG32(UDC_EP5OutPFNR) 1625 #define REG_UDC_EP5OutMPSR REG32(UDC_EP5OutMPSR) 1626 #define REG_UDC_EP5OutDesR REG32(UDC_EP5OutDesR) 1627 #define REG_UDC_EP6OutCR REG32(UDC_EP6OutCR) 1628 #define REG_UDC_EP6OutSR REG32(UDC_EP6OutSR) 1629 #define REG_UDC_EP6OutPFNR REG32(UDC_EP6OutPFNR) 1630 #define REG_UDC_EP6OutMPSR REG32(UDC_EP6OutMPSR) 1631 #define REG_UDC_EP6OutDesR REG32(UDC_EP6OutDesR) 1632 #define REG_UDC_EP7OutCR REG32(UDC_EP7OutCR) 1633 #define REG_UDC_EP7OutSR REG32(UDC_EP7OutSR) 1634 #define REG_UDC_EP7OutPFNR REG32(UDC_EP7OutPFNR) 1635 #define REG_UDC_EP7OutMPSR REG32(UDC_EP7OutMPSR) 1636 #define REG_UDC_EP7OutDesR REG32(UDC_EP7OutDesR) 1637 1638 #define REG_UDC_DevCFGR REG32(UDC_DevCFGR) 1639 #define REG_UDC_DevCR REG32(UDC_DevCR) 1640 #define REG_UDC_DevSR REG32(UDC_DevSR) 1641 #define REG_UDC_DevIntR REG32(UDC_DevIntR) 1642 #define REG_UDC_DevIntMR REG32(UDC_DevIntMR) 1643 #define REG_UDC_EPIntR REG32(UDC_EPIntR) 1644 #define REG_UDC_EPIntMR REG32(UDC_EPIntMR) 1645 1646 #define REG_UDC_STCMAR REG32(UDC_STCMAR) 1647 #define REG_UDC_EP0InfR REG32(UDC_EP0InfR) 1648 #define REG_UDC_EP1InfR REG32(UDC_EP1InfR) 1649 #define REG_UDC_EP2InfR REG32(UDC_EP2InfR) 1650 #define REG_UDC_EP3InfR REG32(UDC_EP3InfR) 1651 #define REG_UDC_EP4InfR REG32(UDC_EP4InfR) 1652 #define REG_UDC_EP5InfR REG32(UDC_EP5InfR) 1653 #define REG_UDC_EP6InfR REG32(UDC_EP6InfR) 1654 #define REG_UDC_EP7InfR REG32(UDC_EP7InfR) 1655 1656 #define UDC_DevCFGR_PI (1 << 5) 1657 #define UDC_DevCFGR_SS (1 << 4) 1658 #define UDC_DevCFGR_SP (1 << 3) 1659 #define UDC_DevCFGR_RW (1 << 2) 1660 #define UDC_DevCFGR_SPD_BIT 0 1661 #define UDC_DevCFGR_SPD_MASK (0x03 << UDC_DevCFGR_SPD_BIT) 1662 #define UDC_DevCFGR_SPD_HS (0 << UDC_DevCFGR_SPD_BIT) 1663 #define UDC_DevCFGR_SPD_LS (2 << UDC_DevCFGR_SPD_BIT) 1664 #define UDC_DevCFGR_SPD_FS (3 << UDC_DevCFGR_SPD_BIT) 1665 1666 #define UDC_DevCR_DM (1 << 9) 1667 #define UDC_DevCR_BE (1 << 5) 1668 #define UDC_DevCR_RES (1 << 0) 1669 1670 #define UDC_DevSR_ENUMSPD_BIT 13 1671 #define UDC_DevSR_ENUMSPD_MASK (0x03 << UDC_DevSR_ENUMSPD_BIT) 1672 #define UDC_DevSR_ENUMSPD_HS (0 << UDC_DevSR_ENUMSPD_BIT) 1673 #define UDC_DevSR_ENUMSPD_LS (2 << UDC_DevSR_ENUMSPD_BIT) 1674 #define UDC_DevSR_ENUMSPD_FS (3 << UDC_DevSR_ENUMSPD_BIT) 1675 #define UDC_DevSR_SUSP (1 << 12) 1676 #define UDC_DevSR_ALT_BIT 8 1677 #define UDC_DevSR_ALT_MASK (0x0f << UDC_DevSR_ALT_BIT) 1678 #define UDC_DevSR_INTF_BIT 4 1679 #define UDC_DevSR_INTF_MASK (0x0f << UDC_DevSR_INTF_BIT) 1680 #define UDC_DevSR_CFG_BIT 0 1681 #define UDC_DevSR_CFG_MASK (0x0f << UDC_DevSR_CFG_BIT) 1682 1683 #define UDC_DevIntR_ENUM (1 << 6) 1684 #define UDC_DevIntR_SOF (1 << 5) 1685 #define UDC_DevIntR_US (1 << 4) 1686 #define UDC_DevIntR_UR (1 << 3) 1687 #define UDC_DevIntR_SI (1 << 1) 1688 #define UDC_DevIntR_SC (1 << 0) 1689 1690 #define UDC_EPIntR_OUTEP_BIT 16 1691 #define UDC_EPIntR_OUTEP_MASK (0xffff << UDC_EPIntR_OUTEP_BIT) 1692 #define UDC_EPIntR_OUTEP0 0x00010000 1693 #define UDC_EPIntR_OUTEP5 0x00200000 1694 #define UDC_EPIntR_OUTEP6 0x00400000 1695 #define UDC_EPIntR_OUTEP7 0x00800000 1696 #define UDC_EPIntR_INEP_BIT 0 1697 #define UDC_EPIntR_INEP_MASK (0xffff << UDC_EPIntR_INEP_BIT) 1698 #define UDC_EPIntR_INEP0 0x00000001 1699 #define UDC_EPIntR_INEP1 0x00000002 1700 #define UDC_EPIntR_INEP2 0x00000004 1701 #define UDC_EPIntR_INEP3 0x00000008 1702 #define UDC_EPIntR_INEP4 0x00000010 1703 1704 1705 #define UDC_EPIntMR_OUTEP_BIT 16 1706 #define UDC_EPIntMR_OUTEP_MASK (0xffff << UDC_EPIntMR_OUTEP_BIT) 1707 #define UDC_EPIntMR_INEP_BIT 0 1708 #define UDC_EPIntMR_INEP_MASK (0xffff << UDC_EPIntMR_INEP_BIT) 1709 1710 #define UDC_EPCR_ET_BIT 4 1711 #define UDC_EPCR_ET_MASK (0x03 << UDC_EPCR_ET_BIT) 1712 #define UDC_EPCR_ET_CTRL (0 << UDC_EPCR_ET_BIT) 1713 #define UDC_EPCR_ET_ISO (1 << UDC_EPCR_ET_BIT) 1714 #define UDC_EPCR_ET_BULK (2 << UDC_EPCR_ET_BIT) 1715 #define UDC_EPCR_ET_INTR (3 << UDC_EPCR_ET_BIT) 1716 #define UDC_EPCR_SN (1 << 2) 1717 #define UDC_EPCR_F (1 << 1) 1718 #define UDC_EPCR_S (1 << 0) 1719 1720 #define UDC_EPSR_RXPKTSIZE_BIT 11 1721 #define UDC_EPSR_RXPKTSIZE_MASK (0x7ff << UDC_EPSR_RXPKTSIZE_BIT) 1722 #define UDC_EPSR_IN (1 << 6) 1723 #define UDC_EPSR_OUT_BIT 4 1724 #define UDC_EPSR_OUT_MASK (0x03 << UDC_EPSR_OUT_BIT) 1725 #define UDC_EPSR_OUT_NONE (0 << UDC_EPSR_OUT_BIT) 1726 #define UDC_EPSR_OUT_RCVDATA (1 << UDC_EPSR_OUT_BIT) 1727 #define UDC_EPSR_OUT_RCVSETUP (2 << UDC_EPSR_OUT_BIT) 1728 #define UDC_EPSR_PID_BIT 0 1729 #define UDC_EPSR_PID_MASK (0x0f << UDC_EPSR_PID_BIT) 1730 1731 #define UDC_EPInfR_MPS_BIT 19 1732 #define UDC_EPInfR_MPS_MASK (0x3ff << UDC_EPInfR_MPS_BIT) 1733 #define UDC_EPInfR_ALTS_BIT 15 1734 #define UDC_EPInfR_ALTS_MASK (0x0f << UDC_EPInfR_ALTS_BIT) 1735 #define UDC_EPInfR_IFN_BIT 11 1736 #define UDC_EPInfR_IFN_MASK (0x0f << UDC_EPInfR_IFN_BIT) 1737 #define UDC_EPInfR_CGN_BIT 7 1738 #define UDC_EPInfR_CGN_MASK (0x0f << UDC_EPInfR_CGN_BIT) 1739 #define UDC_EPInfR_EPT_BIT 5 1740 #define UDC_EPInfR_EPT_MASK (0x03 << UDC_EPInfR_EPT_BIT) 1741 #define UDC_EPInfR_EPT_CTRL (0 << UDC_EPInfR_EPT_BIT) 1742 #define UDC_EPInfR_EPT_ISO (1 << UDC_EPInfR_EPT_BIT) 1743 #define UDC_EPInfR_EPT_BULK (2 << UDC_EPInfR_EPT_BIT) 1744 #define UDC_EPInfR_EPT_INTR (3 << UDC_EPInfR_EPT_BIT) 1745 #define UDC_EPInfR_EPD (1 << 4) 1746 #define UDC_EPInfR_EPD_OUT (0 << 4) 1747 #define UDC_EPInfR_EPD_IN (1 << 4) 1748 1749 #define UDC_EPInfR_EPN_BIT 0 1750 #define UDC_EPInfR_EPN_MASK (0xf << UDC_EPInfR_EPN_BIT) 1751 1752 1753 1754 1755 /************************************************************************* 1756 * DMAC 1757 *************************************************************************/ 1758 #define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) 1759 #define DMAC_DDAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) 1760 #define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) 1761 #define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) 1762 #define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) 1763 #define DMAC_DMAIPR (DMAC_BASE + 0xf8) 1764 #define DMAC_DMACR (DMAC_BASE + 0xfc) 1765 1766 #define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n))) 1767 #define REG_DMAC_DDAR(n) REG32(DMAC_DDAR((n))) 1768 #define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n))) 1769 #define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n))) 1770 #define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) 1771 #define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR) 1772 #define REG_DMAC_DMACR REG32(DMAC_DMACR) 1773 1774 #define DMAC_DRSR_RS_BIT 0 1775 #define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT) 1776 #define DMAC_DRSR_RS_EXTREXTR (0 << DMAC_DRSR_RS_BIT) 1777 #define DMAC_DRSR_RS_PCMCIAOUT (4 << DMAC_DRSR_RS_BIT) 1778 #define DMAC_DRSR_RS_PCMCIAIN (5 << DMAC_DRSR_RS_BIT) 1779 #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) 1780 #define DMAC_DRSR_RS_DESOUT (10 << DMAC_DRSR_RS_BIT) 1781 #define DMAC_DRSR_RS_DESIN (11 << DMAC_DRSR_RS_BIT) 1782 #define DMAC_DRSR_RS_UART3OUT (14 << DMAC_DRSR_RS_BIT) 1783 #define DMAC_DRSR_RS_UART3IN (15 << DMAC_DRSR_RS_BIT) 1784 #define DMAC_DRSR_RS_UART2OUT (16 << DMAC_DRSR_RS_BIT) 1785 #define DMAC_DRSR_RS_UART2IN (17 << DMAC_DRSR_RS_BIT) 1786 #define DMAC_DRSR_RS_UART1OUT (18 << DMAC_DRSR_RS_BIT) 1787 #define DMAC_DRSR_RS_UART1IN (19 << DMAC_DRSR_RS_BIT) 1788 #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT) 1789 #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT) 1790 #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT) 1791 #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT) 1792 #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT) 1793 #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT) 1794 #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT) 1795 #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT) 1796 #define DMAC_DRSR_RS_OST2 (28 << DMAC_DRSR_RS_BIT) 1797 1798 #define DMAC_DCCSR_EACKS (1 << 31) 1799 #define DMAC_DCCSR_EACKM (1 << 30) 1800 #define DMAC_DCCSR_ERDM_BIT 28 1801 #define DMAC_DCCSR_ERDM_MASK (0x03 << DMAC_DCCSR_ERDM_BIT) 1802 #define DMAC_DCCSR_ERDM_LLEVEL (0 << DMAC_DCCSR_ERDM_BIT) 1803 #define DMAC_DCCSR_ERDM_FEDGE (1 << DMAC_DCCSR_ERDM_BIT) 1804 #define DMAC_DCCSR_ERDM_HLEVEL (2 << DMAC_DCCSR_ERDM_BIT) 1805 #define DMAC_DCCSR_ERDM_REDGE (3 << DMAC_DCCSR_ERDM_BIT) 1806 #define DMAC_DCCSR_EOPM (1 << 27) 1807 #define DMAC_DCCSR_SAM (1 << 23) 1808 #define DMAC_DCCSR_DAM (1 << 22) 1809 #define DMAC_DCCSR_RDIL_BIT 16 1810 #define DMAC_DCCSR_RDIL_MASK (0x0f << DMAC_DCCSR_RDIL_BIT) 1811 #define DMAC_DCCSR_RDIL_IGN (0 << DMAC_DCCSR_RDIL_BIT) 1812 #define DMAC_DCCSR_RDIL_2 (1 << DMAC_DCCSR_RDIL_BIT) 1813 #define DMAC_DCCSR_RDIL_4 (2 << DMAC_DCCSR_RDIL_BIT) 1814 #define DMAC_DCCSR_RDIL_8 (3 << DMAC_DCCSR_RDIL_BIT) 1815 #define DMAC_DCCSR_RDIL_12 (4 << DMAC_DCCSR_RDIL_BIT) 1816 #define DMAC_DCCSR_RDIL_16 (5 << DMAC_DCCSR_RDIL_BIT) 1817 #define DMAC_DCCSR_RDIL_20 (6 << DMAC_DCCSR_RDIL_BIT) 1818 #define DMAC_DCCSR_RDIL_24 (7 << DMAC_DCCSR_RDIL_BIT) 1819 #define DMAC_DCCSR_RDIL_28 (8 << DMAC_DCCSR_RDIL_BIT) 1820 #define DMAC_DCCSR_RDIL_32 (9 << DMAC_DCCSR_RDIL_BIT) 1821 #define DMAC_DCCSR_RDIL_48 (10 << DMAC_DCCSR_RDIL_BIT) 1822 #define DMAC_DCCSR_RDIL_60 (11 << DMAC_DCCSR_RDIL_BIT) 1823 #define DMAC_DCCSR_RDIL_64 (12 << DMAC_DCCSR_RDIL_BIT) 1824 #define DMAC_DCCSR_RDIL_124 (13 << DMAC_DCCSR_RDIL_BIT) 1825 #define DMAC_DCCSR_RDIL_128 (14 << DMAC_DCCSR_RDIL_BIT) 1826 #define DMAC_DCCSR_RDIL_200 (15 << DMAC_DCCSR_RDIL_BIT) 1827 #define DMAC_DCCSR_SWDH_BIT 14 1828 #define DMAC_DCCSR_SWDH_MASK (0x03 << DMAC_DCCSR_SWDH_BIT) 1829 #define DMAC_DCCSR_SWDH_32 (0 << DMAC_DCCSR_SWDH_BIT) 1830 #define DMAC_DCCSR_SWDH_8 (1 << DMAC_DCCSR_SWDH_BIT) 1831 #define DMAC_DCCSR_SWDH_16 (2 << DMAC_DCCSR_SWDH_BIT) 1832 #define DMAC_DCCSR_DWDH_BIT 12 1833 #define DMAC_DCCSR_DWDH_MASK (0x03 << DMAC_DCCSR_DWDH_BIT) 1834 #define DMAC_DCCSR_DWDH_32 (0 << DMAC_DCCSR_DWDH_BIT) 1835 #define DMAC_DCCSR_DWDH_8 (1 << DMAC_DCCSR_DWDH_BIT) 1836 #define DMAC_DCCSR_DWDH_16 (2 << DMAC_DCCSR_DWDH_BIT) 1837 #define DMAC_DCCSR_DS_BIT 8 1838 #define DMAC_DCCSR_DS_MASK (0x07 << DMAC_DCCSR_DS_BIT) 1839 #define DMAC_DCCSR_DS_32b (0 << DMAC_DCCSR_DS_BIT) 1840 #define DMAC_DCCSR_DS_8b (1 << DMAC_DCCSR_DS_BIT) 1841 #define DMAC_DCCSR_DS_16b (2 << DMAC_DCCSR_DS_BIT) 1842 #define DMAC_DCCSR_DS_16B (3 << DMAC_DCCSR_DS_BIT) 1843 #define DMAC_DCCSR_DS_32B (4 << DMAC_DCCSR_DS_BIT) 1844 #define DMAC_DCCSR_TM (1 << 7) 1845 #define DMAC_DCCSR_AR (1 << 4) 1846 #define DMAC_DCCSR_TC (1 << 3) 1847 #define DMAC_DCCSR_HLT (1 << 2) 1848 #define DMAC_DCCSR_TCIE (1 << 1) 1849 #define DMAC_DCCSR_CHDE (1 << 0) 1850 1851 #define DMAC_DMAIPR_CINT_BIT 8 1852 #define DMAC_DMAIPR_CINT_MASK (0xff << DMAC_DMAIPR_CINT_BIT) 1853 1854 #define DMAC_DMACR_PR_BIT 8 1855 #define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT) 1856 #define DMAC_DMACR_PR_01234567 (0 << DMAC_DMACR_PR_BIT) 1857 #define DMAC_DMACR_PR_02314675 (1 << DMAC_DMACR_PR_BIT) 1858 #define DMAC_DMACR_PR_20136457 (2 << DMAC_DMACR_PR_BIT) 1859 #define DMAC_DMACR_PR_ROUNDROBIN (3 << DMAC_DMACR_PR_BIT) 1860 #define DMAC_DMACR_HTR (1 << 3) 1861 #define DMAC_DMACR_AER (1 << 2) 1862 #define DMAC_DMACR_DME (1 << 0) 1863 1864 #define IRQ_DMA_0 32 1865 #define NUM_DMA 6 1866 1867 1868 /************************************************************************* 1869 * AIC 1870 *************************************************************************/ 1871 #define AIC_FR (AIC_BASE + 0x000) 1872 #define AIC_CR (AIC_BASE + 0x004) 1873 #define AIC_ACCR1 (AIC_BASE + 0x008) 1874 #define AIC_ACCR2 (AIC_BASE + 0x00C) 1875 #define AIC_I2SCR (AIC_BASE + 0x010) 1876 #define AIC_SR (AIC_BASE + 0x014) 1877 #define AIC_ACSR (AIC_BASE + 0x018) 1878 #define AIC_I2SSR (AIC_BASE + 0x01C) 1879 #define AIC_ACCAR (AIC_BASE + 0x020) 1880 #define AIC_ACCDR (AIC_BASE + 0x024) 1881 #define AIC_ACSAR (AIC_BASE + 0x028) 1882 #define AIC_ACSDR (AIC_BASE + 0x02C) 1883 #define AIC_I2SDIV (AIC_BASE + 0x030) 1884 #define AIC_DR (AIC_BASE + 0x034) 1885 1886 #define REG_AIC_FR REG32(AIC_FR) 1887 #define REG_AIC_CR REG32(AIC_CR) 1888 #define REG_AIC_ACCR1 REG32(AIC_ACCR1) 1889 #define REG_AIC_ACCR2 REG32(AIC_ACCR2) 1890 #define REG_AIC_I2SCR REG32(AIC_I2SCR) 1891 #define REG_AIC_SR REG32(AIC_SR) 1892 #define REG_AIC_ACSR REG32(AIC_ACSR) 1893 #define REG_AIC_I2SSR REG32(AIC_I2SSR) 1894 #define REG_AIC_ACCAR REG32(AIC_ACCAR) 1895 #define REG_AIC_ACCDR REG32(AIC_ACCDR) 1896 #define REG_AIC_ACSAR REG32(AIC_ACSAR) 1897 #define REG_AIC_ACSDR REG32(AIC_ACSDR) 1898 #define REG_AIC_I2SDIV REG32(AIC_I2SDIV) 1899 #define REG_AIC_DR REG32(AIC_DR) 1900 1901 /* AIC Controller Configuration Register (AIC_FR) */ 1902 1903 #define AIC_FR_RFTH_BIT 12 1904 #define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT) 1905 #define AIC_FR_TFTH_BIT 8 1906 #define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT) 1907 #define AIC_FR_AUSEL (1 << 4) 1908 #define AIC_FR_RST (1 << 3) 1909 #define AIC_FR_BCKD (1 << 2) 1910 #define AIC_FR_SYNCD (1 << 1) 1911 #define AIC_FR_ENB (1 << 0) 1912 1913 /* AIC Controller Common Control Register (AIC_CR) */ 1914 1915 #define AIC_CR_RDMS (1 << 15) 1916 #define AIC_CR_TDMS (1 << 14) 1917 #define AIC_CR_FLUSH (1 << 8) 1918 #define AIC_CR_EROR (1 << 6) 1919 #define AIC_CR_ETUR (1 << 5) 1920 #define AIC_CR_ERFS (1 << 4) 1921 #define AIC_CR_ETFS (1 << 3) 1922 #define AIC_CR_ENLBF (1 << 2) 1923 #define AIC_CR_ERPL (1 << 1) 1924 #define AIC_CR_EREC (1 << 0) 1925 1926 /* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */ 1927 1928 #define AIC_ACCR1_RS_BIT 16 1929 #define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT) 1930 #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */ 1931 #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */ 1932 #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */ 1933 #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit */ 1934 #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit */ 1935 #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit */ 1936 #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit */ 1937 #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */ 1938 #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit */ 1939 #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit */ 1940 #define AIC_ACCR1_XS_BIT 0 1941 #define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT) 1942 #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */ 1943 #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */ 1944 #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */ 1945 #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit */ 1946 #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit */ 1947 #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit */ 1948 #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit */ 1949 #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */ 1950 #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit */ 1951 #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit */ 1952 1953 /* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */ 1954 1955 #define AIC_ACCR2_ERSTO (1 << 18) 1956 #define AIC_ACCR2_ESADR (1 << 17) 1957 #define AIC_ACCR2_ECADT (1 << 16) 1958 #define AIC_ACCR2_OASS_BIT 8 1959 #define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT) 1960 #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */ 1961 #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */ 1962 #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */ 1963 #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */ 1964 #define AIC_ACCR2_IASS_BIT 6 1965 #define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT) 1966 #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */ 1967 #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */ 1968 #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */ 1969 #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */ 1970 #define AIC_ACCR2_SO (1 << 3) 1971 #define AIC_ACCR2_SR (1 << 2) 1972 #define AIC_ACCR2_SS (1 << 1) 1973 #define AIC_ACCR2_SA (1 << 0) 1974 1975 /* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */ 1976 1977 #define AIC_I2SCR_STPBK (1 << 12) 1978 #define AIC_I2SCR_WL_BIT 1 1979 #define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT) 1980 #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */ 1981 #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */ 1982 #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */ 1983 #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */ 1984 #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */ 1985 #define AIC_I2SCR_AMSL (1 << 0) 1986 1987 /* AIC Controller FIFO Status Register (AIC_SR) */ 1988 1989 #define AIC_SR_RFL_BIT 24 1990 #define AIC_SR_RFL_MASK (0x1f << AIC_SR_RFL_BIT) 1991 #define AIC_SR_TFL_BIT 8 1992 #define AIC_SR_TFL_MASK (0x1f << AIC_SR_TFL_BIT) 1993 #define AIC_SR_ROR (1 << 6) 1994 #define AIC_SR_TUR (1 << 5) 1995 #define AIC_SR_RFS (1 << 4) 1996 #define AIC_SR_TFS (1 << 3) 1997 1998 /* AIC Controller AC-link Status Register (AIC_ACSR) */ 1999 2000 #define AIC_ACSR_CRDY (1 << 20) 2001 #define AIC_ACSR_CLPM (1 << 19) 2002 #define AIC_ACSR_RSTO (1 << 18) 2003 #define AIC_ACSR_SADR (1 << 17) 2004 #define AIC_ACSR_CADT (1 << 16) 2005 2006 /* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */ 2007 2008 #define AIC_I2SSR_BSY (1 << 2) 2009 2010 /* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */ 2011 2012 #define AIC_ACCAR_CAR_BIT 0 2013 #define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT) 2014 2015 /* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */ 2016 2017 #define AIC_ACCDR_CDR_BIT 0 2018 #define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT) 2019 2020 /* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */ 2021 2022 #define AIC_ACSAR_SAR_BIT 0 2023 #define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT) 2024 2025 /* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */ 2026 2027 #define AIC_ACSDR_SDR_BIT 0 2028 #define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT) 2029 2030 /* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */ 2031 2032 #define AIC_I2SDIV_DIV_BIT 0 2033 #define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT) 2034 #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */ 2035 #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */ 2036 #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */ 2037 #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */ 2038 #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */ 2039 #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */ 2040 2041 2042 2043 2044 /************************************************************************* 2045 * LCD 2046 *************************************************************************/ 2047 2048 /* Register definitions with absolute positioning have been removed. */ 2049 2050 #define LCD_CFG_PDW_BIT 4 2051 #define LCD_CFG_PDW_MASK (0x03 << LCD_DEV_PDW_BIT) 2052 #define LCD_CFG_PDW_1 (0 << LCD_DEV_PDW_BIT) 2053 #define LCD_CFG_PDW_2 (1 << LCD_DEV_PDW_BIT) 2054 #define LCD_CFG_PDW_4 (2 << LCD_DEV_PDW_BIT) 2055 #define LCD_CFG_PDW_8 (3 << LCD_DEV_PDW_BIT) 2056 #define LCD_CFG_MODE_BIT 0 2057 #define LCD_CFG_MODE_MASK (0x0f << LCD_DEV_MODE_BIT) 2058 #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_DEV_MODE_BIT) 2059 #define LCD_CFG_MODE_SHARP_HR (1 << LCD_DEV_MODE_BIT) 2060 #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_DEV_MODE_BIT) 2061 #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_DEV_MODE_BIT) 2062 #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_DEV_MODE_BIT) 2063 #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_DEV_MODE_BIT) 2064 #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_DEV_MODE_BIT) 2065 #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_DEV_MODE_BIT) 2066 #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_DEV_MODE_BIT) 2067 #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_DEV_MODE_BIT) 2068 2069 #define LCD_VSYNC_VPS_BIT 16 2070 #define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) 2071 #define LCD_VSYNC_VPE_BIT 0 2072 #define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) 2073 2074 #define LCD_HSYNC_HPS_BIT 16 2075 #define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) 2076 #define LCD_HSYNC_HPE_BIT 0 2077 #define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) 2078 2079 #define LCD_VAT_HT_BIT 16 2080 #define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) 2081 #define LCD_VAT_VT_BIT 0 2082 #define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) 2083 2084 #define LCD_DAH_HDS_BIT 16 2085 #define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) 2086 #define LCD_DAH_HDE_BIT 0 2087 #define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) 2088 2089 #define LCD_DAV_VDS_BIT 16 2090 #define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) 2091 #define LCD_DAV_VDE_BIT 0 2092 #define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) 2093 2094 #define LCD_CTRL_BST_BIT 28 2095 #define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) 2096 #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) 2097 #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) 2098 #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) 2099 #define LCD_CTRL_RGB555 (1 << 27) 2100 #define LCD_CTRL_OFUP (1 << 26) 2101 #define LCD_CTRL_FRC_BIT 24 2102 #define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) 2103 #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) 2104 #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) 2105 #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) 2106 #define LCD_CTRL_PDD_BIT 16 2107 #define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) 2108 #define LCD_CTRL_EOFM (1 << 13) 2109 #define LCD_CTRL_SOFM (1 << 12) 2110 #define LCD_CTRL_OFUM (1 << 11) 2111 #define LCD_CTRL_IFUM0 (1 << 10) 2112 #define LCD_CTRL_IFUM1 (1 << 9) 2113 #define LCD_CTRL_LDDM (1 << 8) 2114 #define LCD_CTRL_QDM (1 << 7) 2115 #define LCD_CTRL_BEDN (1 << 6) 2116 #define LCD_CTRL_PEDN (1 << 5) 2117 #define LCD_CTRL_DIS (1 << 4) 2118 #define LCD_CTRL_ENA (1 << 3) 2119 #define LCD_CTRL_BPP_BIT 0 2120 #define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) 2121 #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) 2122 #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) 2123 #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) 2124 #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) 2125 #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) 2126 2127 #define LCD_STATE_QD (1 << 7) 2128 #define LCD_STATE_EOF (1 << 5) 2129 #define LCD_STATE_SOF (1 << 4) 2130 #define LCD_STATE_OFU (1 << 3) 2131 #define LCD_STATE_IFU0 (1 << 2) 2132 #define LCD_STATE_IFU1 (1 << 1) 2133 #define LCD_STATE_LDD (1 << 0) 2134 2135 #define LCD_CMD_SOFINT (1 << 31) 2136 #define LCD_CMD_EOFINT (1 << 30) 2137 #define LCD_CMD_PAL (1 << 28) 2138 #define LCD_CMD_LEN_BIT 0 2139 #define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT) 2140 2141 2142 2143 2144 /************************************************************************* 2145 * DES 2146 *************************************************************************/ 2147 #define DES_CR1 (DES_BASE + 0x000) 2148 #define DES_CR2 (DES_BASE + 0x004) 2149 #define DES_SR (DES_BASE + 0x008) 2150 #define DES_K1L (DES_BASE + 0x010) 2151 #define DES_K1R (DES_BASE + 0x014) 2152 #define DES_K2L (DES_BASE + 0x018) 2153 #define DES_K2R (DES_BASE + 0x01C) 2154 #define DES_K3L (DES_BASE + 0x020) 2155 #define DES_K3R (DES_BASE + 0x024) 2156 #define DES_IVL (DES_BASE + 0x028) 2157 #define DES_IVR (DES_BASE + 0x02C) 2158 #define DES_DIN (DES_BASE + 0x030) 2159 #define DES_DOUT (DES_BASE + 0x034) 2160 2161 #define REG_DES_CR1 REG32(DES_CR1) 2162 #define REG_DES_CR2 REG32(DES_CR2) 2163 #define REG_DES_SR REG32(DES_SR) 2164 #define REG_DES_K1L REG32(DES_K1L) 2165 #define REG_DES_K1R REG32(DES_K1R) 2166 #define REG_DES_K2L REG32(DES_K2L) 2167 #define REG_DES_K2R REG32(DES_K2R) 2168 #define REG_DES_K3L REG32(DES_K3L) 2169 #define REG_DES_K3R REG32(DES_K3R) 2170 #define REG_DES_IVL REG32(DES_IVL) 2171 #define REG_DES_IVR REG32(DES_IVR) 2172 #define REG_DES_DIN REG32(DES_DIN) 2173 #define REG_DES_DOUT REG32(DES_DOUT) 2174 2175 /* DES Control Register 1 (DES_CR1) */ 2176 2177 #define DES_CR1_EN (1 << 0) 2178 2179 /* DES Control Register 2 (DES_CR2) */ 2180 2181 #define DES_CR2_ENDEC (1 << 3) 2182 #define DES_CR2_MODE (1 << 2) 2183 #define DES_CR2_ALG (1 << 1) 2184 #define DES_CR2_DMAE (1 << 0) 2185 2186 /* DES State Register (DES_SR) */ 2187 2188 #define DES_SR_IN_FULL (1 << 5) 2189 #define DES_SR_IN_LHF (1 << 4) 2190 #define DES_SR_IN_EMPTY (1 << 3) 2191 #define DES_SR_OUT_FULL (1 << 2) 2192 #define DES_SR_OUT_GHF (1 << 1) 2193 #define DES_SR_OUT_EMPTY (1 << 0) 2194 2195 2196 2197 2198 /************************************************************************* 2199 * CPM 2200 *************************************************************************/ 2201 #define CPM_CFCR (CPM_BASE+0x00) 2202 #define CPM_PLCR1 (CPM_BASE+0x10) 2203 #define CPM_OCR (CPM_BASE+0x1c) 2204 #define CPM_CFCR2 (CPM_BASE+0x60) 2205 #define CPM_LPCR (CPM_BASE+0x04) 2206 #define CPM_RSTR (CPM_BASE+0x08) 2207 #define CPM_MSCR (CPM_BASE+0x20) 2208 #define CPM_SCR (CPM_BASE+0x24) 2209 #define CPM_WRER (CPM_BASE+0x28) 2210 #define CPM_WFER (CPM_BASE+0x2c) 2211 #define CPM_WER (CPM_BASE+0x30) 2212 #define CPM_WSR (CPM_BASE+0x34) 2213 #define CPM_GSR0 (CPM_BASE+0x38) 2214 #define CPM_GSR1 (CPM_BASE+0x3c) 2215 #define CPM_GSR2 (CPM_BASE+0x40) 2216 #define CPM_SPR (CPM_BASE+0x44) 2217 #define CPM_GSR3 (CPM_BASE+0x48) 2218 2219 #define REG_CPM_CFCR REG32(CPM_CFCR) 2220 #define REG_CPM_PLCR1 REG32(CPM_PLCR1) 2221 #define REG_CPM_OCR REG32(CPM_OCR) 2222 #define REG_CPM_CFCR2 REG32(CPM_CFCR2) 2223 #define REG_CPM_LPCR REG32(CPM_LPCR) 2224 #define REG_CPM_RSTR REG32(CPM_RSTR) 2225 #define REG_CPM_MSCR REG32(CPM_MSCR) 2226 #define REG_CPM_SCR REG32(CPM_SCR) 2227 #define REG_CPM_WRER REG32(CPM_WRER) 2228 #define REG_CPM_WFER REG32(CPM_WFER) 2229 #define REG_CPM_WER REG32(CPM_WER) 2230 #define REG_CPM_WSR REG32(CPM_WSR) 2231 #define REG_CPM_GSR0 REG32(CPM_GSR0) 2232 #define REG_CPM_GSR1 REG32(CPM_GSR1) 2233 #define REG_CPM_GSR2 REG32(CPM_GSR2) 2234 #define REG_CPM_SPR REG32(CPM_SPR) 2235 #define REG_CPM_GSR3 REG32(CPM_GSR3) 2236 2237 #define CPM_CFCR_SSI (1 << 31) 2238 #define CPM_CFCR_LCD (1 << 30) 2239 #define CPM_CFCR_I2S (1 << 29) 2240 #define CPM_CFCR_UCS (1 << 28) 2241 #define CPM_CFCR_UFR_BIT 25 2242 #define CPM_CFCR_UFR_MASK (0x07 << CPM_CFCR_UFR_BIT) 2243 #define CPM_CFCR_MSC (1 << 24) 2244 #define CPM_CFCR_CKOEN2 (1 << 23) 2245 #define CPM_CFCR_CKOEN1 (1 << 22) 2246 #define CPM_CFCR_UPE (1 << 20) 2247 #define CPM_CFCR_MFR_BIT 16 2248 #define CPM_CFCR_MFR_MASK (0x0f << CPM_CFCR_MFR_BIT) 2249 #define CFCR_MDIV_1 (0 << CPM_CFCR_MFR_BIT) 2250 #define CFCR_MDIV_2 (1 << CPM_CFCR_MFR_BIT) 2251 #define CFCR_MDIV_3 (2 << CPM_CFCR_MFR_BIT) 2252 #define CFCR_MDIV_4 (3 << CPM_CFCR_MFR_BIT) 2253 #define CFCR_MDIV_6 (4 << CPM_CFCR_MFR_BIT) 2254 #define CFCR_MDIV_8 (5 << CPM_CFCR_MFR_BIT) 2255 #define CFCR_MDIV_12 (6 << CPM_CFCR_MFR_BIT) 2256 #define CFCR_MDIV_16 (7 << CPM_CFCR_MFR_BIT) 2257 #define CFCR_MDIV_24 (8 << CPM_CFCR_MFR_BIT) 2258 #define CFCR_MDIV_32 (9 << CPM_CFCR_MFR_BIT) 2259 #define CPM_CFCR_LFR_BIT 12 2260 #define CPM_CFCR_LFR_MASK (0x0f << CPM_CFCR_LFR_BIT) 2261 #define CPM_CFCR_PFR_BIT 8 2262 #define CPM_CFCR_PFR_MASK (0x0f << CPM_CFCR_PFR_BIT) 2263 #define CFCR_PDIV_1 (0 << CPM_CFCR_PFR_BIT) 2264 #define CFCR_PDIV_2 (1 << CPM_CFCR_PFR_BIT) 2265 #define CFCR_PDIV_3 (2 << CPM_CFCR_PFR_BIT) 2266 #define CFCR_PDIV_4 (3 << CPM_CFCR_PFR_BIT) 2267 #define CFCR_PDIV_6 (4 << CPM_CFCR_PFR_BIT) 2268 #define CFCR_PDIV_8 (5 << CPM_CFCR_PFR_BIT) 2269 #define CFCR_PDIV_12 (6 << CPM_CFCR_PFR_BIT) 2270 #define CFCR_PDIV_16 (7 << CPM_CFCR_PFR_BIT) 2271 #define CFCR_PDIV_24 (8 << CPM_CFCR_PFR_BIT) 2272 #define CFCR_PDIV_32 (9 << CPM_CFCR_PFR_BIT) 2273 #define CPM_CFCR_SFR_BIT 4 2274 #define CPM_CFCR_SFR_MASK (0x0f << CPM_CFCR_SFR_BIT) 2275 #define CFCR_SDIV_1 (0 << CPM_CFCR_SFR_BIT) 2276 #define CFCR_SDIV_2 (1 << CPM_CFCR_SFR_BIT) 2277 #define CFCR_SDIV_3 (2 << CPM_CFCR_SFR_BIT) 2278 #define CFCR_SDIV_4 (3 << CPM_CFCR_SFR_BIT) 2279 #define CFCR_SDIV_6 (4 << CPM_CFCR_SFR_BIT) 2280 #define CFCR_SDIV_8 (5 << CPM_CFCR_SFR_BIT) 2281 #define CFCR_SDIV_12 (6 << CPM_CFCR_SFR_BIT) 2282 #define CFCR_SDIV_16 (7 << CPM_CFCR_SFR_BIT) 2283 #define CFCR_SDIV_24 (8 << CPM_CFCR_SFR_BIT) 2284 #define CFCR_SDIV_32 (9 << CPM_CFCR_SFR_BIT) 2285 #define CPM_CFCR_IFR_BIT 0 2286 #define CPM_CFCR_IFR_MASK (0x0f << CPM_CFCR_IFR_BIT) 2287 #define CFCR_IDIV_1 (0 << CPM_CFCR_IFR_BIT) 2288 #define CFCR_IDIV_2 (1 << CPM_CFCR_IFR_BIT) 2289 #define CFCR_IDIV_3 (2 << CPM_CFCR_IFR_BIT) 2290 #define CFCR_IDIV_4 (3 << CPM_CFCR_IFR_BIT) 2291 #define CFCR_IDIV_6 (4 << CPM_CFCR_IFR_BIT) 2292 #define CFCR_IDIV_8 (5 << CPM_CFCR_IFR_BIT) 2293 #define CFCR_IDIV_12 (6 << CPM_CFCR_IFR_BIT) 2294 #define CFCR_IDIV_16 (7 << CPM_CFCR_IFR_BIT) 2295 #define CFCR_IDIV_24 (8 << CPM_CFCR_IFR_BIT) 2296 #define CFCR_IDIV_32 (9 << CPM_CFCR_IFR_BIT) 2297 2298 #define CPM_PLCR1_PLL1FD_BIT 23 2299 #define CPM_PLCR1_PLL1FD_MASK (0x1ff << CPM_PLCR1_PLL1FD_BIT) 2300 #define CPM_PLCR1_PLL1RD_BIT 18 2301 #define CPM_PLCR1_PLL1RD_MASK (0x1f << CPM_PLCR1_PLL1RD_BIT) 2302 #define CPM_PLCR1_PLL1OD_BIT 16 2303 #define CPM_PLCR1_PLL1OD_MASK (0x03 << CPM_PLCR1_PLL1OD_BIT) 2304 #define CPM_PLCR1_PLL1S (1 << 10) 2305 #define CPM_PLCR1_PLL1BP (1 << 9) 2306 #define CPM_PLCR1_PLL1EN (1 << 8) 2307 #define CPM_PLCR1_PLL1ST_BIT 0 2308 #define CPM_PLCR1_PLL1ST_MASK (0xff << CPM_PLCR1_PLL1ST_BIT) 2309 2310 #define CPM_OCR_O1ST_BIT 16 2311 #define CPM_OCR_O1ST_MASK (0xff << CPM_OCR_O1ST_BIT) 2312 #define CPM_OCR_EXT_RTC_CLK (1<<8) 2313 #define CPM_OCR_SUSPEND_PHY1 (1<<7) 2314 #define CPM_OCR_SUSPEND_PHY0 (1<<6) 2315 2316 #define CPM_CFCR2_PXFR_BIT 0 2317 #define CPM_CFCR2_PXFR_MASK (0x1ff << CPM_CFCR2_PXFR_BIT) 2318 2319 #define CPM_LPCR_DUTY_BIT 3 2320 #define CPM_LPCR_DUTY_MASK (0x1f << CPM_LPCR_DUTY_BIT) 2321 #define CPM_LPCR_DOZE (1 << 2) 2322 #define CPM_LPCR_LPM_BIT 0 2323 #define CPM_LPCR_LPM_MASK (0x03 << CPM_LPCR_LPM_BIT) 2324 #define CPM_LPCR_LPM_IDLE (0 << CPM_LPCR_LPM_BIT) 2325 #define CPM_LPCR_LPM_SLEEP (1 << CPM_LPCR_LPM_BIT) 2326 #define CPM_LPCR_LPM_HIBERNATE (2 << CPM_LPCR_LPM_BIT) 2327 2328 #define CPM_RSTR_SR (1 << 2) 2329 #define CPM_RSTR_WR (1 << 1) 2330 #define CPM_RSTR_HR (1 << 0) 2331 2332 #define CPM_MSCR_MSTP_BIT 0 2333 #define CPM_MSCR_MSTP_MASK (0x1ffffff << CPM_MSCR_MSTP_BIT) 2334 #define CPM_MSCR_MSTP_UART0 0 2335 #define CPM_MSCR_MSTP_UART1 1 2336 #define CPM_MSCR_MSTP_UART2 2 2337 #define CPM_MSCR_MSTP_OST 3 2338 #define CPM_MSCR_MSTP_DMAC 5 2339 #define CPM_MSCR_MSTP_UHC 6 2340 #define CPM_MSCR_MSTP_LCD 7 2341 #define CPM_MSCR_MSTP_I2C 8 2342 #define CPM_MSCR_MSTP_AICPCLK 9 2343 #define CPM_MSCR_MSTP_PWM0 10 2344 #define CPM_MSCR_MSTP_PWM1 11 2345 #define CPM_MSCR_MSTP_SSI 12 2346 #define CPM_MSCR_MSTP_MSC 13 2347 #define CPM_MSCR_MSTP_SCC 14 2348 #define CPM_MSCR_MSTP_AICBCLK 18 2349 #define CPM_MSCR_MSTP_UART3 20 2350 #define CPM_MSCR_MSTP_ETH 21 2351 #define CPM_MSCR_MSTP_KBC 22 2352 #define CPM_MSCR_MSTP_CIM 23 2353 #define CPM_MSCR_MSTP_UDC 24 2354 #define CPM_MSCR_MSTP_UPRT 25 2355 2356 #define CPM_SCR_O1SE (1 << 4) 2357 #define CPM_SCR_HGP (1 << 3) 2358 #define CPM_SCR_HZP (1 << 2) 2359 #define CPM_SCR_HZM (1 << 1) 2360 2361 #define CPM_WRER_RE_BIT 0 2362 #define CPM_WRER_RE_MASK (0xffff << CPM_WRER_RE_BIT) 2363 2364 #define CPM_WFER_FE_BIT 0 2365 #define CPM_WFER_FE_MASK (0xffff << CPM_WFER_FE_BIT) 2366 2367 #define CPM_WER_WERTC (1 << 31) 2368 #define CPM_WER_WEETH (1 << 30) 2369 #define CPM_WER_WE_BIT 0 2370 #define CPM_WER_WE_MASK (0xffff << CPM_WER_WE_BIT) 2371 2372 #define CPM_WSR_WSRTC (1 << 31) 2373 #define CPM_WSR_WSETH (1 << 30) 2374 #define CPM_WSR_WS_BIT 0 2375 #define CPM_WSR_WS_MASK (0xffff << CPM_WSR_WS_BIT) 2376 2377 2378 2379 2380 /************************************************************************* 2381 * SSI 2382 *************************************************************************/ 2383 #define SSI_DR (SSI_BASE + 0x000) 2384 #define SSI_CR0 (SSI_BASE + 0x004) 2385 #define SSI_CR1 (SSI_BASE + 0x008) 2386 #define SSI_SR (SSI_BASE + 0x00C) 2387 #define SSI_ITR (SSI_BASE + 0x010) 2388 #define SSI_ICR (SSI_BASE + 0x014) 2389 #define SSI_GR (SSI_BASE + 0x018) 2390 2391 #define REG_SSI_DR REG32(SSI_DR) 2392 #define REG_SSI_CR0 REG16(SSI_CR0) 2393 #define REG_SSI_CR1 REG32(SSI_CR1) 2394 #define REG_SSI_SR REG32(SSI_SR) 2395 #define REG_SSI_ITR REG16(SSI_ITR) 2396 #define REG_SSI_ICR REG8(SSI_ICR) 2397 #define REG_SSI_GR REG16(SSI_GR) 2398 2399 /* SSI Data Register (SSI_DR) */ 2400 2401 #define SSI_DR_GPC_BIT 0 2402 #define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT) 2403 2404 /* SSI Control Register 0 (SSI_CR0) */ 2405 2406 #define SSI_CR0_SSIE (1 << 15) 2407 #define SSI_CR0_TIE (1 << 14) 2408 #define SSI_CR0_RIE (1 << 13) 2409 #define SSI_CR0_TEIE (1 << 12) 2410 #define SSI_CR0_REIE (1 << 11) 2411 #define SSI_CR0_LOOP (1 << 10) 2412 #define SSI_CR0_RFINE (1 << 9) 2413 #define SSI_CR0_RFINC (1 << 8) 2414 #define SSI_CR0_FSEL (1 << 6) 2415 #define SSI_CR0_TFLUSH (1 << 2) 2416 #define SSI_CR0_RFLUSH (1 << 1) 2417 #define SSI_CR0_DISREV (1 << 0) 2418 2419 /* SSI Control Register 1 (SSI_CR1) */ 2420 2421 #define SSI_CR1_FRMHL_BIT 30 2422 #define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT) 2423 #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */ 2424 #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */ 2425 #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */ 2426 #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */ 2427 #define SSI_CR1_TFVCK_BIT 28 2428 #define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT) 2429 #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT) 2430 #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT) 2431 #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT) 2432 #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT) 2433 #define SSI_CR1_TCKFI_BIT 26 2434 #define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT) 2435 #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT) 2436 #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT) 2437 #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT) 2438 #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT) 2439 #define SSI_CR1_LFST (1 << 25) 2440 #define SSI_CR1_ITFRM (1 << 24) 2441 #define SSI_CR1_UNFIN (1 << 23) 2442 #define SSI_CR1_MULTS (1 << 22) 2443 #define SSI_CR1_FMAT_BIT 20 2444 #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT) 2445 #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola????s SPI format */ 2446 #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */ 2447 #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */ 2448 #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */ 2449 #define SSI_CR1_MCOM_BIT 12 2450 #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT) 2451 #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */ 2452 #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */ 2453 #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */ 2454 #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */ 2455 #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */ 2456 #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */ 2457 #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */ 2458 #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */ 2459 #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */ 2460 #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */ 2461 #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */ 2462 #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */ 2463 #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */ 2464 #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */ 2465 #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */ 2466 #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */ 2467 #define SSI_CR1_TTRG_BIT 10 2468 #define SSI_CR1_TTRG_MASK (0x3 << SSI_CR1_TTRG_BIT) 2469 #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)/* Less than or equal to 1 */ 2470 #define SSI_CR1_TTRG_4 (1 << SSI_CR1_TTRG_BIT) /* Less than or equal to 4 */ 2471 #define SSI_CR1_TTRG_8 (2 << SSI_CR1_TTRG_BIT) /* Less than or equal to 8 */ 2472 #define SSI_CR1_TTRG_14 (3 << SSI_CR1_TTRG_BIT) /* Less than or equal to 14 */ 2473 #define SSI_CR1_RTRG_BIT 8 2474 #define SSI_CR1_RTRG_MASK (0x3 << SSI_CR1_RTRG_BIT) 2475 #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) /* More than or equal to 1 */ 2476 #define SSI_CR1_RTRG_4 (1 << SSI_CR1_RTRG_BIT) /* More than or equal to 4 */ 2477 #define SSI_CR1_RTRG_8 (2 << SSI_CR1_RTRG_BIT) /* More than or equal to 8 */ 2478 #define SSI_CR1_RTRG_14 (3 << SSI_CR1_RTRG_BIT) /* More than or equal to 14 */ 2479 #define SSI_CR1_FLEN_BIT 4 2480 #define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT) 2481 #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT) 2482 #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT) 2483 #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT) 2484 #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT) 2485 #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT) 2486 #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT) 2487 #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT) 2488 #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT) 2489 #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT) 2490 #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT) 2491 #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT) 2492 #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT) 2493 #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT) 2494 #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT) 2495 #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT) 2496 #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT) 2497 #define SSI_CR1_PHA (1 << 1) 2498 #define SSI_CR1_POL (1 << 0) 2499 2500 /* SSI Status Register (SSI_SR) */ 2501 2502 #define SSI_SR_TFIFONUM_BIT 13 2503 #define SSI_SR_TFIFONUM_MASK (0x1f << SSI_SR_TFIFONUM_BIT) 2504 #define SSI_SR_RFIFONUM_BIT 8 2505 #define SSI_SR_RFIFONUM_MASK (0x1f << SSI_SR_RFIFONUM_BIT) 2506 #define SSI_SR_END (1 << 7) 2507 #define SSI_SR_BUSY (1 << 6) 2508 #define SSI_SR_TFF (1 << 5) 2509 #define SSI_SR_RFE (1 << 4) 2510 #define SSI_SR_TFHE (1 << 3) 2511 #define SSI_SR_RFHF (1 << 2) 2512 #define SSI_SR_UNDR (1 << 1) 2513 #define SSI_SR_OVER (1 << 0) 2514 2515 /* SSI Interval Time Control Register (SSI_ITR) */ 2516 2517 #define SSI_ITR_CNTCLK (1 << 15) 2518 #define SSI_ITR_IVLTM_BIT 0 2519 #define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT) 2520 2521 #ifndef __ASSEMBLY__ 2522 2523 /*************************************************************************** 2524 * MSC 2525 ***************************************************************************/ 2526 2527 #define __msc_start_op() \ 2528 ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START ) 2529 2530 #define __msc_set_resto(to) ( REG_MSC_RESTO = to ) 2531 #define __msc_set_rdto(to) ( REG_MSC_RDTO = to ) 2532 #define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd ) 2533 #define __msc_set_arg(arg) ( REG_MSC_ARG = arg ) 2534 #define __msc_set_nob(nob) ( REG_MSC_NOB = nob ) 2535 #define __msc_get_nob() ( REG_MSC_NOB ) 2536 #define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len ) 2537 #define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat ) 2538 #define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT ) 2539 #define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT ) 2540 2541 #define __msc_set_cmdat_bus_width1() \ 2542 do { \ 2543 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ 2544 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \ 2545 } while(0) 2546 2547 #define __msc_set_cmdat_bus_width4() \ 2548 do { \ 2549 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ 2550 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \ 2551 } while(0) 2552 2553 #define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN ) 2554 #define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT ) 2555 #define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY ) 2556 #define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK ) 2557 #define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK ) 2558 #define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ ) 2559 #define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ ) 2560 #define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN ) 2561 2562 /* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */ 2563 #define __msc_set_cmdat_res_format(r) \ 2564 do { \ 2565 REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ 2566 REG_MSC_CMDAT |= (r); \ 2567 } while(0) 2568 2569 #define __msc_clear_cmdat() \ 2570 REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ 2571 MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ 2572 MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK ) 2573 2574 #define __msc_get_imask() ( REG_MSC_IMASK ) 2575 #define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff ) 2576 #define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 ) 2577 #define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ ) 2578 #define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ ) 2579 #define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ ) 2580 #define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ ) 2581 #define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES ) 2582 #define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES ) 2583 #define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE ) 2584 #define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE ) 2585 #define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE ) 2586 #define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE ) 2587 2588 /* n=1,2,4,8,16,32,64,128 */ 2589 #define __msc_set_clkrt_div(n) \ 2590 do { \ 2591 REG_MSC_CLKRT &= ~MSC_CLKRT_CLK_RATE_MASK; \ 2592 REG_MSC_CLKRT |= MSC_CLKRT_CLK_RATE_DIV_##n; \ 2593 } while(0) 2594 2595 #define __msc_get_ireg() ( REG_MSC_IREG ) 2596 #define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ ) 2597 #define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ ) 2598 #define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES ) 2599 #define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE ) 2600 #define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE ) 2601 #define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES ) 2602 #define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE ) 2603 #define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE ) 2604 2605 #define __msc_get_stat() ( REG_MSC_STAT ) 2606 #define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0) 2607 #define __msc_stat_crc_err() \ 2608 ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) ) 2609 #define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR ) 2610 #define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR ) 2611 #define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES ) 2612 #define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES ) 2613 #define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ ) 2614 2615 #define __msc_rd_resfifo() ( REG_MSC_RES ) 2616 #define __msc_rd_rxfifo() ( REG_MSC_RXFIFO ) 2617 #define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v ) 2618 2619 #define __msc_reset() \ 2620 do { \ 2621 REG_MSC_STRPCL = MSC_STRPCL_RESET; \ 2622 while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \ 2623 } while (0) 2624 2625 #define __msc_start_clk() \ 2626 do { \ 2627 REG_MSC_STRPCL &= ~MSC_STRPCL_CLOCK_CONTROL_MASK; \ 2628 REG_MSC_STRPCL |= MSC_STRPCL_CLOCK_CONTROL_START; \ 2629 } while (0) 2630 2631 #define __msc_stop_clk() \ 2632 do { \ 2633 REG_MSC_STRPCL &= ~MSC_STRPCL_CLOCK_CONTROL_MASK; \ 2634 REG_MSC_STRPCL |= MSC_STRPCL_CLOCK_CONTROL_STOP; \ 2635 } while (0) 2636 2637 #define MMC_CLK 19169200 2638 #define SD_CLK 24576000 2639 2640 /* msc_clk should little than pclk and little than clk retrieve from card */ 2641 #define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \ 2642 do { \ 2643 unsigned int rate, pclk, i; \ 2644 pclk = dev_clk; \ 2645 rate = type?SD_CLK:MMC_CLK; \ 2646 if (msc_clk && msc_clk < pclk) \ 2647 pclk = msc_clk; \ 2648 i = 0; \ 2649 while (pclk < rate) \ 2650 { \ 2651 i ++; \ 2652 rate >>= 1; \ 2653 } \ 2654 lv = i; \ 2655 } while(0) 2656 2657 /* divide rate to little than or equal to 400kHz */ 2658 #define __msc_calc_slow_clk_divisor(type, lv) \ 2659 do { \ 2660 unsigned int rate, i; \ 2661 rate = (type?SD_CLK:MMC_CLK)/1000/400; \ 2662 i = 0; \ 2663 while (rate > 0) \ 2664 { \ 2665 rate >>= 1; \ 2666 i ++; \ 2667 } \ 2668 lv = i; \ 2669 } while(0) 2670 2671 /*************************************************************************** 2672 * RTC 2673 ***************************************************************************/ 2674 2675 #define __rtc_start() ( REG_RTC_RCR |= RTC_RCR_START ) 2676 #define __rtc_stop() ( REG_RTC_RCR &= ~RTC_RCR_START ) 2677 2678 #define __rtc_enable_alarm() ( REG_RTC_RCR |= RTC_RCR_AE ) 2679 #define __rtc_disable_alarm() ( REG_RTC_RCR &= ~RTC_RCR_AE ) 2680 #define __rtc_enable_alarm_irq() ( REG_RTC_RCR |= RTC_RCR_AIE ) 2681 #define __rtc_disable_alarm_irq() ( REG_RTC_RCR &= ~RTC_RCR_AIE ) 2682 2683 #define __rtc_enable_1hz_irq() ( REG_RTC_RCR |= RTC_RCR_HZIE ) 2684 #define __rtc_disable_1hz_irq() ( REG_RTC_RCR &= ~RTC_RCR_HZIE ) 2685 2686 #define __rtc_is_alarm_flag() ( REG_RTC_RCR & RTC_RCR_AF ) 2687 #define __rtc_is_1hz_flag() ( REG_RTC_RCR & RTC_RCR_HZ ) 2688 #define __rtc_clear_alarm_flag() ( REG_RTC_RCR &= ~RTC_RCR_AF ) 2689 #define __rtc_clear_1hz_flag() ( REG_RTC_RCR &= ~RTC_RCR_HZ ) 2690 2691 #define __rtc_set_second(s) ( REG_RTC_RSR = (s) ) 2692 #define __rtc_get_second() REG_RTC_RSR 2693 #define __rtc_set_alarm(s) ( REG_RTC_RSAR = (s) ) 2694 #define __rtc_get_alarm() REG_RTC_RSAR 2695 2696 #define __rtc_adjust_1hz(f32k) \ 2697 ( REG_RTC_RGR = (REG_RTC_RGR & ~(RTC_REG_DIV_MASK | RTC_RGR_ADJ_MASK)) | f32k | 0 ) 2698 #define __rtc_lock_1hz() ( REG_RTC_RGR |= RTC_RGR_LOCK ) 2699 2700 2701 /*************************************************************************** 2702 * FIR 2703 ***************************************************************************/ 2704 2705 /* enable/disable fir unit */ 2706 #define __fir_enable() ( REG_FIR_CR1 |= FIR_CR1_FIRUE ) 2707 #define __fir_disable() ( REG_FIR_CR1 &= ~FIR_CR1_FIRUE ) 2708 2709 /* enable/disable address comparison */ 2710 #define __fir_enable_ac() ( REG_FIR_CR1 |= FIR_CR1_ACE ) 2711 #define __fir_disable_ac() ( REG_FIR_CR1 &= ~FIR_CR1_ACE ) 2712 2713 /* select frame end mode as underrun or normal */ 2714 #define __fir_set_eous() ( REG_FIR_CR1 |= FIR_CR1_EOUS ) 2715 #define __fir_clear_eous() ( REG_FIR_CR1 &= ~FIR_CR1_EOUS ) 2716 2717 /* enable/disable transmitter idle interrupt */ 2718 #define __fir_enable_tii() ( REG_FIR_CR1 |= FIR_CR1_TIIE ) 2719 #define __fir_disable_tii() ( REG_FIR_CR1 &= ~FIR_CR1_TIIE ) 2720 2721 /* enable/disable transmit FIFO service request interrupt */ 2722 #define __fir_enable_tfi() ( REG_FIR_CR1 |= FIR_CR1_TFIE ) 2723 #define __fir_disable_tfi() ( REG_FIR_CR1 &= ~FIR_CR1_TFIE ) 2724 2725 /* enable/disable receive FIFO service request interrupt */ 2726 #define __fir_enable_rfi() ( REG_FIR_CR1 |= FIR_CR1_RFIE ) 2727 #define __fir_disable_rfi() ( REG_FIR_CR1 &= ~FIR_CR1_RFIE ) 2728 2729 /* enable/disable tx function */ 2730 #define __fir_tx_enable() ( REG_FIR_CR1 |= FIR_CR1_TXE ) 2731 #define __fir_tx_disable() ( REG_FIR_CR1 &= ~FIR_CR1_TXE ) 2732 2733 /* enable/disable rx function */ 2734 #define __fir_rx_enable() ( REG_FIR_CR1 |= FIR_CR1_RXE ) 2735 #define __fir_rx_disable() ( REG_FIR_CR1 &= ~FIR_CR1_RXE ) 2736 2737 2738 /* enable/disable serial infrared interaction pulse (SIP) */ 2739 #define __fir_enable_sip() ( REG_FIR_CR2 |= FIR_CR2_SIPE ) 2740 #define __fir_disable_sip() ( REG_FIR_CR2 &= ~FIR_CR2_SIPE ) 2741 2742 /* un-inverted CRC value is sent out */ 2743 #define __fir_enable_bcrc() ( REG_FIR_CR2 |= FIR_CR2_BCRC ) 2744 2745 /* inverted CRC value is sent out */ 2746 #define __fir_disable_bcrc() ( REG_FIR_CR2 &= ~FIR_CR2_BCRC ) 2747 2748 /* enable/disable Transmit Frame Length Register */ 2749 #define __fir_enable_tflr() ( REG_FIR_CR2 |= FIR_CR2_TFLRS ) 2750 #define __fir_disable_tflr() ( REG_FIR_CR2 &= ~FIR_CR2_TFLRS ) 2751 2752 /* Preamble is transmitted in idle state */ 2753 #define __fir_set_iss() ( REG_FIR_CR2 |= FIR_CR2_ISS ) 2754 2755 /* Abort symbol is transmitted in idle state */ 2756 #define __fir_clear_iss() ( REG_FIR_CR2 &= ~FIR_CR2_ISS ) 2757 2758 /* enable/disable loopback mode */ 2759 #define __fir_enable_loopback() ( REG_FIR_CR2 |= FIR_CR2_LMS ) 2760 #define __fir_disable_loopback() ( REG_FIR_CR2 &= ~FIR_CR2_LMS ) 2761 2762 /* select transmit pin polarity */ 2763 #define __fir_tpp_negative() ( REG_FIR_CR2 |= FIR_CR2_TPPS ) 2764 #define __fir_tpp_positive() ( REG_FIR_CR2 &= ~FIR_CR2_TPPS ) 2765 2766 /* select receive pin polarity */ 2767 #define __fir_rpp_negative() ( REG_FIR_CR2 |= FIR_CR2_RPPS ) 2768 #define __fir_rpp_positive() ( REG_FIR_CR2 &= ~FIR_CR2_RPPS ) 2769 2770 /* n=16,32,64,128 */ 2771 #define __fir_set_txfifo_trigger(n) \ 2772 do { \ 2773 REG_FIR_CR2 &= ~FIR_CR2_TTRG_MASK; \ 2774 REG_FIR_CR2 |= FIR_CR2_TTRG_##n; \ 2775 } while (0) 2776 2777 /* n=16,32,64,128 */ 2778 #define __fir_set_rxfifo_trigger(n) \ 2779 do { \ 2780 REG_FIR_CR2 &= ~FIR_CR2_RTRG_MASK; \ 2781 REG_FIR_CR2 |= FIR_CR2_RTRG_##n; \ 2782 } while (0) 2783 2784 2785 /* FIR status checking */ 2786 2787 #define __fir_test_rfw() ( REG_FIR_SR & FIR_SR_RFW ) 2788 #define __fir_test_rfa() ( REG_FIR_SR & FIR_SR_RFA ) 2789 #define __fir_test_tfrtl() ( REG_FIR_SR & FIR_SR_TFRTL ) 2790 #define __fir_test_rfrtl() ( REG_FIR_SR & FIR_SR_RFRTL ) 2791 #define __fir_test_urun() ( REG_FIR_SR & FIR_SR_URUN ) 2792 #define __fir_test_rfte() ( REG_FIR_SR & FIR_SR_RFTE ) 2793 #define __fir_test_orun() ( REG_FIR_SR & FIR_SR_ORUN ) 2794 #define __fir_test_crce() ( REG_FIR_SR & FIR_SR_CRCE ) 2795 #define __fir_test_fend() ( REG_FIR_SR & FIR_SR_FEND ) 2796 #define __fir_test_tff() ( REG_FIR_SR & FIR_SR_TFF ) 2797 #define __fir_test_rfe() ( REG_FIR_SR & FIR_SR_RFE ) 2798 #define __fir_test_tidle() ( REG_FIR_SR & FIR_SR_TIDLE ) 2799 #define __fir_test_rb() ( REG_FIR_SR & FIR_SR_RB ) 2800 2801 #define __fir_clear_status() \ 2802 do { \ 2803 REG_FIR_SR |= FIR_SR_RFW | FIR_SR_RFA | FIR_SR_URUN; \ 2804 } while (0) 2805 2806 #define __fir_clear_rfw() ( REG_FIR_SR |= FIR_SR_RFW ) 2807 #define __fir_clear_rfa() ( REG_FIR_SR |= FIR_SR_RFA ) 2808 #define __fir_clear_urun() ( REG_FIR_SR |= FIR_SR_URUN ) 2809 2810 #define __fir_set_tflr(len) \ 2811 do { \ 2812 REG_FIR_TFLR = len; \ 2813 } while (0) 2814 2815 #define __fir_set_addr(a) ( REG_FIR_AR = (a) ) 2816 2817 #define __fir_write_data(data) ( REG_FIR_TDR = data ) 2818 #define __fir_read_data(data) ( data = REG_FIR_RDR ) 2819 2820 /*************************************************************************** 2821 * SCC 2822 ***************************************************************************/ 2823 2824 #define __scc_enable(base) ( REG_SCC_CR(base) |= SCC_CR_SCCE ) 2825 #define __scc_disable(base) ( REG_SCC_CR(base) &= ~SCC_CR_SCCE ) 2826 2827 #define __scc_set_tx_mode(base) ( REG_SCC_CR(base) |= SCC_CR_TRS ) 2828 #define __scc_set_rx_mode(base) ( REG_SCC_CR(base) &= ~SCC_CR_TRS ) 2829 2830 #define __scc_enable_t2r(base) ( REG_SCC_CR(base) |= SCC_CR_T2R ) 2831 #define __scc_disable_t2r(base) ( REG_SCC_CR(base) &= ~SCC_CR_T2R ) 2832 2833 #define __scc_clk_as_devclk(base) \ 2834 do { \ 2835 REG_SCC_CR(base) &= ~SCC_CR_FDIV_MASK; \ 2836 REG_SCC_CR(base) |= SCC_CR_FDIV_1; \ 2837 } while (0) 2838 2839 #define __scc_clk_as_half_devclk(base) \ 2840 do { \ 2841 REG_SCC_CR(base) &= ~SCC_CR_FDIV_MASK; \ 2842 REG_SCC_CR(base) |= SCC_CR_FDIV_2; \ 2843 } while (0) 2844 2845 /* n=1,4,8,14 */ 2846 #define __scc_set_fifo_trigger(base, n) \ 2847 do { \ 2848 REG_SCC_CR(base) &= ~SCC_CR_TRIG_MASK; \ 2849 REG_SCC_CR(base) |= SCC_CR_TRIG_##n; \ 2850 } while (0) 2851 2852 #define __scc_set_protocol(base, p) \ 2853 do { \ 2854 if (p) \ 2855 REG_SCC_CR(base) |= SCC_CR_TP; \ 2856 else \ 2857 REG_SCC_CR(base) &= ~SCC_CR_TP; \ 2858 } while (0) 2859 2860 #define __scc_flush_fifo(base) ( REG_SCC_CR(base) |= SCC_CR_FLUSH ) 2861 2862 #define __scc_set_invert_mode(base) ( REG_SCC_CR(base) |= SCC_CR_CONV ) 2863 #define __scc_set_direct_mode(base) ( REG_SCC_CR(base) &= ~SCC_CR_CONV ) 2864 2865 #define SCC_ERR_INTRS \ 2866 ( SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE ) 2867 #define SCC_ALL_INTRS \ 2868 ( SCC_CR_TXIE | SCC_CR_RXIE | SCC_CR_TENDIE | SCC_CR_RTOIE | \ 2869 SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE ) 2870 2871 #define __scc_enable_err_intrs(base) ( REG_SCC_CR(base) |= SCC_ERR_INTRS ) 2872 #define __scc_disable_err_intrs(base) ( REG_SCC_CR(base) &= ~SCC_ERR_INTRS ) 2873 2874 #define SCC_ALL_ERRORS \ 2875 ( SCC_SR_ORER | SCC_SR_RTO | SCC_SR_PER | SCC_SR_RETR_3 | SCC_SR_ECNTO) 2876 2877 #define __scc_clear_errors(base) ( REG_SCC_SR(base) &= ~SCC_ALL_ERRORS ) 2878 2879 #define __scc_enable_all_intrs(base) ( REG_SCC_CR(base) |= SCC_ALL_INTRS ) 2880 #define __scc_disable_all_intrs(base) ( REG_SCC_CR(base) &= ~SCC_ALL_INTRS ) 2881 2882 #define __scc_enable_tx_intr(base) ( REG_SCC_CR(base) |= SCC_CR_TXIE | SCC_CR_TENDIE ) 2883 #define __scc_disable_tx_intr(base) ( REG_SCC_CR(base) &= ~(SCC_CR_TXIE | SCC_CR_TENDIE) ) 2884 2885 #define __scc_enable_rx_intr(base) ( REG_SCC_CR(base) |= SCC_CR_RXIE) 2886 #define __scc_disable_rx_intr(base) ( REG_SCC_CR(base) &= ~SCC_CR_RXIE) 2887 2888 #define __scc_set_tsend(base) ( REG_SCC_CR(base) |= SCC_CR_TSEND ) 2889 #define __scc_clear_tsend(base) ( REG_SCC_CR(base) &= ~SCC_CR_TSEND ) 2890 2891 #define __scc_set_clockstop(base) ( REG_SCC_CR(base) |= SCC_CR_CLKSTP ) 2892 #define __scc_clear_clockstop(base) ( REG_SCC_CR(base) &= ~SCC_CR_CLKSTP ) 2893 2894 #define __scc_clockstop_low(base) \ 2895 do { \ 2896 REG_SCC_CR(base) &= ~SCC_CR_PX_MASK; \ 2897 REG_SCC_CR(base) |= SCC_CR_PX_STOP_LOW; \ 2898 } while (0) 2899 2900 #define __scc_clockstop_high(base) \ 2901 do { \ 2902 REG_SCC_CR(base) &= ~SCC_CR_PX_MASK; \ 2903 REG_SCC_CR(base) |= SCC_CR_PX_STOP_HIGH; \ 2904 } while (0) 2905 2906 2907 /* SCC status checking */ 2908 #define __scc_check_transfer_status(base) ( REG_SCC_SR(base) & SCC_SR_TRANS ) 2909 #define __scc_check_rx_overrun_error(base) ( REG_SCC_SR(base) & SCC_SR_ORER ) 2910 #define __scc_check_rx_timeout(base) ( REG_SCC_SR(base) & SCC_SR_RTO ) 2911 #define __scc_check_parity_error(base) ( REG_SCC_SR(base) & SCC_SR_PER ) 2912 #define __scc_check_txfifo_trigger(base) ( REG_SCC_SR(base) & SCC_SR_TFTG ) 2913 #define __scc_check_rxfifo_trigger(base) ( REG_SCC_SR(base) & SCC_SR_RFTG ) 2914 #define __scc_check_tx_end(base) ( REG_SCC_SR(base) & SCC_SR_TEND ) 2915 #define __scc_check_retx_3(base) ( REG_SCC_SR(base) & SCC_SR_RETR_3 ) 2916 #define __scc_check_ecnt_overflow(base) ( REG_SCC_SR(base) & SCC_SR_ECNTO ) 2917 2918 2919 /*************************************************************************** 2920 * WDT 2921 ***************************************************************************/ 2922 2923 #define __wdt_set_count(count) ( REG_WDT_WTCNT = (count) ) 2924 #define __wdt_start() ( REG_WDT_WTCSR |= WDT_WTCSR_START ) 2925 #define __wdt_stop() ( REG_WDT_WTCSR &= ~WDT_WTCSR_START ) 2926 2927 2928 /*************************************************************************** 2929 * OST 2930 ***************************************************************************/ 2931 2932 #define __ost_enable_all() ( REG_OST_TER |= 0x07 ) 2933 #define __ost_disable_all() ( REG_OST_TER &= ~0x07 ) 2934 #define __ost_enable_channel(n) ( REG_OST_TER |= (1 << (n)) ) 2935 #define __ost_disable_channel(n) ( REG_OST_TER &= ~(1 << (n)) ) 2936 #define __ost_set_reload(n, val) ( REG_OST_TRDR(n) = (val) ) 2937 #define __ost_set_count(n, val) ( REG_OST_TCNT(n) = (val) ) 2938 #define __ost_get_count(n) ( REG_OST_TCNT(n) ) 2939 #define __ost_set_clock(n, cs) ( REG_OST_TCSR(n) |= (cs) ) 2940 #define __ost_set_mode(n, val) ( REG_OST_TCSR(n) = (val) ) 2941 #define __ost_enable_interrupt(n) ( REG_OST_TCSR(n) |= OST_TCSR_UIE ) 2942 #define __ost_disable_interrupt(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_UIE ) 2943 #define __ost_uf_detected(n) ( REG_OST_TCSR(n) & OST_TCSR_UF ) 2944 #define __ost_clear_uf(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_UF ) 2945 #define __ost_is_busy(n) ( REG_OST_TCSR(n) & OST_TCSR_BUSY ) 2946 #define __ost_clear_busy(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_BUSY ) 2947 2948 2949 /*************************************************************************** 2950 * UART 2951 ***************************************************************************/ 2952 2953 #define __uart_enable(n) \ 2954 ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = UARTFCR_UUE | UARTFCR_FE ) 2955 #define __uart_disable(n) \ 2956 ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = ~UARTFCR_UUE ) 2957 2958 #define __uart_enable_transmit_irq(n) \ 2959 ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_TIE ) 2960 #define __uart_disable_transmit_irq(n) \ 2961 ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~UARTIER_TIE ) 2962 2963 #define __uart_enable_receive_irq(n) \ 2964 ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE ) 2965 #define __uart_disable_receive_irq(n) \ 2966 ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) ) 2967 2968 #define __uart_enable_loopback(n) \ 2969 ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) |= UARTMCR_LOOP ) 2970 #define __uart_disable_loopback(n) \ 2971 ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) &= ~UARTMCR_LOOP ) 2972 2973 #define __uart_set_8n1(n) \ 2974 ( REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) = UARTLCR_WLEN_8 ) 2975 2976 #define __uart_set_baud(n, devclk, baud) \ 2977 do { \ 2978 REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) |= UARTLCR_DLAB; \ 2979 REG8(UART_BASE + UART_OFF*(n) + OFF_DLLR) = (devclk / 16 / baud) & 0xff; \ 2980 REG8(UART_BASE + UART_OFF*(n) + OFF_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \ 2981 REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) &= ~UARTLCR_DLAB; \ 2982 } while (0) 2983 2984 #define __uart_parity_error(n) \ 2985 ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_PER) != 0 ) 2986 2987 #define __uart_clear_errors(n) \ 2988 ( REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTSR_RFER) ) 2989 2990 #define __uart_transmit_fifo_empty(n) \ 2991 ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TDRQ) != 0 ) 2992 2993 #define __uart_transmit_end(n) \ 2994 ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TEMT) != 0 ) 2995 2996 #define __uart_transmit_char(n, ch) \ 2997 REG8(UART_BASE + UART_OFF*(n) + OFF_TDR) = (ch) 2998 2999 #define __uart_receive_fifo_full(n) \ 3000 ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) 3001 3002 #define __uart_receive_ready(n) \ 3003 ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 ) 3004 3005 #define __uart_receive_char(n) \ 3006 REG8(UART_BASE + UART_OFF*(n) + OFF_RDR) 3007 3008 #define __uart_disable_irda() \ 3009 ( REG8(IRDA_BASE + OFF_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) ) 3010 #define __uart_enable_irda() \ 3011 /* Tx high pulse as 0, Rx low pulse as 0 */ \ 3012 ( REG8(IRDA_BASE + OFF_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS ) 3013 3014 3015 /*************************************************************************** 3016 * INTC 3017 ***************************************************************************/ 3018 #define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) ) 3019 #define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) ) 3020 #define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) ) 3021 3022 /*************************************************************************** 3023 * CIM 3024 ***************************************************************************/ 3025 3026 #define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA ) 3027 #define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA ) 3028 3029 #define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT ) 3030 #define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT ) 3031 3032 #define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP ) 3033 #define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP ) 3034 3035 #define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP ) 3036 #define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP ) 3037 3038 #define __cim_sample_data_at_pclk_falling_edge() \ 3039 ( REG_CIM_CFG |= CIM_CFG_PCP ) 3040 #define __cim_sample_data_at_pclk_rising_edge() \ 3041 ( REG_CIM_CFG &= ~CIM_CFG_PCP ) 3042 3043 #define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO ) 3044 #define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO ) 3045 3046 #define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC ) 3047 #define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC ) 3048 3049 /* n=0-7 */ 3050 #define __cim_set_data_packing_mode(n) \ 3051 do { \ 3052 REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \ 3053 REG_CIM_CFG |= (CIM_CFG_PACK_##n); \ 3054 } while (0) 3055 3056 #define __cim_enable_ccir656_progressive_mode() \ 3057 do { \ 3058 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 3059 REG_CIM_CFG |= CIM_CFG_DSM_CPM; \ 3060 } while (0) 3061 3062 #define __cim_enable_ccir656_interlace_mode() \ 3063 do { \ 3064 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 3065 REG_CIM_CFG |= CIM_CFG_DSM_CIM; \ 3066 } while (0) 3067 3068 #define __cim_enable_gated_clock_mode() \ 3069 do { \ 3070 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 3071 REG_CIM_CFG |= CIM_CFG_DSM_GCM; \ 3072 } while (0) 3073 3074 #define __cim_enable_nongated_clock_mode() \ 3075 do { \ 3076 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \ 3077 REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \ 3078 } while (0) 3079 3080 /* sclk:system bus clock 3081 * mclk: CIM master clock 3082 */ 3083 #define __cim_set_master_clk(sclk, mclk) \ 3084 do { \ 3085 REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \ 3086 REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \ 3087 } while (0) 3088 3089 #define __cim_enable_sof_intr() \ 3090 ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM ) 3091 #define __cim_disable_sof_intr() \ 3092 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM ) 3093 3094 #define __cim_enable_eof_intr() \ 3095 ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM ) 3096 #define __cim_disable_eof_intr() \ 3097 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM ) 3098 3099 #define __cim_enable_stop_intr() \ 3100 ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM ) 3101 #define __cim_disable_stop_intr() \ 3102 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM ) 3103 3104 #define __cim_enable_trig_intr() \ 3105 ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM ) 3106 #define __cim_disable_trig_intr() \ 3107 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM ) 3108 3109 #define __cim_enable_rxfifo_overflow_intr() \ 3110 ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM ) 3111 #define __cim_disable_rxfifo_overflow_intr() \ 3112 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM ) 3113 3114 /* n=1-16 */ 3115 #define __cim_set_frame_rate(n) \ 3116 do { \ 3117 REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \ 3118 REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \ 3119 } while (0) 3120 3121 #define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN ) 3122 #define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN ) 3123 3124 #define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST ) 3125 #define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST ) 3126 3127 /* n=4,8,12,16,20,24,28,32 */ 3128 #define __cim_set_rxfifo_trigger(n) \ 3129 do { \ 3130 REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \ 3131 REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \ 3132 } while (0) 3133 3134 #define __cim_clear_state() ( REG_CIM_STATE = 0 ) 3135 3136 #define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD ) 3137 #define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY ) 3138 #define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG ) 3139 #define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF ) 3140 #define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF ) 3141 #define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP ) 3142 #define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF ) 3143 #define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF ) 3144 3145 #define __cim_get_iid() ( REG_CIM_IID ) 3146 #define __cim_get_image_data() ( REG_CIM_RXFIFO ) 3147 #define __cim_get_dam_cmd() ( REG_CIM_CMD ) 3148 3149 #define __cim_set_da(a) ( REG_CIM_DA = (a) ) 3150 3151 /*************************************************************************** 3152 * PWM 3153 ***************************************************************************/ 3154 3155 /* n is the pwm channel (0,1,..) */ 3156 #define __pwm_enable_module(n) ( REG_PWM_CTR(n) |= PWM_CTR_EN ) 3157 #define __pwm_disable_module(n) ( REG_PWM_CTR(n) &= ~PWM_CTR_EN ) 3158 #define __pwm_graceful_shutdown_mode(n) ( REG_PWM_CTR(n) &= ~PWM_CTR_SD ) 3159 #define __pwm_abrupt_shutdown_mode(n) ( REG_PWM_CTR(n) |= PWM_CTR_SD ) 3160 #define __pwm_set_full_duty(n) ( REG_PWM_DUT(n) |= PWM_DUT_FDUTY ) 3161 3162 #define __pwm_set_prescale(n, p) \ 3163 ( REG_PWM_CTR(n) = ((REG_PWM_CTR(n) & ~PWM_CTR_PRESCALE_MASK) | (p) ) ) 3164 #define __pwm_set_period(n, p) \ 3165 ( REG_PWM_PER(n) = ( (REG_PWM_PER(n) & ~PWM_PER_PERIOD_MASK) | (p) ) ) 3166 #define __pwm_set_duty(n, d) \ 3167 ( REG_PWM_DUT(n) = ( (REG_PWM_DUT(n) & ~PWM_DUT_FDUTY) | (d) ) ) 3168 3169 /*************************************************************************** 3170 * EMC 3171 ***************************************************************************/ 3172 3173 #define __emc_enable_split() ( REG_EMC_BCR = EMC_BCR_BRE ) 3174 #define __emc_disable_split() ( REG_EMC_BCR = 0 ) 3175 3176 #define __emc_smem_bus_width(n) /* 8, 16 or 32*/ \ 3177 ( REG_EMC_SMCR = (REG_EMC_SMCR & EMC_SMCR_BW_MASK) | \ 3178 EMC_SMCR_BW_##n##BIT ) 3179 #define __emc_smem_byte_control() \ 3180 ( REG_EMC_SMCR = (REG_EMC_SMCR | EMC_SMCR_BCM ) 3181 #define __emc_normal_smem() \ 3182 ( REG_EMC_SMCR = (REG_EMC_SMCR & ~EMC_SMCR_SMT ) 3183 #define __emc_burst_smem() \ 3184 ( REG_EMC_SMCR = (REG_EMC_SMCR | EMC_SMCR_SMT ) 3185 #define __emc_smem_burstlen(n) /* 4, 8, 16 or 32 */ \ 3186 ( REG_EMC_SMCR = (REG_EMC_SMCR & EMC_SMCR_BL_MASK) | (EMC_SMCR_BL_##n ) 3187 3188 /*************************************************************************** 3189 * GPIO 3190 ***************************************************************************/ 3191 3192 /* p is the port number (0,1,2,3) 3193 * o is the pin offset (0-31) inside the port 3194 * n is the absolute number of a pin (0-124), regardless of the port 3195 * m is the interrupt manner (low/high/falling/rising) 3196 */ 3197 3198 #define __gpio_port_data(p) ( REG_GPIO_GPDR(p) ) 3199 3200 #define __gpio_port_as_output(p, o) \ 3201 do { \ 3202 unsigned int tmp; \ 3203 REG_GPIO_GPIER(p) &= ~(1 << (o)); \ 3204 REG_GPIO_GPDIR(p) |= (1 << (o)); \ 3205 if (o < 16) { \ 3206 tmp = REG_GPIO_GPALR(p); \ 3207 tmp &= ~(3 << ((o) << 1)); \ 3208 REG_GPIO_GPALR(p) = tmp; \ 3209 } else { \ 3210 tmp = REG_GPIO_GPAUR(p); \ 3211 tmp &= ~(3 << (((o) - 16)<< 1)); \ 3212 REG_GPIO_GPAUR(p) = tmp; \ 3213 } \ 3214 } while (0) 3215 3216 #define __gpio_port_as_input(p, o) \ 3217 do { \ 3218 unsigned int tmp; \ 3219 REG_GPIO_GPIER(p) &= ~(1 << (o)); \ 3220 REG_GPIO_GPDIR(p) &= ~(1 << (o)); \ 3221 if (o < 16) { \ 3222 tmp = REG_GPIO_GPALR(p); \ 3223 tmp &= ~(3 << ((o) << 1)); \ 3224 REG_GPIO_GPALR(p) = tmp; \ 3225 } else { \ 3226 tmp = REG_GPIO_GPAUR(p); \ 3227 tmp &= ~(3 << (((o) - 16)<< 1)); \ 3228 REG_GPIO_GPAUR(p) = tmp; \ 3229 } \ 3230 } while (0) 3231 3232 #define __gpio_as_output(n) \ 3233 do { \ 3234 unsigned int p, o; \ 3235 p = (n) / 32; \ 3236 o = (n) % 32; \ 3237 __gpio_port_as_output(p, o); \ 3238 } while (0) 3239 3240 #define __gpio_as_input(n) \ 3241 do { \ 3242 unsigned int p, o; \ 3243 p = (n) / 32; \ 3244 o = (n) % 32; \ 3245 __gpio_port_as_input(p, o); \ 3246 } while (0) 3247 3248 #define __gpio_set_pin(n) \ 3249 do { \ 3250 unsigned int p, o; \ 3251 p = (n) / 32; \ 3252 o = (n) % 32; \ 3253 __gpio_port_data(p) |= (1 << o); \ 3254 } while (0) 3255 3256 #define __gpio_clear_pin(n) \ 3257 do { \ 3258 unsigned int p, o; \ 3259 p = (n) / 32; \ 3260 o = (n) % 32; \ 3261 __gpio_port_data(p) &= ~(1 << o); \ 3262 } while (0) 3263 3264 static __inline__ unsigned int __gpio_get_pin(unsigned int n) 3265 { 3266 unsigned int p, o; 3267 p = (n) / 32; 3268 o = (n) % 32; 3269 if (__gpio_port_data(p) & (1 << o)) 3270 return 1; 3271 else 3272 return 0; 3273 } 3274 3275 3276 #define __gpio_set_irq_detect_manner(p, o, m) \ 3277 do { \ 3278 unsigned int tmp; \ 3279 if (o < 16) { \ 3280 tmp = REG_GPIO_GPIDLR(p); \ 3281 tmp &= ~(3 << ((o) << 1)); \ 3282 tmp |= ((m) << ((o) << 1)); \ 3283 REG_GPIO_GPIDLR(p) = tmp; \ 3284 } else { \ 3285 o -= 16; \ 3286 tmp = REG_GPIO_GPIDUR(p); \ 3287 tmp &= ~(3 << ((o) << 1)); \ 3288 tmp |= ((m) << ((o) << 1)); \ 3289 REG_GPIO_GPIDUR(p) = tmp; \ 3290 } \ 3291 } while (0) 3292 3293 #define __gpio_port_as_irq(p, o, m) \ 3294 do { \ 3295 __gpio_set_irq_detect_manner(p, o, m); \ 3296 __gpio_port_as_input(p, o); \ 3297 REG_GPIO_GPIER(p) |= (1 << o); \ 3298 } while (0) 3299 3300 #define __gpio_as_irq(n, m) \ 3301 do { \ 3302 unsigned int p, o; \ 3303 p = (n) / 32; \ 3304 o = (n) % 32; \ 3305 __gpio_port_as_irq(p, o, m); \ 3306 } while (0) 3307 3308 3309 #define __gpio_as_irq_high_level(n) __gpio_as_irq(n, GPIO_IRQ_HILEVEL) 3310 #define __gpio_as_irq_low_level(n) __gpio_as_irq(n, GPIO_IRQ_LOLEVEL) 3311 #define __gpio_as_irq_fall_edge(n) __gpio_as_irq(n, GPIO_IRQ_FALLEDG) 3312 #define __gpio_as_irq_rise_edge(n) __gpio_as_irq(n, GPIO_IRQ_RAISEDG) 3313 3314 3315 #define __gpio_mask_irq(n) \ 3316 do { \ 3317 unsigned int p, o; \ 3318 p = (n) / 32; \ 3319 o = (n) % 32; \ 3320 REG_GPIO_GPIER(p) &= ~(1 << o); \ 3321 } while (0) 3322 3323 #define __gpio_unmask_irq(n) \ 3324 do { \ 3325 unsigned int p, o; \ 3326 p = (n) / 32; \ 3327 o = (n) % 32; \ 3328 REG_GPIO_GPIER(n) |= (1 << o); \ 3329 } while (0) 3330 3331 #define __gpio_ack_irq(n) \ 3332 do { \ 3333 unsigned int p, o; \ 3334 p = (n) / 32; \ 3335 o = (n) % 32; \ 3336 REG_GPIO_GPFR(p) |= (1 << o); \ 3337 } while (0) 3338 3339 3340 static __inline__ unsigned int __gpio_get_irq(void) 3341 { 3342 unsigned int tmp, i; 3343 3344 tmp = REG_GPIO_GPFR(3); 3345 for (i=0; i<32; i++) 3346 if (tmp & (1 << i)) 3347 return 0x60 + i; 3348 tmp = REG_GPIO_GPFR(2); 3349 for (i=0; i<32; i++) 3350 if (tmp & (1 << i)) 3351 return 0x40 + i; 3352 tmp = REG_GPIO_GPFR(1); 3353 for (i=0; i<32; i++) 3354 if (tmp & (1 << i)) 3355 return 0x20 + i; 3356 tmp = REG_GPIO_GPFR(0); 3357 for (i=0; i<32; i++) 3358 if (tmp & (1 << i)) 3359 return i; 3360 return 0; 3361 } 3362 3363 #define __gpio_group_irq(n) \ 3364 ({ \ 3365 register int tmp, i; \ 3366 tmp = REG_GPIO_GPFR((n)); \ 3367 for (i=31;i>=0;i--) \ 3368 if (tmp & (1 << i)) \ 3369 break; \ 3370 i; \ 3371 }) 3372 3373 #define __gpio_enable_pull(n) \ 3374 do { \ 3375 unsigned int p, o; \ 3376 p = (n) / 32; \ 3377 o = (n) % 32; \ 3378 REG_GPIO_GPPUR(p) |= (1 << o); \ 3379 } while (0) 3380 3381 #define __gpio_disable_pull(n) \ 3382 do { \ 3383 unsigned int p, o; \ 3384 p = (n) / 32; \ 3385 o = (n) % 32; \ 3386 REG_GPIO_GPPUR(p) &= ~(1 << o); \ 3387 } while (0) 3388 3389 /* Init the alternate function pins */ 3390 3391 3392 #define __gpio_as_ssi() \ 3393 do { \ 3394 REG_GPIO_GPALR(2) &= 0xFC00FFFF; \ 3395 REG_GPIO_GPALR(2) |= 0x01550000; \ 3396 } while (0) 3397 3398 #define __gpio_as_uart3() \ 3399 do { \ 3400 REG_GPIO_GPAUR(0) &= 0xFFFF0000; \ 3401 REG_GPIO_GPAUR(0) |= 0x00005555; \ 3402 } while (0) 3403 3404 #define __gpio_as_uart2() \ 3405 do { \ 3406 REG_GPIO_GPALR(3) &= 0x3FFFFFFF; \ 3407 REG_GPIO_GPALR(3) |= 0x40000000; \ 3408 REG_GPIO_GPAUR(3) &= 0xF3FFFFFF; \ 3409 REG_GPIO_GPAUR(3) |= 0x04000000; \ 3410 } while (0) 3411 3412 #define __gpio_as_uart1() \ 3413 do { \ 3414 REG_GPIO_GPAUR(0) &= 0xFFF0FFFF; \ 3415 REG_GPIO_GPAUR(0) |= 0x00050000; \ 3416 } while (0) 3417 3418 #define __gpio_as_uart0() \ 3419 do { \ 3420 REG_GPIO_GPAUR(3) &= 0x0FFFFFFF; \ 3421 REG_GPIO_GPAUR(3) |= 0x50000000; \ 3422 } while (0) 3423 3424 3425 #define __gpio_as_scc0() \ 3426 do { \ 3427 REG_GPIO_GPALR(2) &= 0xFFFFFFCC; \ 3428 REG_GPIO_GPALR(2) |= 0x00000011; \ 3429 } while (0) 3430 3431 #define __gpio_as_scc1() \ 3432 do { \ 3433 REG_GPIO_GPALR(2) &= 0xFFFFFF33; \ 3434 REG_GPIO_GPALR(2) |= 0x00000044; \ 3435 } while (0) 3436 3437 #define __gpio_as_scc() \ 3438 do { \ 3439 __gpio_as_scc0(); \ 3440 __gpio_as_scc1(); \ 3441 } while (0) 3442 3443 #define __gpio_as_dma() \ 3444 do { \ 3445 REG_GPIO_GPALR(0) &= 0x00FFFFFF; \ 3446 REG_GPIO_GPALR(0) |= 0x55000000; \ 3447 REG_GPIO_GPAUR(0) &= 0xFF0FFFFF; \ 3448 REG_GPIO_GPAUR(0) |= 0x00500000; \ 3449 } while (0) 3450 3451 #define __gpio_as_msc() \ 3452 do { \ 3453 REG_GPIO_GPALR(1) &= 0xFFFF000F; \ 3454 REG_GPIO_GPALR(1) |= 0x00005550; \ 3455 } while (0) 3456 3457 #define __gpio_as_pcmcia() \ 3458 do { \ 3459 REG_GPIO_GPAUR(2) &= 0xF000FFFF; \ 3460 REG_GPIO_GPAUR(2) |= 0x05550000; \ 3461 } while (0) 3462 3463 #define __gpio_as_emc() \ 3464 do { \ 3465 REG_GPIO_GPALR(2) &= 0x3FFFFFFF; \ 3466 REG_GPIO_GPALR(2) |= 0x40000000; \ 3467 REG_GPIO_GPAUR(2) &= 0xFFFF0000; \ 3468 REG_GPIO_GPAUR(2) |= 0x00005555; \ 3469 } while (0) 3470 3471 #define __gpio_as_lcd_slave() \ 3472 do { \ 3473 REG_GPIO_GPALR(1) &= 0x0000FFFF; \ 3474 REG_GPIO_GPALR(1) |= 0x55550000; \ 3475 REG_GPIO_GPAUR(1) &= 0x00000000; \ 3476 REG_GPIO_GPAUR(1) |= 0x55555555; \ 3477 } while (0) 3478 3479 #define __gpio_as_lcd_master() \ 3480 do { \ 3481 REG_GPIO_GPALR(1) &= 0x0000FFFF; \ 3482 REG_GPIO_GPALR(1) |= 0x55550000; \ 3483 REG_GPIO_GPAUR(1) &= 0x00000000; \ 3484 REG_GPIO_GPAUR(1) |= 0x556A5555; \ 3485 } while (0) 3486 3487 #define __gpio_as_usb() \ 3488 do { \ 3489 REG_GPIO_GPAUR(0) &= 0x00FFFFFF; \ 3490 REG_GPIO_GPAUR(0) |= 0x55000000; \ 3491 } while (0) 3492 3493 #define __gpio_as_ac97() \ 3494 do { \ 3495 REG_GPIO_GPALR(2) &= 0xC3FF03FF; \ 3496 REG_GPIO_GPALR(2) |= 0x24005400; \ 3497 } while (0) 3498 3499 #define __gpio_as_i2s_slave() \ 3500 do { \ 3501 REG_GPIO_GPALR(2) &= 0xC3FF0CFF; \ 3502 REG_GPIO_GPALR(2) |= 0x14005100; \ 3503 } while (0) 3504 3505 #define __gpio_as_i2s_master() \ 3506 do { \ 3507 REG_GPIO_GPALR(2) &= 0xC3FF0CFF; \ 3508 REG_GPIO_GPALR(2) |= 0x28005100; \ 3509 } while (0) 3510 3511 #define __gpio_as_eth() \ 3512 do { \ 3513 REG_GPIO_GPAUR(3) &= 0xFC000000; \ 3514 REG_GPIO_GPAUR(3) |= 0x01555555; \ 3515 } while (0) 3516 3517 #define __gpio_as_pwm() \ 3518 do { \ 3519 REG_GPIO_GPAUR(2) &= 0x0FFFFFFF; \ 3520 REG_GPIO_GPAUR(2) |= 0x50000000; \ 3521 } while (0) 3522 3523 #define __gpio_as_ps2() \ 3524 do { \ 3525 REG_GPIO_GPALR(1) &= 0xFFFFFFF0; \ 3526 REG_GPIO_GPALR(1) |= 0x00000005; \ 3527 } while (0) 3528 3529 #define __gpio_as_uprt() \ 3530 do { \ 3531 REG_GPIO_GPALR(1) &= 0x0000000F; \ 3532 REG_GPIO_GPALR(1) |= 0x55555550; \ 3533 REG_GPIO_GPALR(3) &= 0xC0000000; \ 3534 REG_GPIO_GPALR(3) |= 0x15555555; \ 3535 } while (0) 3536 3537 #define __gpio_as_cim() \ 3538 do { \ 3539 REG_GPIO_GPALR(0) &= 0xFF000000; \ 3540 REG_GPIO_GPALR(0) |= 0x00555555; \ 3541 } while (0) 3542 3543 /*************************************************************************** 3544 * HARB 3545 ***************************************************************************/ 3546 3547 #define __harb_usb0_udc() \ 3548 do { \ 3549 REG_HARB_HAPOR &= ~HARB_HAPOR_UCHSEL; \ 3550 } while (0) 3551 3552 #define __harb_usb0_uhc() \ 3553 do { \ 3554 REG_HARB_HAPOR |= HARB_HAPOR_UCHSEL; \ 3555 } while (0) 3556 3557 #define __harb_set_priority(n) \ 3558 do { \ 3559 REG_HARB_HAPOR = ((REG_HARB_HAPOR & ~HARB_HAPOR_PRIO_MASK) | n); \ 3560 } while (0) 3561 3562 /*************************************************************************** 3563 * I2C 3564 ***************************************************************************/ 3565 3566 #define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE ) 3567 #define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE ) 3568 3569 #define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA ) 3570 #define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO ) 3571 #define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC ) 3572 #define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC ) 3573 3574 #define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF ) 3575 #define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF ) 3576 #define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF ) 3577 3578 #define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) ) 3579 #define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY ) 3580 #define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND ) 3581 3582 #define __i2c_set_clk(dev_clk, i2c_clk) \ 3583 ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 ) 3584 3585 #define __i2c_read() ( REG_I2C_DR ) 3586 #define __i2c_write(val) ( REG_I2C_DR = (val) ) 3587 3588 /*************************************************************************** 3589 * UDC 3590 ***************************************************************************/ 3591 3592 #define __udc_set_16bit_phy() ( REG_UDC_DevCFGR |= UDC_DevCFGR_PI ) 3593 #define __udc_set_8bit_phy() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_PI ) 3594 3595 #define __udc_enable_sync_frame() ( REG_UDC_DevCFGR |= UDC_DevCFGR_SS ) 3596 #define __udc_disable_sync_frame() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_SS ) 3597 3598 #define __udc_self_powered() ( REG_UDC_DevCFGR |= UDC_DevCFGR_SP ) 3599 #define __udc_bus_powered() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_SP ) 3600 3601 #define __udc_enable_remote_wakeup() ( REG_UDC_DevCFGR |= UDC_DevCFGR_RW ) 3602 #define __udc_disable_remote_wakeup() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_RW ) 3603 3604 #define __udc_set_speed_high() \ 3605 do { \ 3606 REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ 3607 REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_HS; \ 3608 } while (0) 3609 3610 #define __udc_set_speed_full() \ 3611 do { \ 3612 REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ 3613 REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_FS; \ 3614 } while (0) 3615 3616 #define __udc_set_speed_low() \ 3617 do { \ 3618 REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \ 3619 REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_LS; \ 3620 } while (0) 3621 3622 3623 #define __udc_set_dma_mode() ( REG_UDC_DevCR |= UDC_DevCR_DM ) 3624 #define __udc_set_slave_mode() ( REG_UDC_DevCR &= ~UDC_DevCR_DM ) 3625 #define __udc_set_big_endian() ( REG_UDC_DevCR |= UDC_DevCR_BE ) 3626 #define __udc_set_little_endian() ( REG_UDC_DevCR &= ~UDC_DevCR_BE ) 3627 #define __udc_generate_resume() ( REG_UDC_DevCR |= UDC_DevCR_RES ) 3628 #define __udc_clear_resume() ( REG_UDC_DevCR &= ~UDC_DevCR_RES ) 3629 3630 3631 #define __udc_get_enumarated_speed() ( REG_UDC_DevSR & UDC_DevSR_ENUMSPD_MASK ) 3632 #define __udc_suspend_detected() ( REG_UDC_DevSR & UDC_DevSR_SUSP ) 3633 #define __udc_get_alternate_setting() ( (REG_UDC_DevSR & UDC_DevSR_ALT_MASK) >> UDC_DevSR_ALT_BIT ) 3634 #define __udc_get_interface_number() ( (REG_UDC_DevSR & UDC_DevSR_INTF_MASK) >> UDC_DevSR_INTF_BIT ) 3635 #define __udc_get_config_number() ( (REG_UDC_DevSR & UDC_DevSR_CFG_MASK) >> UDC_DevSR_CFG_BIT ) 3636 3637 3638 #define __udc_sof_detected(r) ( (r) & UDC_DevIntR_SOF ) 3639 #define __udc_usb_suspend_detected(r) ( (r) & UDC_DevIntR_US ) 3640 #define __udc_usb_reset_detected(r) ( (r) & UDC_DevIntR_UR ) 3641 #define __udc_set_interface_detected(r) ( (r) & UDC_DevIntR_SI ) 3642 #define __udc_set_config_detected(r) ( (r) & UDC_DevIntR_SC ) 3643 3644 #define __udc_clear_sof() ( REG_UDC_DevIntR |= UDC_DevIntR_SOF ) 3645 #define __udc_clear_usb_suspend() ( REG_UDC_DevIntR |= UDC_DevIntR_US ) 3646 #define __udc_clear_usb_reset() ( REG_UDC_DevIntR |= UDC_DevIntR_UR ) 3647 #define __udc_clear_set_interface() ( REG_UDC_DevIntR |= UDC_DevIntR_SI ) 3648 #define __udc_clear_set_config() ( REG_UDC_DevIntR |= UDC_DevIntR_SC ) 3649 3650 #define __udc_mask_sof() ( REG_UDC_DevIntMR |= UDC_DevIntR_SOF ) 3651 #define __udc_mask_usb_suspend() ( REG_UDC_DevIntMR |= UDC_DevIntR_US ) 3652 #define __udc_mask_usb_reset() ( REG_UDC_DevIntMR |= UDC_DevIntR_UR ) 3653 #define __udc_mask_set_interface() ( REG_UDC_DevIntMR |= UDC_DevIntR_SI ) 3654 #define __udc_mask_set_config() ( REG_UDC_DevIntMR |= UDC_DevIntR_SC ) 3655 #define __udc_mask_all_dev_intrs() \ 3656 ( REG_UDC_DevIntMR = UDC_DevIntR_SOF | UDC_DevIntR_US | \ 3657 UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC ) 3658 3659 #define __udc_unmask_sof() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SOF ) 3660 #define __udc_unmask_usb_suspend() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_US ) 3661 #define __udc_unmask_usb_reset() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_UR ) 3662 #define __udc_unmask_set_interface() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SI ) 3663 #define __udc_unmask_set_config() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SC ) 3664 #if 0 3665 #define __udc_unmask_all_dev_intrs() \ 3666 ( REG_UDC_DevIntMR = ~(UDC_DevIntR_SOF | UDC_DevIntR_US | \ 3667 UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC) ) 3668 #else 3669 #define __udc_unmask_all_dev_intrs() \ 3670 ( REG_UDC_DevIntMR = 0x00000000 ) 3671 #endif 3672 3673 3674 #define __udc_ep0out_irq_detected(epintr) \ 3675 ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 0)) & 0x1 ) 3676 #define __udc_ep5out_irq_detected(epintr) \ 3677 ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 5)) & 0x1 ) 3678 #define __udc_ep6out_irq_detected(epintr) \ 3679 ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 6)) & 0x1 ) 3680 #define __udc_ep7out_irq_detected(epintr) \ 3681 ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 7)) & 0x1 ) 3682 3683 #define __udc_ep0in_irq_detected(epintr) \ 3684 ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 0)) & 0x1 ) 3685 #define __udc_ep1in_irq_detected(epintr) \ 3686 ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 1)) & 0x1 ) 3687 #define __udc_ep2in_irq_detected(epintr) \ 3688 ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 2)) & 0x1 ) 3689 #define __udc_ep3in_irq_detected(epintr) \ 3690 ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 3)) & 0x1 ) 3691 #define __udc_ep4in_irq_detected(epintr) \ 3692 ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 4)) & 0x1 ) 3693 3694 3695 #define __udc_mask_ep0out_irq() \ 3696 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 0)) ) 3697 #define __udc_mask_ep5out_irq() \ 3698 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 5)) ) 3699 #define __udc_mask_ep6out_irq() \ 3700 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 6)) ) 3701 #define __udc_mask_ep7out_irq() \ 3702 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 7)) ) 3703 3704 #define __udc_unmask_ep0out_irq() \ 3705 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 0)) ) 3706 #define __udc_unmask_ep5out_irq() \ 3707 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 5)) ) 3708 #define __udc_unmask_ep6out_irq() \ 3709 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 6)) ) 3710 #define __udc_unmask_ep7out_irq() \ 3711 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 7)) ) 3712 3713 #define __udc_mask_ep0in_irq() \ 3714 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 0)) ) 3715 #define __udc_mask_ep1in_irq() \ 3716 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 1)) ) 3717 #define __udc_mask_ep2in_irq() \ 3718 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 2)) ) 3719 #define __udc_mask_ep3in_irq() \ 3720 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 3)) ) 3721 #define __udc_mask_ep4in_irq() \ 3722 ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 4)) ) 3723 3724 #define __udc_unmask_ep0in_irq() \ 3725 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 0)) ) 3726 #define __udc_unmask_ep1in_irq() \ 3727 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 1)) ) 3728 #define __udc_unmask_ep2in_irq() \ 3729 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 2)) ) 3730 #define __udc_unmask_ep3in_irq() \ 3731 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 3)) ) 3732 #define __udc_unmask_ep4in_irq() \ 3733 ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 4)) ) 3734 3735 #define __udc_mask_all_ep_intrs() \ 3736 ( REG_UDC_EPIntMR = 0xffffffff ) 3737 #define __udc_unmask_all_ep_intrs() \ 3738 ( REG_UDC_EPIntMR = 0x00000000 ) 3739 3740 3741 /* ep0 only CTRL, ep1 only INTR, ep2/3/5/6 only BULK, ep4/7 only ISO */ 3742 #define __udc_config_endpoint_type() \ 3743 do { \ 3744 REG_UDC_EP0InCR = (REG_UDC_EP0InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL; \ 3745 REG_UDC_EP0OutCR = (REG_UDC_EP0OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL; \ 3746 REG_UDC_EP1InCR = (REG_UDC_EP1InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_INTR; \ 3747 REG_UDC_EP2InCR = (REG_UDC_EP2InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ 3748 REG_UDC_EP3InCR = (REG_UDC_EP3InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ 3749 REG_UDC_EP4InCR = (REG_UDC_EP4InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO; \ 3750 REG_UDC_EP5OutCR = (REG_UDC_EP5OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ 3751 REG_UDC_EP6OutCR = (REG_UDC_EP6OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \ 3752 REG_UDC_EP7OutCR = (REG_UDC_EP7OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO; \ 3753 } while (0) 3754 3755 #define __udc_enable_ep0out_snoop_mode() ( REG_UDC_EP0OutCR |= UDC_EPCR_SN ) 3756 #define __udc_enable_ep5out_snoop_mode() ( REG_UDC_EP5OutCR |= UDC_EPCR_SN ) 3757 #define __udc_enable_ep6out_snoop_mode() ( REG_UDC_EP6OutCR |= UDC_EPCR_SN ) 3758 #define __udc_enable_ep7out_snoop_mode() ( REG_UDC_EP7OutCR |= UDC_EPCR_SN ) 3759 3760 #define __udc_disable_ep0out_snoop_mode() ( REG_UDC_EP0OutCR &= ~UDC_EPCR_SN ) 3761 #define __udc_disable_ep5out_snoop_mode() ( REG_UDC_EP5OutCR &= ~UDC_EPCR_SN ) 3762 #define __udc_disable_ep6out_snoop_mode() ( REG_UDC_EP6OutCR &= ~UDC_EPCR_SN ) 3763 #define __udc_disable_ep7out_snoop_mode() ( REG_UDC_EP7OutCR &= ~UDC_EPCR_SN ) 3764 3765 #define __udc_flush_ep0in_fifo() ( REG_UDC_EP0InCR |= UDC_EPCR_F ) 3766 #define __udc_flush_ep1in_fifo() ( REG_UDC_EP1InCR |= UDC_EPCR_F ) 3767 #define __udc_flush_ep2in_fifo() ( REG_UDC_EP2InCR |= UDC_EPCR_F ) 3768 #define __udc_flush_ep3in_fifo() ( REG_UDC_EP3InCR |= UDC_EPCR_F ) 3769 #define __udc_flush_ep4in_fifo() ( REG_UDC_EP4InCR |= UDC_EPCR_F ) 3770 3771 #define __udc_unflush_ep0in_fifo() ( REG_UDC_EP0InCR &= ~UDC_EPCR_F ) 3772 #define __udc_unflush_ep1in_fifo() ( REG_UDC_EP1InCR &= ~UDC_EPCR_F ) 3773 #define __udc_unflush_ep2in_fifo() ( REG_UDC_EP2InCR &= ~UDC_EPCR_F ) 3774 #define __udc_unflush_ep3in_fifo() ( REG_UDC_EP3InCR &= ~UDC_EPCR_F ) 3775 #define __udc_unflush_ep4in_fifo() ( REG_UDC_EP4InCR &= ~UDC_EPCR_F ) 3776 3777 #define __udc_enable_ep0in_stall() ( REG_UDC_EP0InCR |= UDC_EPCR_S ) 3778 #define __udc_enable_ep0out_stall() ( REG_UDC_EP0OutCR |= UDC_EPCR_S ) 3779 #define __udc_enable_ep1in_stall() ( REG_UDC_EP1InCR |= UDC_EPCR_S ) 3780 #define __udc_enable_ep2in_stall() ( REG_UDC_EP2InCR |= UDC_EPCR_S ) 3781 #define __udc_enable_ep3in_stall() ( REG_UDC_EP3InCR |= UDC_EPCR_S ) 3782 #define __udc_enable_ep4in_stall() ( REG_UDC_EP4InCR |= UDC_EPCR_S ) 3783 #define __udc_enable_ep5out_stall() ( REG_UDC_EP5OutCR |= UDC_EPCR_S ) 3784 #define __udc_enable_ep6out_stall() ( REG_UDC_EP6OutCR |= UDC_EPCR_S ) 3785 #define __udc_enable_ep7out_stall() ( REG_UDC_EP7OutCR |= UDC_EPCR_S ) 3786 3787 #define __udc_disable_ep0in_stall() ( REG_UDC_EP0InCR &= ~UDC_EPCR_S ) 3788 #define __udc_disable_ep0out_stall() ( REG_UDC_EP0OutCR &= ~UDC_EPCR_S ) 3789 #define __udc_disable_ep1in_stall() ( REG_UDC_EP1InCR &= ~UDC_EPCR_S ) 3790 #define __udc_disable_ep2in_stall() ( REG_UDC_EP2InCR &= ~UDC_EPCR_S ) 3791 #define __udc_disable_ep3in_stall() ( REG_UDC_EP3InCR &= ~UDC_EPCR_S ) 3792 #define __udc_disable_ep4in_stall() ( REG_UDC_EP4InCR &= ~UDC_EPCR_S ) 3793 #define __udc_disable_ep5out_stall() ( REG_UDC_EP5OutCR &= ~UDC_EPCR_S ) 3794 #define __udc_disable_ep6out_stall() ( REG_UDC_EP6OutCR &= ~UDC_EPCR_S ) 3795 #define __udc_disable_ep7out_stall() ( REG_UDC_EP7OutCR &= ~UDC_EPCR_S ) 3796 3797 3798 #define __udc_ep0out_packet_size() \ 3799 ( (REG_UDC_EP0OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) 3800 #define __udc_ep5out_packet_size() \ 3801 ( (REG_UDC_EP5OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) 3802 #define __udc_ep6out_packet_size() \ 3803 ( (REG_UDC_EP6OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) 3804 #define __udc_ep7out_packet_size() \ 3805 ( (REG_UDC_EP7OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT ) 3806 3807 #define __udc_ep0in_received_intoken() ( (REG_UDC_EP0InSR & UDC_EPSR_IN) ) 3808 #define __udc_ep1in_received_intoken() ( (REG_UDC_EP1InSR & UDC_EPSR_IN) ) 3809 #define __udc_ep2in_received_intoken() ( (REG_UDC_EP2InSR & UDC_EPSR_IN) ) 3810 #define __udc_ep3in_received_intoken() ( (REG_UDC_EP3InSR & UDC_EPSR_IN) ) 3811 #define __udc_ep4in_received_intoken() ( (REG_UDC_EP4InSR & UDC_EPSR_IN) ) 3812 3813 #define __udc_ep0out_received_none() \ 3814 ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) 3815 #define __udc_ep0out_received_data() \ 3816 ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) 3817 #define __udc_ep0out_received_setup() \ 3818 ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) 3819 3820 #define __udc_ep5out_received_none() \ 3821 ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) 3822 #define __udc_ep5out_received_data() \ 3823 ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) 3824 #define __udc_ep5out_received_setup() \ 3825 ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) 3826 3827 #define __udc_ep6out_received_none() \ 3828 ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) 3829 #define __udc_ep6out_received_data() \ 3830 ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) 3831 #define __udc_ep6out_received_setup() \ 3832 ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) 3833 3834 #define __udc_ep7out_received_none() \ 3835 ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE ) 3836 #define __udc_ep7out_received_data() \ 3837 ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA ) 3838 #define __udc_ep7out_received_setup() \ 3839 ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP ) 3840 3841 /* ep7out ISO only */ 3842 #define __udc_ep7out_get_pid() \ 3843 ( (REG_UDC_EP7OutSR & UDC_EPSR_PID_MASK) >> UDC_EPSR_PID_BIT ) 3844 3845 3846 #define __udc_ep0in_set_buffer_size(n) ( REG_UDC_EP0InBSR = (n) ) 3847 #define __udc_ep1in_set_buffer_size(n) ( REG_UDC_EP1InBSR = (n) ) 3848 #define __udc_ep2in_set_buffer_size(n) ( REG_UDC_EP2InBSR = (n) ) 3849 #define __udc_ep3in_set_buffer_size(n) ( REG_UDC_EP3InBSR = (n) ) 3850 #define __udc_ep4in_set_buffer_size(n) ( REG_UDC_EP4InBSR = (n) ) 3851 3852 #define __udc_ep0out_get_frame_number(n) ( UDC_EP0OutPFNR ) 3853 #define __udc_ep5out_get_frame_number(n) ( UDC_EP5OutPFNR ) 3854 #define __udc_ep6out_get_frame_number(n) ( UDC_EP6OutPFNR ) 3855 #define __udc_ep7out_get_frame_number(n) ( UDC_EP7OutPFNR ) 3856 3857 3858 #define __udc_ep0in_set_max_packet_size(n) ( REG_UDC_EP0InMPSR = (n) ) 3859 #define __udc_ep0out_set_max_packet_size(n) ( REG_UDC_EP0OutMPSR = (n) ) 3860 #define __udc_ep1in_set_max_packet_size(n) ( REG_UDC_EP1InMPSR = (n) ) 3861 #define __udc_ep2in_set_max_packet_size(n) ( REG_UDC_EP2InMPSR = (n) ) 3862 #define __udc_ep3in_set_max_packet_size(n) ( REG_UDC_EP3InMPSR = (n) ) 3863 #define __udc_ep4in_set_max_packet_size(n) ( REG_UDC_EP4InMPSR = (n) ) 3864 #define __udc_ep5out_set_max_packet_size(n) ( REG_UDC_EP5OutMPSR = (n) ) 3865 #define __udc_ep6out_set_max_packet_size(n) ( REG_UDC_EP6OutMPSR = (n) ) 3866 #define __udc_ep7out_set_max_packet_size(n) ( REG_UDC_EP7OutMPSR = (n) ) 3867 3868 /* set to 0xFFFF for UDC */ 3869 #define __udc_set_setup_command_address(n) ( REG_UDC_STCMAR = (n) ) 3870 3871 /* Init and configure EPxInfR(x=0,1,2,3,4,5,6,7) 3872 * c: Configuration number to which this endpoint belongs 3873 * i: Interface number to which this endpoint belongs 3874 * a: Alternate setting to which this endpoint belongs 3875 * p: max Packet size of this endpoint 3876 */ 3877 3878 #define __udc_ep0info_init(c,i,a,p) \ 3879 do { \ 3880 REG_UDC_EP0InfR &= ~UDC_EPInfR_MPS_MASK; \ 3881 REG_UDC_EP0InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ 3882 REG_UDC_EP0InfR &= ~UDC_EPInfR_ALTS_MASK; \ 3883 REG_UDC_EP0InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ 3884 REG_UDC_EP0InfR &= ~UDC_EPInfR_IFN_MASK; \ 3885 REG_UDC_EP0InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ 3886 REG_UDC_EP0InfR &= ~UDC_EPInfR_CGN_MASK; \ 3887 REG_UDC_EP0InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ 3888 REG_UDC_EP0InfR &= ~UDC_EPInfR_EPT_MASK; \ 3889 REG_UDC_EP0InfR |= UDC_EPInfR_EPT_CTRL; \ 3890 REG_UDC_EP0InfR &= ~UDC_EPInfR_EPD; \ 3891 REG_UDC_EP0InfR |= UDC_EPInfR_EPD_OUT; \ 3892 REG_UDC_EP0InfR &= ~UDC_EPInfR_EPN_MASK; \ 3893 REG_UDC_EP0InfR |= (0 << UDC_EPInfR_EPN_BIT); \ 3894 } while (0) 3895 3896 #define __udc_ep1info_init(c,i,a,p) \ 3897 do { \ 3898 REG_UDC_EP1InfR &= ~UDC_EPInfR_MPS_MASK; \ 3899 REG_UDC_EP1InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ 3900 REG_UDC_EP1InfR &= ~UDC_EPInfR_ALTS_MASK; \ 3901 REG_UDC_EP1InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ 3902 REG_UDC_EP1InfR &= ~UDC_EPInfR_IFN_MASK; \ 3903 REG_UDC_EP1InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ 3904 REG_UDC_EP1InfR &= ~UDC_EPInfR_CGN_MASK; \ 3905 REG_UDC_EP1InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ 3906 REG_UDC_EP1InfR &= ~UDC_EPInfR_EPT_MASK; \ 3907 REG_UDC_EP1InfR |= UDC_EPInfR_EPT_INTR; \ 3908 REG_UDC_EP1InfR &= ~UDC_EPInfR_EPD; \ 3909 REG_UDC_EP1InfR |= UDC_EPInfR_EPD_IN; \ 3910 REG_UDC_EP1InfR &= ~UDC_EPInfR_EPN_MASK; \ 3911 REG_UDC_EP1InfR |= (1 << UDC_EPInfR_EPN_BIT); \ 3912 } while (0) 3913 3914 #define __udc_ep2info_init(c,i,a,p) \ 3915 do { \ 3916 REG_UDC_EP2InfR &= ~UDC_EPInfR_MPS_MASK; \ 3917 REG_UDC_EP2InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ 3918 REG_UDC_EP2InfR &= ~UDC_EPInfR_ALTS_MASK; \ 3919 REG_UDC_EP2InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ 3920 REG_UDC_EP2InfR &= ~UDC_EPInfR_IFN_MASK; \ 3921 REG_UDC_EP2InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ 3922 REG_UDC_EP2InfR &= ~UDC_EPInfR_CGN_MASK; \ 3923 REG_UDC_EP2InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ 3924 REG_UDC_EP2InfR &= ~UDC_EPInfR_EPT_MASK; \ 3925 REG_UDC_EP2InfR |= UDC_EPInfR_EPT_BULK; \ 3926 REG_UDC_EP2InfR &= ~UDC_EPInfR_EPD; \ 3927 REG_UDC_EP2InfR |= UDC_EPInfR_EPD_IN; \ 3928 REG_UDC_EP2InfR &= ~UDC_EPInfR_EPN_MASK; \ 3929 REG_UDC_EP2InfR |= (2 << UDC_EPInfR_EPN_BIT); \ 3930 } while (0) 3931 3932 #define __udc_ep3info_init(c,i,a,p) \ 3933 do { \ 3934 REG_UDC_EP3InfR &= ~UDC_EPInfR_MPS_MASK; \ 3935 REG_UDC_EP3InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ 3936 REG_UDC_EP3InfR &= ~UDC_EPInfR_ALTS_MASK; \ 3937 REG_UDC_EP3InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ 3938 REG_UDC_EP3InfR &= ~UDC_EPInfR_IFN_MASK; \ 3939 REG_UDC_EP3InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ 3940 REG_UDC_EP3InfR &= ~UDC_EPInfR_CGN_MASK; \ 3941 REG_UDC_EP3InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ 3942 REG_UDC_EP3InfR &= ~UDC_EPInfR_EPT_MASK; \ 3943 REG_UDC_EP3InfR |= UDC_EPInfR_EPT_BULK; \ 3944 REG_UDC_EP3InfR &= ~UDC_EPInfR_EPD; \ 3945 REG_UDC_EP3InfR |= UDC_EPInfR_EPD_IN; \ 3946 REG_UDC_EP3InfR &= ~UDC_EPInfR_EPN_MASK; \ 3947 REG_UDC_EP3InfR |= (3 << UDC_EPInfR_EPN_BIT); \ 3948 } while (0) 3949 3950 #define __udc_ep4info_init(c,i,a,p) \ 3951 do { \ 3952 REG_UDC_EP4InfR &= ~UDC_EPInfR_MPS_MASK; \ 3953 REG_UDC_EP4InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ 3954 REG_UDC_EP4InfR &= ~UDC_EPInfR_ALTS_MASK; \ 3955 REG_UDC_EP4InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ 3956 REG_UDC_EP4InfR &= ~UDC_EPInfR_IFN_MASK; \ 3957 REG_UDC_EP4InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ 3958 REG_UDC_EP4InfR &= ~UDC_EPInfR_CGN_MASK; \ 3959 REG_UDC_EP4InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ 3960 REG_UDC_EP4InfR &= ~UDC_EPInfR_EPT_MASK; \ 3961 REG_UDC_EP4InfR |= UDC_EPInfR_EPT_ISO; \ 3962 REG_UDC_EP4InfR &= ~UDC_EPInfR_EPD; \ 3963 REG_UDC_EP4InfR |= UDC_EPInfR_EPD_IN; \ 3964 REG_UDC_EP4InfR &= ~UDC_EPInfR_EPN_MASK; \ 3965 REG_UDC_EP4InfR |= (4 << UDC_EPInfR_EPN_BIT); \ 3966 } while (0) 3967 3968 #define __udc_ep5info_init(c,i,a,p) \ 3969 do { \ 3970 REG_UDC_EP5InfR &= ~UDC_EPInfR_MPS_MASK; \ 3971 REG_UDC_EP5InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ 3972 REG_UDC_EP5InfR &= ~UDC_EPInfR_ALTS_MASK; \ 3973 REG_UDC_EP5InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ 3974 REG_UDC_EP5InfR &= ~UDC_EPInfR_IFN_MASK; \ 3975 REG_UDC_EP5InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ 3976 REG_UDC_EP5InfR &= ~UDC_EPInfR_CGN_MASK; \ 3977 REG_UDC_EP5InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ 3978 REG_UDC_EP5InfR &= ~UDC_EPInfR_EPT_MASK; \ 3979 REG_UDC_EP5InfR |= UDC_EPInfR_EPT_BULK; \ 3980 REG_UDC_EP5InfR &= ~UDC_EPInfR_EPD; \ 3981 REG_UDC_EP5InfR |= UDC_EPInfR_EPD_OUT; \ 3982 REG_UDC_EP5InfR &= ~UDC_EPInfR_EPN_MASK; \ 3983 REG_UDC_EP5InfR |= (5 << UDC_EPInfR_EPN_BIT); \ 3984 } while (0) 3985 3986 #define __udc_ep6info_init(c,i,a,p) \ 3987 do { \ 3988 REG_UDC_EP6InfR &= ~UDC_EPInfR_MPS_MASK; \ 3989 REG_UDC_EP6InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ 3990 REG_UDC_EP6InfR &= ~UDC_EPInfR_ALTS_MASK; \ 3991 REG_UDC_EP6InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ 3992 REG_UDC_EP6InfR &= ~UDC_EPInfR_IFN_MASK; \ 3993 REG_UDC_EP6InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ 3994 REG_UDC_EP6InfR &= ~UDC_EPInfR_CGN_MASK; \ 3995 REG_UDC_EP6InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ 3996 REG_UDC_EP6InfR &= ~UDC_EPInfR_EPT_MASK; \ 3997 REG_UDC_EP6InfR |= UDC_EPInfR_EPT_BULK; \ 3998 REG_UDC_EP6InfR &= ~UDC_EPInfR_EPD; \ 3999 REG_UDC_EP6InfR |= UDC_EPInfR_EPD_OUT; \ 4000 REG_UDC_EP6InfR &= ~UDC_EPInfR_EPN_MASK; \ 4001 REG_UDC_EP6InfR |= (6 << UDC_EPInfR_EPN_BIT); \ 4002 } while (0) 4003 4004 #define __udc_ep7info_init(c,i,a,p) \ 4005 do { \ 4006 REG_UDC_EP7InfR &= ~UDC_EPInfR_MPS_MASK; \ 4007 REG_UDC_EP7InfR |= ((p) << UDC_EPInfR_MPS_BIT); \ 4008 REG_UDC_EP7InfR &= ~UDC_EPInfR_ALTS_MASK; \ 4009 REG_UDC_EP7InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \ 4010 REG_UDC_EP7InfR &= ~UDC_EPInfR_IFN_MASK; \ 4011 REG_UDC_EP7InfR |= ((i) << UDC_EPInfR_IFN_BIT); \ 4012 REG_UDC_EP7InfR &= ~UDC_EPInfR_CGN_MASK; \ 4013 REG_UDC_EP7InfR |= ((c) << UDC_EPInfR_CGN_BIT); \ 4014 REG_UDC_EP7InfR &= ~UDC_EPInfR_EPT_MASK; \ 4015 REG_UDC_EP7InfR |= UDC_EPInfR_EPT_ISO; \ 4016 REG_UDC_EP7InfR &= ~UDC_EPInfR_EPD; \ 4017 REG_UDC_EP7InfR |= UDC_EPInfR_EPD_OUT; \ 4018 REG_UDC_EP7InfR &= ~UDC_EPInfR_EPN_MASK; \ 4019 REG_UDC_EP7InfR |= (7 << UDC_EPInfR_EPN_BIT); \ 4020 } while (0) 4021 4022 4023 /*************************************************************************** 4024 * DMAC 4025 ***************************************************************************/ 4026 4027 /* n is the DMA channel (0 - 7) */ 4028 4029 #define __dmac_enable_all_channels() \ 4030 ( REG_DMAC_DMACR |= DMAC_DMACR_DME | DMAC_DMACR_PR_ROUNDROBIN ) 4031 #define __dmac_disable_all_channels() \ 4032 ( REG_DMAC_DMACR &= ~DMAC_DMACR_DME ) 4033 4034 /* p=0,1,2,3 */ 4035 #define __dmac_set_priority(p) \ 4036 do { \ 4037 REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \ 4038 REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \ 4039 } while (0) 4040 4041 #define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HTR ) 4042 #define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AER ) 4043 4044 #define __dmac_enable_channel(n) \ 4045 ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_CHDE ) 4046 #define __dmac_disable_channel(n) \ 4047 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_CHDE ) 4048 #define __dmac_channel_enabled(n) \ 4049 ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_CHDE ) 4050 4051 #define __dmac_channel_enable_irq(n) \ 4052 ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_TCIE ) 4053 #define __dmac_channel_disable_irq(n) \ 4054 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TCIE ) 4055 4056 #define __dmac_channel_transmit_halt_detected(n) \ 4057 ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_HLT ) 4058 #define __dmac_channel_transmit_end_detected(n) \ 4059 ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_TC ) 4060 #define __dmac_channel_address_error_detected(n) \ 4061 ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_AR ) 4062 4063 #define __dmac_channel_clear_transmit_halt(n) \ 4064 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT ) 4065 #define __dmac_channel_clear_transmit_end(n) \ 4066 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TC ) 4067 #define __dmac_channel_clear_address_error(n) \ 4068 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR ) 4069 4070 #define __dmac_channel_set_single_mode(n) \ 4071 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TM ) 4072 #define __dmac_channel_set_block_mode(n) \ 4073 ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_TM ) 4074 4075 #define __dmac_channel_set_transfer_unit_32bit(n) \ 4076 do { \ 4077 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ 4078 REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_32b; \ 4079 } while (0) 4080 4081 #define __dmac_channel_set_transfer_unit_16bit(n) \ 4082 do { \ 4083 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ 4084 REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_16b; \ 4085 } while (0) 4086 4087 #define __dmac_channel_set_transfer_unit_8bit(n) \ 4088 do { \ 4089 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ 4090 REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_8b; \ 4091 } while (0) 4092 4093 #define __dmac_channel_set_transfer_unit_16byte(n) \ 4094 do { \ 4095 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ 4096 REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_16B; \ 4097 } while (0) 4098 4099 #define __dmac_channel_set_transfer_unit_32byte(n) \ 4100 do { \ 4101 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \ 4102 REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_32B; \ 4103 } while (0) 4104 4105 /* w=8,16,32 */ 4106 #define __dmac_channel_set_dest_port_width(n,w) \ 4107 do { \ 4108 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DWDH_MASK; \ 4109 REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DWDH_##w; \ 4110 } while (0) 4111 4112 /* w=8,16,32 */ 4113 #define __dmac_channel_set_src_port_width(n,w) \ 4114 do { \ 4115 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SWDH_MASK; \ 4116 REG_DMAC_DCCSR(n) |= DMAC_DCCSR_SWDH_##w; \ 4117 } while (0) 4118 4119 /* v=0-15 */ 4120 #define __dmac_channel_set_rdil(n,v) \ 4121 do { \ 4122 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_RDIL_MASK; \ 4123 REG_DMAC_DCCSR(n) |= ((v) << DMAC_DCCSR_RDIL_BIT); \ 4124 } while (0) 4125 4126 #define __dmac_channel_dest_addr_fixed(n) \ 4127 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DAM ) 4128 #define __dmac_channel_dest_addr_increment(n) \ 4129 ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DAM ) 4130 4131 #define __dmac_channel_src_addr_fixed(n) \ 4132 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SAM ) 4133 #define __dmac_channel_src_addr_increment(n) \ 4134 ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_SAM ) 4135 4136 #define __dmac_channel_set_eop_high(n) \ 4137 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EOPM ) 4138 #define __dmac_channel_set_eop_low(n) \ 4139 ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EOPM ) 4140 4141 #define __dmac_channel_set_erdm(n,m) \ 4142 do { \ 4143 REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SWDH_MASK; \ 4144 REG_DMAC_DCCSR(n) |= ((m) << DMAC_DCCSR_ERDM_BIT); \ 4145 } while (0) 4146 4147 #define __dmac_channel_set_eackm(n) \ 4148 ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EACKM ) 4149 #define __dmac_channel_clear_eackm(n) \ 4150 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKM ) 4151 4152 #define __dmac_channel_set_eacks(n) \ 4153 ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EACKS ) 4154 #define __dmac_channel_clear_eacks(n) \ 4155 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKS ) 4156 4157 4158 #define __dmac_channel_irq_detected(n) \ 4159 ( REG_DMAC_DCCSR(n) & (DMAC_DCCSR_TC | DMAC_DCCSR_AR) ) 4160 4161 static __inline__ int __dmac_get_irq(void) 4162 { 4163 int i; 4164 for (i=0;i<NUM_DMA;i++) 4165 if (__dmac_channel_irq_detected(i)) 4166 return i; 4167 return -1; 4168 } 4169 4170 /*************************************************************************** 4171 * AIC (AC'97 & I2S Controller) 4172 ***************************************************************************/ 4173 4174 #define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) 4175 #define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) 4176 #define __aic_reset() ( REG_AIC_FR |= AIC_FR_RST ) 4177 #define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) 4178 #define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) 4179 4180 #define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) 4181 #define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) 4182 4183 #define __aic_set_transmit_trigger(n) \ 4184 do { \ 4185 REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ 4186 REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \ 4187 } while(0) 4188 4189 #define __aic_set_receive_trigger(n) \ 4190 do { \ 4191 REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ 4192 REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \ 4193 } while(0) 4194 4195 #define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) 4196 #define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) 4197 #define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) 4198 #define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) 4199 #define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) 4200 #define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) 4201 4202 #define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH ) 4203 #define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH ) 4204 4205 #define __aic_enable_transmit_intr() \ 4206 ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) 4207 #define __aic_disable_transmit_intr() \ 4208 ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) 4209 #define __aic_enable_receive_intr() \ 4210 ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) 4211 #define __aic_disable_receive_intr() \ 4212 ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) 4213 4214 #define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) 4215 #define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) 4216 #define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) 4217 #define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) 4218 4219 #define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3 4220 #define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4 4221 #define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6 4222 #define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7 4223 #define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8 4224 #define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9 4225 4226 #define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3 4227 #define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4 4228 #define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6 4229 #define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7 4230 #define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8 4231 #define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9 4232 4233 #define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) 4234 #define __ac97_set_xs_mono() \ 4235 do { \ 4236 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ 4237 REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ 4238 } while(0) 4239 #define __ac97_set_xs_stereo() \ 4240 do { \ 4241 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ 4242 REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ 4243 } while(0) 4244 4245 /* In fact, only stereo is support now. */ 4246 #define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) 4247 #define __ac97_set_rs_mono() \ 4248 do { \ 4249 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ 4250 REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ 4251 } while(0) 4252 #define __ac97_set_rs_stereo() \ 4253 do { \ 4254 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ 4255 REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ 4256 } while(0) 4257 4258 #define __ac97_warm_reset_codec() \ 4259 do { \ 4260 REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ 4261 REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ 4262 udelay(1); \ 4263 REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ 4264 REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ 4265 } while (0) 4266 4267 //#define Jz_AC97_RESET_BUG 1 4268 #ifndef Jz_AC97_RESET_BUG 4269 #define __ac97_cold_reset_codec() \ 4270 do { \ 4271 REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ 4272 REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ 4273 REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ 4274 udelay(1); \ 4275 REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ 4276 REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ 4277 } while (0) 4278 #else 4279 #define __ac97_cold_reset_codec() \ 4280 do { \ 4281 __gpio_as_output(111); /* SDATA_OUT */ \ 4282 __gpio_as_output(110); /* SDATA_IN */ \ 4283 __gpio_as_output(112); /* SYNC */ \ 4284 __gpio_as_output(114); /* RESET# */ \ 4285 __gpio_clear_pin(111); \ 4286 __gpio_clear_pin(110); \ 4287 __gpio_clear_pin(112); \ 4288 __gpio_clear_pin(114); \ 4289 udelay(2); \ 4290 __gpio_set_pin(114); \ 4291 udelay(1); \ 4292 __gpio_as_ac97(); \ 4293 } while (0) 4294 #endif 4295 4296 /* n=8,16,18,20 */ 4297 #define __ac97_set_iass(n) \ 4298 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) 4299 #define __ac97_set_oass(n) \ 4300 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) 4301 4302 #define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) 4303 #define __i2s_select_left_justified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) 4304 4305 /* n=8,16,18,20,24 */ 4306 #define __i2s_set_sample_size(n) \ 4307 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT ) 4308 4309 #define __i2s_stop_clock() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) 4310 #define __i2s_start_clock() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) 4311 4312 #define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) 4313 #define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) 4314 #define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) 4315 #define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) 4316 4317 #define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) 4318 4319 #define __aic_get_transmit_resident() \ 4320 ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT ) 4321 #define __aic_get_receive_count() \ 4322 ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT ) 4323 4324 #define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) 4325 #define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) 4326 #define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) 4327 #define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) 4328 #define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) 4329 4330 #define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) 4331 4332 #define CODEC_READ_CMD (1 << 19) 4333 #define CODEC_WRITE_CMD (0 << 19) 4334 #define CODEC_REG_INDEX_BIT 12 4335 #define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */ 4336 #define CODEC_REG_DATA_BIT 4 4337 #define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */ 4338 4339 #define __ac97_out_rcmd_addr(reg) \ 4340 do { \ 4341 REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ 4342 } while (0) 4343 4344 #define __ac97_out_wcmd_addr(reg) \ 4345 do { \ 4346 REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \ 4347 } while (0) 4348 4349 #define __ac97_out_data(value) \ 4350 do { \ 4351 REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \ 4352 } while (0) 4353 4354 #define __ac97_in_data() \ 4355 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT ) 4356 4357 #define __ac97_in_status_addr() \ 4358 ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT ) 4359 4360 #define __i2s_set_sample_rate(i2sclk, sync) \ 4361 ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) 4362 4363 #define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) 4364 #define __aic_read_rfifo() ( REG_AIC_DR ) 4365 4366 // 4367 // Define next ops for AC97 compatible 4368 // 4369 4370 #define AC97_ACSR AIC_ACSR 4371 4372 #define __ac97_enable() __aic_enable(); __aic_select_ac97() 4373 #define __ac97_disable() __aic_disable() 4374 #define __ac97_reset() __aic_reset() 4375 4376 #define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) 4377 #define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) 4378 4379 #define __ac97_enable_record() __aic_enable_record() 4380 #define __ac97_disable_record() __aic_disable_record() 4381 #define __ac97_enable_replay() __aic_enable_replay() 4382 #define __ac97_disable_replay() __aic_disable_replay() 4383 #define __ac97_enable_loopback() __aic_enable_loopback() 4384 #define __ac97_disable_loopback() __aic_disable_loopback() 4385 4386 #define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() 4387 #define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() 4388 #define __ac97_enable_receive_dma() __aic_enable_receive_dma() 4389 #define __ac97_disable_receive_dma() __aic_disable_receive_dma() 4390 4391 #define __ac97_transmit_request() __aic_transmit_request() 4392 #define __ac97_receive_request() __aic_receive_request() 4393 #define __ac97_transmit_underrun() __aic_transmit_underrun() 4394 #define __ac97_receive_overrun() __aic_receive_overrun() 4395 4396 #define __ac97_clear_errors() __aic_clear_errors() 4397 4398 #define __ac97_get_transmit_resident() __aic_get_transmit_resident() 4399 #define __ac97_get_receive_count() __aic_get_receive_count() 4400 4401 #define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() 4402 #define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() 4403 #define __ac97_enable_receive_intr() __aic_enable_receive_intr() 4404 #define __ac97_disable_receive_intr() __aic_disable_receive_intr() 4405 4406 #define __ac97_write_tfifo(v) __aic_write_tfifo(v) 4407 #define __ac97_read_rfifo() __aic_read_rfifo() 4408 4409 // 4410 // Define next ops for I2S compatible 4411 // 4412 4413 #define I2S_ACSR AIC_I2SSR 4414 4415 #define __i2s_enable() __aic_enable(); __aic_select_i2s() 4416 #define __i2s_disable() __aic_disable() 4417 #define __i2s_reset() __aic_reset() 4418 4419 #define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) 4420 #define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) 4421 4422 #define __i2s_enable_record() __aic_enable_record() 4423 #define __i2s_disable_record() __aic_disable_record() 4424 #define __i2s_enable_replay() __aic_enable_replay() 4425 #define __i2s_disable_replay() __aic_disable_replay() 4426 #define __i2s_enable_loopback() __aic_enable_loopback() 4427 #define __i2s_disable_loopback() __aic_disable_loopback() 4428 4429 #define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() 4430 #define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() 4431 #define __i2s_enable_receive_dma() __aic_enable_receive_dma() 4432 #define __i2s_disable_receive_dma() __aic_disable_receive_dma() 4433 4434 #define __i2s_transmit_request() __aic_transmit_request() 4435 #define __i2s_receive_request() __aic_receive_request() 4436 #define __i2s_transmit_underrun() __aic_transmit_underrun() 4437 #define __i2s_receive_overrun() __aic_receive_overrun() 4438 4439 #define __i2s_clear_errors() __aic_clear_errors() 4440 4441 #define __i2s_get_transmit_resident() __aic_get_transmit_resident() 4442 #define __i2s_get_receive_count() __aic_get_receive_count() 4443 4444 #define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() 4445 #define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() 4446 #define __i2s_enable_receive_intr() __aic_enable_receive_intr() 4447 #define __i2s_disable_receive_intr() __aic_disable_receive_intr() 4448 4449 #define __i2s_write_tfifo(v) __aic_write_tfifo(v) 4450 #define __i2s_read_rfifo() __aic_read_rfifo() 4451 4452 #define __i2s_reset_codec() \ 4453 do { \ 4454 __gpio_as_output(111); /* SDATA_OUT */ \ 4455 __gpio_as_input(110); /* SDATA_IN */ \ 4456 __gpio_as_output(112); /* SYNC */ \ 4457 __gpio_as_output(114); /* RESET# */ \ 4458 __gpio_clear_pin(111); \ 4459 __gpio_clear_pin(110); \ 4460 __gpio_clear_pin(112); \ 4461 __gpio_clear_pin(114); \ 4462 __gpio_as_i2s_master(); \ 4463 } while (0) 4464 4465 4466 /*************************************************************************** 4467 * LCD 4468 ***************************************************************************/ 4469 4470 /* Register operations using absolute positioning have been removed. */ 4471 4472 /*************************************************************************** 4473 * DES 4474 ***************************************************************************/ 4475 4476 4477 /*************************************************************************** 4478 * CPM 4479 ***************************************************************************/ 4480 #define __cpm_plcr1_fd() \ 4481 ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT) 4482 #define __cpm_plcr1_rd() \ 4483 ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT) 4484 #define __cpm_plcr1_od() \ 4485 ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT) 4486 #define __cpm_cfcr_mfr() \ 4487 ((REG_CPM_CFCR & CPM_CFCR_MFR_MASK) >> CPM_CFCR_MFR_BIT) 4488 #define __cpm_cfcr_pfr() \ 4489 ((REG_CPM_CFCR & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT) 4490 #define __cpm_cfcr_sfr() \ 4491 ((REG_CPM_CFCR & CPM_CFCR_SFR_MASK) >> CPM_CFCR_SFR_BIT) 4492 #define __cpm_cfcr_ifr() \ 4493 ((REG_CPM_CFCR & CPM_CFCR_IFR_MASK) >> CPM_CFCR_IFR_BIT) 4494 4495 static __inline__ unsigned int __cpm_divisor_encode(unsigned int n) 4496 { 4497 unsigned int encode[10] = {1,2,3,4,6,8,12,16,24,32}; 4498 int i; 4499 for (i=0;i<10;i++) 4500 if (n < encode[i]) 4501 break; 4502 return i; 4503 } 4504 4505 #define __cpm_set_mclk_div(n) \ 4506 do { \ 4507 REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_MFR_MASK) | \ 4508 ((n) << (CPM_CFCR_MFR_BIT)); \ 4509 } while (0) 4510 4511 #define __cpm_set_pclk_div(n) \ 4512 do { \ 4513 REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_PFR_MASK) | \ 4514 ((n) << (CPM_CFCR_PFR_BIT)); \ 4515 } while (0) 4516 4517 #define __cpm_set_sclk_div(n) \ 4518 do { \ 4519 REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_SFR_MASK) | \ 4520 ((n) << (CPM_CFCR_SFR_BIT)); \ 4521 } while (0) 4522 4523 #define __cpm_set_iclk_div(n) \ 4524 do { \ 4525 REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_IFR_MASK) | \ 4526 ((n) << (CPM_CFCR_IFR_BIT)); \ 4527 } while (0) 4528 4529 #define __cpm_set_lcdclk_div(n) \ 4530 do { \ 4531 REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_LFR_MASK) | \ 4532 ((n) << (CPM_CFCR_LFR_BIT)); \ 4533 } while (0) 4534 4535 #define __cpm_enable_cko1() (REG_CPM_CFCR |= CPM_CFCR_CKOEN1) 4536 #define __cpm_enable_cko2() (REG_CPM_CFCR |= CPM_CFCR_CKOEN2) 4537 #define __cpm_disable_cko1() (REG_CPM_CFCR &= ~CPM_CFCR_CKOEN1) 4538 #define __cpm_disable_cko2() (REG_CPM_CFCR &= ~CPM_CFCR_CKOEN2) 4539 4540 #define __cpm_idle_mode() \ 4541 (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \ 4542 CPM_LPCR_LPM_IDLE) 4543 #define __cpm_sleep_mode() \ 4544 (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \ 4545 CPM_LPCR_LPM_SLEEP) 4546 #define __cpm_hibernate_mode() \ 4547 (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \ 4548 CPM_LPCR_LPM_HIBERNATE) 4549 4550 #define __cpm_start_uart0() \ 4551 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART0)) 4552 #define __cpm_start_uart1() \ 4553 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART1)) 4554 #define __cpm_start_uart2() \ 4555 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART2)) 4556 #define __cpm_start_uart3() \ 4557 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART3)) 4558 #define __cpm_start_ost() \ 4559 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_OST)) 4560 #define __cpm_start_dmac() \ 4561 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_DMAC)) 4562 #define __cpm_start_uhc() \ 4563 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UHC)) 4564 #define __cpm_start_lcd() \ 4565 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_LCD)) 4566 #define __cpm_start_i2c() \ 4567 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_I2C)) 4568 #define __cpm_start_aic_pclk() \ 4569 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_AICPCLK)) 4570 #define __cpm_start_aic_bitclk() \ 4571 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_AICBCLK)) 4572 #define __cpm_start_pwm0() \ 4573 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_PWM0)) 4574 #define __cpm_start_pwm1() \ 4575 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_PWM1)) 4576 #define __cpm_start_ssi() \ 4577 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_SSI)) 4578 #define __cpm_start_msc() \ 4579 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_MSC)) 4580 #define __cpm_start_scc() \ 4581 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_SCC)) 4582 #define __cpm_start_eth() \ 4583 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_ETH)) 4584 #define __cpm_start_kbc() \ 4585 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_KBC)) 4586 #define __cpm_start_cim() \ 4587 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_CIM)) 4588 #define __cpm_start_udc() \ 4589 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UDC)) 4590 #define __cpm_start_uprt() \ 4591 (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UPRT)) 4592 #define __cpm_start_all() (REG_CPM_MSCR = 0) 4593 4594 #define __cpm_stop_uart0() \ 4595 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART0)) 4596 #define __cpm_stop_uart1() \ 4597 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART1)) 4598 #define __cpm_stop_uart2() \ 4599 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART2)) 4600 #define __cpm_stop_uart3() \ 4601 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART3)) 4602 #define __cpm_stop_ost() \ 4603 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_OST)) 4604 #define __cpm_stop_dmac() \ 4605 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_DMAC)) 4606 #define __cpm_stop_uhc() \ 4607 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UHC)) 4608 #define __cpm_stop_lcd() \ 4609 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_LCD)) 4610 #define __cpm_stop_i2c() \ 4611 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_I2C)) 4612 #define __cpm_stop_aic_pclk() \ 4613 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_AICPCLK)) 4614 #define __cpm_stop_aic_bitclk() \ 4615 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_AICBCLK)) 4616 #define __cpm_stop_pwm0() \ 4617 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_PWM0)) 4618 #define __cpm_stop_pwm1() \ 4619 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_PWM1)) 4620 #define __cpm_stop_ssi() \ 4621 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_SSI)) 4622 #define __cpm_stop_msc() \ 4623 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_MSC)) 4624 #define __cpm_stop_scc() \ 4625 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_SCC)) 4626 #define __cpm_stop_eth() \ 4627 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_ETH)) 4628 #define __cpm_stop_kbc() \ 4629 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_KBC)) 4630 #define __cpm_stop_cim() \ 4631 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_CIM)) 4632 #define __cpm_stop_udc() \ 4633 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UDC)) 4634 #define __cpm_stop_uprt() \ 4635 (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UPRT)) 4636 #define __cpm_stop_all() (REG_CPM_MSCR = 0xffffffff) 4637 4638 #define __cpm_set_pin(n) \ 4639 do { \ 4640 unsigned int p, o; \ 4641 p = (n) / 32; \ 4642 o = (n) % 32; \ 4643 if (p == 0) \ 4644 REG_CPM_GSR0 |= (1 << o); \ 4645 else if (p == 1) \ 4646 REG_CPM_GSR1 |= (1 << o); \ 4647 else if (p == 2) \ 4648 REG_CPM_GSR2 |= (1 << o); \ 4649 else if (p == 3) \ 4650 REG_CPM_GSR3 |= (1 << o); \ 4651 } while (0) 4652 4653 #define __cpm_clear_pin(n) \ 4654 do { \ 4655 unsigned int p, o; \ 4656 p = (n) / 32; \ 4657 o = (n) % 32; \ 4658 if (p == 0) \ 4659 REG_CPM_GSR0 &= ~(1 << o); \ 4660 else if (p == 1) \ 4661 REG_CPM_GSR1 &= ~(1 << o); \ 4662 else if (p == 2) \ 4663 REG_CPM_GSR2 &= ~(1 << o); \ 4664 else if (p == 3) \ 4665 REG_CPM_GSR3 &= ~(1 << o); \ 4666 } while (0) 4667 4668 4669 #define __cpm_select_msc_clk(type) \ 4670 do { \ 4671 if (type == 0) \ 4672 REG_CPM_CFCR &= ~CPM_CFCR_MSC; \ 4673 else \ 4674 REG_CPM_CFCR |= CPM_CFCR_MSC; \ 4675 REG_CPM_CFCR |= CPM_CFCR_UPE; \ 4676 } while(0) 4677 4678 4679 /*************************************************************************** 4680 * SSI 4681 ***************************************************************************/ 4682 4683 #define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE ) 4684 #define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE ) 4685 #define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL ) 4686 4687 #define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK ) 4688 4689 #define __ssi_select_ce2() \ 4690 do { \ 4691 REG_SSI_CR0 |= SSI_CR0_FSEL; \ 4692 REG_SSI_CR1 &= ~SSI_CR1_MULTS; \ 4693 } while (0) 4694 4695 #define __ssi_select_gpc() \ 4696 do { \ 4697 REG_SSI_CR0 &= ~SSI_CR0_FSEL; \ 4698 REG_SSI_CR1 |= SSI_CR1_MULTS; \ 4699 } while (0) 4700 4701 #define __ssi_enable_tx_intr() \ 4702 ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE ) 4703 4704 #define __ssi_disable_tx_intr() \ 4705 ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) ) 4706 4707 #define __ssi_enable_rx_intr() \ 4708 ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE ) 4709 4710 #define __ssi_disable_rx_intr() \ 4711 ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) ) 4712 4713 #define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP ) 4714 #define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP ) 4715 4716 #define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV ) 4717 #define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV ) 4718 4719 #define __ssi_finish_receive() \ 4720 ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) ) 4721 4722 #define __ssi_disable_recvfinish() \ 4723 ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) ) 4724 4725 #define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH ) 4726 #define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH ) 4727 4728 #define __ssi_flush_fifo() \ 4729 ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH ) 4730 4731 #define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN ) 4732 4733 /* Motorola's SPI format, set 1 delay */ 4734 #define __ssi_spi_format() \ 4735 do { \ 4736 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ 4737 REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \ 4738 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ 4739 REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \ 4740 } while (0) 4741 4742 /* TI's SSP format, must clear SSI_CR1.UNFIN */ 4743 #define __ssi_ssp_format() \ 4744 do { \ 4745 REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \ 4746 REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \ 4747 } while (0) 4748 4749 /* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */ 4750 #define __ssi_microwire_format() \ 4751 do { \ 4752 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \ 4753 REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \ 4754 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\ 4755 REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \ 4756 REG_SSI_CR0 &= ~SSI_CR0_RFINE; \ 4757 } while (0) 4758 4759 /* CE# level (FRMHL), CE# in interval time (ITFRM), 4760 clock phase and polarity (PHA POL), 4761 interval time (SSIITR), interval characters/frame (SSIICR) */ 4762 4763 /* frmhl,endian,mcom,flen,pha,pol MASK */ 4764 #define SSICR1_MISC_MASK \ 4765 ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \ 4766 | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \ 4767 4768 #define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \ 4769 do { \ 4770 REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \ 4771 REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \ 4772 (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \ 4773 ((pha) << 1) | (pol); \ 4774 } while(0) 4775 4776 /* Transfer with MSB or LSB first */ 4777 #define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST ) 4778 #define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST ) 4779 4780 /* n = 2 - 17 */ 4781 #define __ssi_set_frame_length(n) \ 4782 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | SSI_CR1_FLEN_##n##BIT) ) 4783 4784 /* n = 1 - 16 */ 4785 #define __ssi_set_microwire_command_length(n) \ 4786 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) ) 4787 4788 /* Set the clock phase for SPI */ 4789 #define __ssi_set_spi_clock_phase(n) \ 4790 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) ) 4791 4792 /* Set the clock polarity for SPI */ 4793 #define __ssi_set_spi_clock_polarity(n) \ 4794 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) ) 4795 4796 /* n = 1,4,8,14 */ 4797 #define __ssi_set_tx_trigger(n) \ 4798 do { \ 4799 REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \ 4800 REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \ 4801 } while (0) 4802 4803 /* n = 1,4,8,14 */ 4804 #define __ssi_set_rx_trigger(n) \ 4805 do { \ 4806 REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \ 4807 REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \ 4808 } while (0) 4809 4810 #define __ssi_get_txfifo_count() \ 4811 ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT ) 4812 4813 #define __ssi_get_rxfifo_count() \ 4814 ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT ) 4815 4816 #define __ssi_clear_errors() \ 4817 ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) ) 4818 4819 #define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END ) 4820 #define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY ) 4821 4822 #define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF ) 4823 #define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE ) 4824 #define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF ) 4825 4826 #define __ssi_set_clk(dev_clk, ssi_clk) \ 4827 ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 ) 4828 4829 #define __ssi_receive_data() REG_SSI_DR 4830 #define __ssi_transmit_data(v) ( REG_SSI_DR = (v) ) 4831 4832 /*************************************************************************** 4833 * WDT 4834 ***************************************************************************/ 4835 4836 #define __wdt_set_count(count) ( REG_WDT_WTCNT = (count) ) 4837 #define __wdt_start() ( REG_WDT_WTCSR |= WDT_WTCSR_START ) 4838 #define __wdt_stop() ( REG_WDT_WTCSR &= ~WDT_WTCSR_START ) 4839 4840 4841 /*************************************************************************** 4842 ***************************************************************************/ 4843 4844 /* 4845 * CPU clocks 4846 */ 4847 #define JZ_EXTAL CONFIG_SYS_EXTAL 4848 #define JZ_EXTAL2 32768 /* RTC clock */ 4849 4850 static __inline__ unsigned int __cpm_get_pllout(void) 4851 { 4852 unsigned int nf, nr, no, pllout; 4853 unsigned long plcr = REG_CPM_PLCR1; 4854 unsigned long od[4] = {1, 2, 2, 4}; 4855 if (plcr & CPM_PLCR1_PLL1EN) { 4856 nf = (plcr & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT; 4857 nr = (plcr & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT; 4858 no = od[((plcr & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT)]; 4859 pllout = (JZ_EXTAL) / ((nr+2) * no) * (nf+2); 4860 } else 4861 pllout = JZ_EXTAL; 4862 return pllout; 4863 } 4864 4865 static __inline__ unsigned int __cpm_get_iclk(void) 4866 { 4867 unsigned int iclk; 4868 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 4869 unsigned long cfcr = REG_CPM_CFCR; 4870 unsigned long plcr = REG_CPM_PLCR1; 4871 if (plcr & CPM_PLCR1_PLL1EN) 4872 iclk = __cpm_get_pllout() / 4873 div[(cfcr & CPM_CFCR_IFR_MASK) >> CPM_CFCR_IFR_BIT]; 4874 else 4875 iclk = JZ_EXTAL; 4876 return iclk; 4877 } 4878 4879 static __inline__ unsigned int __cpm_get_sclk(void) 4880 { 4881 unsigned int sclk; 4882 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 4883 unsigned long cfcr = REG_CPM_CFCR; 4884 unsigned long plcr = REG_CPM_PLCR1; 4885 if (plcr & CPM_PLCR1_PLL1EN) 4886 sclk = __cpm_get_pllout() / 4887 div[(cfcr & CPM_CFCR_SFR_MASK) >> CPM_CFCR_SFR_BIT]; 4888 else 4889 sclk = JZ_EXTAL; 4890 return sclk; 4891 } 4892 4893 static __inline__ unsigned int __cpm_get_mclk(void) 4894 { 4895 unsigned int mclk; 4896 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 4897 unsigned long cfcr = REG_CPM_CFCR; 4898 unsigned long plcr = REG_CPM_PLCR1; 4899 if (plcr & CPM_PLCR1_PLL1EN) 4900 mclk = __cpm_get_pllout() / 4901 div[(cfcr & CPM_CFCR_MFR_MASK) >> CPM_CFCR_MFR_BIT]; 4902 else 4903 mclk = JZ_EXTAL; 4904 return mclk; 4905 } 4906 4907 static __inline__ unsigned int __cpm_get_pclk(void) 4908 { 4909 unsigned int devclk; 4910 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 4911 unsigned long cfcr = REG_CPM_CFCR; 4912 unsigned long plcr = REG_CPM_PLCR1; 4913 if (plcr & CPM_PLCR1_PLL1EN) 4914 devclk = __cpm_get_pllout() / 4915 div[(cfcr & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT]; 4916 else 4917 devclk = JZ_EXTAL; 4918 return devclk; 4919 } 4920 4921 static __inline__ unsigned int __cpm_get_devclk(void) 4922 { 4923 unsigned int devclk; 4924 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 4925 unsigned long cfcr = REG_CPM_CFCR; 4926 unsigned long plcr = REG_CPM_PLCR1; 4927 if (plcr & CPM_PLCR1_PLL1EN) 4928 devclk = __cpm_get_pllout() / 4929 div[(cfcr & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT]; 4930 else 4931 devclk = JZ_EXTAL; 4932 return devclk; 4933 } 4934 4935 #endif /* !__ASSEMBLY__ */ 4936 4937 #endif /* __JZ4730_H__ */