1 /* 2 * Generic board initialisation, based on uboot-xburst and xburst-tools. 3 * 4 * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 5 * Copyright (C) 2005-2006 Ingenic Semiconductor, <jlwei@ingenic.cn> 6 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> 7 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 8 * 9 * This program is free software; you can redistribute it and/or modify it under 10 * the terms of the GNU General Public License as published by the Free Software 11 * Foundation; either version 3 of the License, or (at your option) any later 12 * version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 16 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #ifdef CONFIG_CPU_JZ4730 24 #include "jz4730.h" 25 #include "jz4730_compat.h" 26 #else 27 #include "jz4740.h" 28 #endif 29 30 #include "sdram.h" 31 #include "usb_boot_defines.h" 32 33 /* These arguments are initialised by usbboot and are defined in... 34 /etc/xburst-tools/usbboot.cfg. */ 35 36 struct fw_args *fw_args; 37 volatile u32 FW_CPU_ID; 38 volatile u8 FW_SDRAM_BW16; 39 volatile u8 FW_SDRAM_BANK4; 40 volatile u8 FW_SDRAM_ROW; 41 volatile u8 FW_SDRAM_COL; 42 volatile u8 FW_CONFIG_MOBILE_SDRAM; 43 volatile u8 FW_IS_SHARE; 44 45 void load_args(void) 46 { 47 /* Get the fw args from memory. See head1.S for the memory layout. */ 48 49 fw_args = (struct fw_args *)0x80002008; 50 FW_CPU_ID = fw_args->cpu_id ; 51 FW_SDRAM_BW16 = fw_args->bus_width; 52 FW_SDRAM_BANK4 = fw_args->bank_num; 53 FW_SDRAM_ROW = fw_args->row_addr; 54 FW_SDRAM_COL = fw_args->col_addr; 55 FW_CONFIG_MOBILE_SDRAM = fw_args->is_mobile; 56 FW_IS_SHARE = fw_args->is_busshare; 57 } 58 59 /* Initialisation functions. */ 60 61 void gpio_init(void) 62 { 63 #ifndef CONFIG_CPU_JZ4730 64 /* 65 * Initialize NAND Flash Pins 66 */ 67 __gpio_as_nand(); 68 69 /* 70 * Initialize SDRAM pins 71 */ 72 __gpio_as_sdram_16bit_4720(); 73 #endif 74 } 75 76 void pll_init(void) 77 { 78 register unsigned int cfcr, plcr1; 79 int nf, pllout2; 80 81 /* See CPCCR (Clock Control Register). 82 * 0 == same frequency; 2 == f/3 83 */ 84 85 cfcr = CPM_CPCCR_CLKOEN | 86 CPM_CPCCR_PCS | 87 (0 << CPM_CPCCR_CDIV_BIT) | 88 (2 << CPM_CPCCR_HDIV_BIT) | 89 (2 << CPM_CPCCR_PDIV_BIT) | 90 (2 << CPM_CPCCR_MDIV_BIT) | 91 (2 << CPM_CPCCR_LDIV_BIT); 92 93 /* Init USB Host clock. 94 * Desired frequency == 48MHz 95 */ 96 97 #ifdef CONFIG_CPU_JZ4730 98 cfcr |= ((CFG_CPU_SPEED / 48000000 - 1) << 25); 99 #else 100 /* Determine the divider clock output based on the PCS bit. */ 101 pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); 102 103 /* Divisor == UHCCDR + 1 */ 104 REG_CPM_UHCCDR = pllout2 / 48000000 - 1; 105 #endif 106 107 nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; 108 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ 109 (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ 110 (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ 111 CPM_CPPCR_PLLEN; /* enable PLL */ 112 113 /* Update PLL and wait. */ 114 115 REG_CPM_CPCCR = cfcr; 116 REG_CPM_CPPCR = plcr1; 117 while (!__cpm_pll_is_on()); 118 } 119 120 void sdram_init(void) 121 { 122 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; 123 unsigned int pllout = __cpm_get_pllout(); 124 125 unsigned int cas_latency_sdmr[2] = { 126 EMC_SDMR_CAS_2, 127 EMC_SDMR_CAS_3, 128 }; 129 130 unsigned int cas_latency_dmcr[2] = { 131 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ 132 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ 133 }; 134 135 /* Divisors for CPCCR values. */ 136 137 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 138 139 cpu_clk = pllout / div[__cpm_get_cdiv()]; 140 mem_clk = pllout / div[__cpm_get_mdiv()]; 141 142 REG_EMC_BCR = 0; /* Disable bus release */ 143 REG_EMC_RTCSR = 0; /* Disable clock for counting */ 144 145 /* Fault DMCR value for mode register setting*/ 146 dmcr0 = (0<<EMC_DMCR_RA_BIT) | 147 (0<<EMC_DMCR_CA_BIT) | 148 (0<<EMC_DMCR_BA_BIT) | 149 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | 150 EMC_DMCR_EPIN | 151 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 152 153 /* Basic DMCR value */ 154 dmcr = ((FW_SDRAM_ROW-SDRAM_ROW0)<<EMC_DMCR_RA_BIT) | 155 ((FW_SDRAM_COL-SDRAM_COL0)<<EMC_DMCR_CA_BIT) | 156 ((FW_SDRAM_BANK4-SDRAM_BANK40)<<EMC_DMCR_BA_BIT) | 157 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | 158 EMC_DMCR_EPIN | 159 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 160 161 /* SDRAM timimg */ 162 ns = 1000000000 / mem_clk; 163 tmp = SDRAM_TRAS/ns; 164 if (tmp < 4) tmp = 4; 165 if (tmp > 11) tmp = 11; 166 dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); 167 tmp = SDRAM_RCD/ns; 168 if (tmp > 3) tmp = 3; 169 dmcr |= (tmp << EMC_DMCR_RCD_BIT); 170 tmp = SDRAM_TPC/ns; 171 if (tmp > 7) tmp = 7; 172 dmcr |= (tmp << EMC_DMCR_TPC_BIT); 173 tmp = SDRAM_TRWL/ns; 174 if (tmp > 3) tmp = 3; 175 dmcr |= (tmp << EMC_DMCR_TRWL_BIT); 176 tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; 177 if (tmp > 14) tmp = 14; 178 dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); 179 180 /* SDRAM mode value */ 181 sdmode = EMC_SDMR_BT_SEQ | 182 EMC_SDMR_OM_NORMAL | 183 EMC_SDMR_BL_4 | 184 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; 185 186 /* jz4730 additional measures */ 187 #ifdef CONFIG_CPU_JZ4730 188 if (FW_SDRAM_BW16) 189 sdmode <<= 1; 190 else 191 sdmode <<= 2; 192 #endif 193 194 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ 195 REG_EMC_DMCR = dmcr; 196 REG8(EMC_SDMR0|sdmode) = 0; 197 198 /* jz4730 additional measures */ 199 #ifdef CONFIG_CPU_JZ4730 200 REG8(EMC_SDMR1|sdmode) = 0; 201 #endif 202 203 /* Wait for precharge, > 200us */ 204 tmp = (cpu_clk / 1000000) * 1000; 205 while (tmp--); 206 207 /* Stage 2. Enable auto-refresh */ 208 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; 209 210 tmp = SDRAM_TREF/ns; 211 tmp = tmp/64 + 1; 212 if (tmp > 0xff) tmp = 0xff; 213 REG_EMC_RTCOR = tmp; 214 REG_EMC_RTCNT = 0; 215 REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ 216 217 /* Wait for number of auto-refresh cycles */ 218 tmp = (cpu_clk / 1000000) * 1000; 219 while (tmp--); 220 221 /* Stage 3. Mode Register Set */ 222 REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 223 REG8(EMC_SDMR0|sdmode) = 0; 224 225 /* jz4730 additional measures */ 226 #ifdef CONFIG_CPU_JZ4730 227 REG8(EMC_SDMR1|sdmode) = 0; 228 #endif 229 230 /* Set back to basic DMCR value */ 231 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 232 233 /* everything is ok now */ 234 }