1 /* 2 * Common SDRAM configuration 3 * 4 * Copyright (C) 2009 Qi Hardware Inc. 5 * Authors: Xiangfu Liu <xiangfu@openmobilefree.net> 6 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 3 of the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 21 * Boston, MA 02110-1301, USA 22 */ 23 24 #ifndef __SDRAM_H__ 25 #define __SDRAM_H__ 26 27 /* virt_to_phys() from u-boot/arch/mips/include/asm/addrspace.h 28 via u-boot/arch/mips/include/asm/io.h */ 29 /* #define virt_to_phys(n) (((int) n) & 0x1fffffff) */ 30 #define virt_to_phys(n) ((int) n) 31 32 /* 33 * RAM configuration 34 */ 35 #define CONFIG_SYS_SDRAM_BASE 0x80000000 36 37 /* 38 * SDRAM configuration (timings in ns) 39 */ 40 #define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ 41 #define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ 42 #define SDRAM_ROW 13 /* Row address: 11 to 13 */ 43 #define SDRAM_COL 9 /* Column address: 8 to 12 */ 44 #define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ 45 #define SDRAM_TRAS 45 /* RAS# Active Time */ 46 #define SDRAM_RCD 20 /* RAS# to CAS# Delay */ 47 #define SDRAM_TPC 20 /* RAS# Precharge Time */ 48 #define SDRAM_TRWL 7 /* Write Latency Time */ 49 #define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ 50 51 #define SDRAM_ROW0 11 /* Row address minimum */ 52 #define SDRAM_COL0 8 /* Column address minimum */ 53 #define SDRAM_BANK40 0 /* Bank minimum */ 54 55 /* 56 * Cache configuration 57 */ 58 #define CONFIG_SYS_DCACHE_SIZE 16384 59 #define CONFIG_SYS_ICACHE_SIZE 16384 60 #define CONFIG_SYS_CACHELINE_SIZE 32 61 62 /* 63 * Memory configuration 64 */ 65 #define KSEG0 0x80000000 66 #define PAGE_SIZE 4096 67 68 #endif /* __SDRAM_H__ */