NanoPayload

stage2/cpu_op.S

216:95be7694d999
2017-06-28 Paul Boddie Employ structure member names to make initialisation clearer.
     1 /*     2  * CPU-specific routines originally from U-Boot.     3  * See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c     4  * See: u-boot/arch/mips/include/asm/cacheops.h     5  *     6  * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>     7  * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk>     8  *     9  * This program is free software; you can redistribute it and/or    10  * modify it under the terms of the GNU General Public License as    11  * published by the Free Software Foundation; either version 2 of    12  * the License, or (at your option) any later version.    13  *    14  * This program is distributed in the hope that it will be useful,    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the    17  * GNU General Public License for more details.    18  *    19  * You should have received a copy of the GNU General Public License    20  * along with this program; if not, write to the Free Software    21  * Foundation, Inc., 51 Franklin Street, Fifth Floor,    22  * Boston, MA  02110-1301, USA    23  */    24     25 #include "mips.h"    26 #include "paging.h"    27 #include "sdram.h"    28     29 .text    30 .globl flush_icache_tag    31 .globl flush_icache_region    32 .globl flush_icache_config    33 .globl flush_dcache_region    34 .globl handle_error_level    35 .globl enable_interrupts    36 .globl init_interrupts    37 .globl invoke_task    38 .globl enter_task    39 .globl configure_tlb    40 .globl map_page_set_index    41 .globl map_page_index_op    42 .globl map_page_op    43 .set noreorder    44     45     46     47 flush_icache_tag:    48 	mtc0 $zero, CP0_TAGLO    49 	mtc0 $zero, CP0_TAGHI    50 	jr $ra    51 	nop    52     53     54     55 flush_icache_region:    56 	cache Index_Store_Tag_I, 0($a0)    57 	jr $ra    58 	nop    59     60     61     62 flush_icache_config:    63 	move $t3, $zero    64 	mfc0 $t3, CP0_CONFIG, 7    65 	nop    66 	ori $t3, 2    67 	mtc0 $t3, CP0_CONFIG, 7    68 	jr $ra    69 	nop    70     71     72     73 flush_dcache_region:    74 	cache Index_Writeback_Inv_D, 0($a0)    75 	jr $ra    76 	nop    77     78     79     80 handle_error_level:    81 	mfc0 $t3, CP0_STATUS    82 	li $t4, ~STATUS_ERL    83 	and $t3, $t3, $t4    84 	mtc0 $t3, CP0_STATUS    85 	jr $ra    86 	nop    87     88     89     90 enable_interrupts:    91 	mfc0 $t3, CP0_STATUS    92 	ori $t3, $t3, STATUS_IRQ | STATUS_IE    93 	mtc0 $t3, CP0_STATUS    94 	jr $ra    95 	nop    96     97     98     99 init_interrupts:   100    101 	/* Set exception registers. */   102    103 	mtc0 $zero, CP0_WATCHLO   104 	li $t3, CAUSE_IV	/* IV = 1 (use 0x80000200 for interrupts) */   105 	mtc0 $t3, CP0_CAUSE   106 	mfc0 $t4, CP0_STATUS   107 	li $t3, ~STATUS_BEV   108 	and $t3, $t3, $t4   109 	mtc0 $t3, CP0_STATUS   110 	jr $ra   111 	nop   112    113    114    115 /* (u8 asid, u32 *base, u32 *stack_pointer) */   116    117 invoke_task:   118 	mtc0 $a0, CP0_ENTRYHI   119 	nop   120 	move $t4, $a2		/* use arguments before they are overwritten */   121 	lw $sp, 0($t4)		/* set the stack pointer */   122 	move $t3, $a1		/* load parameters from the stored registers */   123 	lw $a0, 16($t3)   124 	lw $a1, 20($t3)   125 	lw $a2, 24($t3)   126 	lw $a3, 28($t3)   127 	lw $t9, 100($t3)   128 	lw $gp, 104($t3)   129 	mtc0 $t9, CP0_EPC   130    131 enter_task:   132 	mfc0 $t3, CP0_STATUS   133 	ori $t3, $t3, STATUS_EXL | STATUS_UM   134 	/* li $t4, STATUS_CP0	** flag resides in the upper 16 bits, needed... */   135 	/* or $t3, $t3, $t4	** for debugging by accessing CP0 in user mode */   136 	mtc0 $t3, CP0_STATUS   137 	eret   138 	nop   139    140    141    142 configure_tlb:   143 	mtc0 $zero, CP0_CONTEXT   144 	mtc0 $a0, CP0_WIRED	/* first random entry is defined by the parameter */   145 	mfc0 $v0, CP0_CONFIG	/* return the limit */   146 	jr $ra   147 	nop   148    149    150    151 /* (u32 index) */   152    153 map_page_set_index:   154 	mtc0 $a0, CP0_INDEX   155 	jr $ra   156 	nop   157    158    159    160 /* (u32 lower, u32 upper, u32 start, u32 pagemask) */   161    162 map_page_index_op:   163 	jal map_page_op_setup   164 	nop   165    166 	tlbwi   167 	jr $ra   168 	nop   169    170    171    172 /* (u32 lower, u32 upper, u32 start, u32 pagemask) */   173    174 map_page_op:   175 	jal map_page_op_setup   176 	nop   177    178 	tlbwr   179 	jr $ra   180 	nop   181    182    183    184 /* (u32 lower, u32 upper, u32 start, u32 pagemask) */   185    186 map_page_op_setup:   187 	mtc0 $a3, CP0_PAGEMASK   188    189 	/* Set physical address. */   190    191 	mtc0 $a0, CP0_ENTRYLO0   192 	mtc0 $a1, CP0_ENTRYLO1   193    194 	/* Set virtual address. */   195    196 	mtc0 $a2, CP0_ENTRYHI   197 	jr $ra   198 	nop   199    200    201    202 .set reorder