1 /* 2 * U-Boot and JzRISC LCD controller definitions 3 * 4 * Copyright (C) 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * Copyright (C) 2005-2007, Ingenic Semiconductor Inc. 6 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> 7 * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 22 * Boston, MA 02110-1301, USA 23 */ 24 25 #ifndef __JZLCD_H__ 26 #define __JZLCD_H__ 27 28 #include "xburst_types.h" 29 30 void lcd_set_bpp(u8 bpp); 31 unsigned long lcd_ctrl_init(); 32 void lcd_enable(); 33 void lcd_disable(); 34 35 /* 36 * Framebuffer characteristics 37 */ 38 struct jzfb_info { 39 unsigned int cfg; /* panel mode and pin usage etc. */ 40 unsigned int w; 41 unsigned int h; 42 unsigned int bpp; /* bit per pixel */ 43 unsigned int fclk; /* frame clk */ 44 unsigned int hsw; /* hsync width, in pclk */ 45 unsigned int vsw; /* vsync width, in line count */ 46 unsigned int elw; /* end of line, in pclk */ 47 unsigned int blw; /* begin of line, in pclk */ 48 unsigned int efw; /* end of frame, in line count */ 49 unsigned int bfw; /* begin of frame, in line count */ 50 }; 51 52 /* 53 * LCD controller stucture for JZSOC: JZ4740 54 */ 55 struct jz_fb_dma_descriptor { 56 struct jz_fb_dma_descriptor *fdadr; /* Frame descriptor address register */ 57 unsigned long fsadr; /* Frame source address register */ 58 unsigned long fidr; /* Frame ID register */ 59 unsigned long ldcmd; /* Command register */ 60 }; 61 62 /* 63 * Jz LCD info 64 */ 65 struct jz_fb_info { 66 67 struct jz_fb_dma_descriptor *fdadr0; /* physical address of frame/palette descriptor */ 68 struct jz_fb_dma_descriptor *fdadr1; /* physical address of frame descriptor */ 69 70 /* DMA descriptors */ 71 struct jz_fb_dma_descriptor *dmadesc_fblow; 72 struct jz_fb_dma_descriptor *dmadesc_fbhigh; 73 struct jz_fb_dma_descriptor *dmadesc_palette; 74 75 unsigned long screen; /* address of frame buffer */ 76 unsigned long palette; /* address of palette memory */ 77 }; 78 79 /* 80 * Concise display characteristics with low-level structure reference 81 */ 82 typedef struct vidinfo { 83 unsigned short vl_col; /* Number of columns (i.e. 640) */ 84 unsigned short vl_row; /* Number of rows (i.e. 480) */ 85 unsigned char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */ 86 87 struct jz_fb_info jz_fb; 88 } vidinfo_t; 89 90 /* Alignment/rounding macros. */ 91 92 #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) 93 #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) 94 95 /* General values for colour depths and framebuffer characteristics. */ 96 97 #define LCD_MONOCHROME 0 98 #define LCD_COLOR2 1 99 #define LCD_COLOR4 2 100 #define LCD_COLOR8 3 101 #define LCD_COLOR16 4 102 #define LCD_COLOR32 5 103 104 /* Calculate number of bits per pixel and number of colours. */ 105 106 #define NBITS(bit_code) (1 << (bit_code)) 107 #define NCOLORS(bit_code) (1 << NBITS(bit_code)) 108 109 /* Transfer and display types. */ 110 111 #define MODE_MASK 0x0f 112 #define MODE_TFT_GEN 0x00 113 #define MODE_TFT_SHARP 0x01 114 #define MODE_TFT_CASIO 0x02 115 #define MODE_TFT_SAMSUNG 0x03 116 #define MODE_CCIR656_NONINT 0x04 117 #define MODE_CCIR656_INT 0x05 118 #define MODE_STN_COLOR_SINGLE 0x08 119 #define MODE_STN_MONO_SINGLE 0x09 120 #define MODE_STN_COLOR_DUAL 0x0a 121 #define MODE_STN_MONO_DUAL 0x0b 122 #define MODE_8BIT_SERIAL_TFT 0x0c 123 124 #define MODE_TFT_18BIT (1<<7) 125 126 #define STN_DAT_PIN1 (0x00 << 4) 127 #define STN_DAT_PIN2 (0x01 << 4) 128 #define STN_DAT_PIN4 (0x02 << 4) 129 #define STN_DAT_PIN8 (0x03 << 4) 130 #define STN_DAT_PINMASK STN_DAT_PIN8 131 132 #define STFT_PSHI (1 << 15) 133 #define STFT_CLSHI (1 << 14) 134 #define STFT_SPLHI (1 << 13) 135 #define STFT_REVHI (1 << 12) 136 137 #define SYNC_MASTER (0 << 16) 138 #define SYNC_SLAVE (1 << 16) 139 140 #define DE_P (0 << 9) 141 #define DE_N (1 << 9) 142 143 #define PCLK_P (0 << 10) 144 #define PCLK_N (1 << 10) 145 146 #define HSYNC_P (0 << 11) 147 #define HSYNC_N (1 << 11) 148 149 #define VSYNC_P (0 << 8) 150 #define VSYNC_N (1 << 8) 151 152 #define DATA_NORMAL (0 << 17) 153 #define DATA_INVERSE (1 << 17) 154 155 #endif /* __JZLCD_H__ */