NanoPayload

stage2/handlers.S

114:b9ac03c2c599
2016-02-22 Paul Boddie Introduced elementary TLB handling; separated out register saving and loading. stage2-non-pic
     1 /*     2  * Handler routines.     3  *     4  * Copyright (C) 2015 Nicholas FitzRoy-Dale <wzdd.code@lardcave.net>     5  * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk>     6  *     7  * This program is free software: you can redistribute it and/or modify     8  * it under the terms of the GNU General Public License as published by     9  * the Free Software Foundation, either version 3 of the License, or    10  * (at your option) any later version.    11  *    12  * This program is distributed in the hope that it will be useful,    13  * but WITHOUT ANY WARRANTY; without even the implied warranty of    14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the    15  * GNU General Public License for more details.    16  *    17  * You should have received a copy of the GNU General Public License    18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.    19  */    20     21 .text    22 .extern tlb_handle    23 .extern irq_handle    24 .globl tlb_handler    25 .globl interrupt_handler    26 .set noreorder    27 .set noat    28     29 tlb_handler:    30 	sw $ra, -112($sp)    31 	jal save_state    32 	nop    33     34 	/* Invoke the handler. */    35     36 	jal tlb_handle    37 	nop    38     39 	j load_and_return    40 	nop    41     42 interrupt_handler:    43 	sw $ra, -112($sp)    44 	jal save_state    45 	nop    46     47 	/* Invoke the handler. */    48     49 	jal irq_handle    50 	nop    51     52 	j load_and_return    53 	nop    54     55 save_state:    56     57 	/* Save the status, mask interrupts. */    58     59 	mfc0 $k0, $12 /* CP0_STATUS */    60 	li $k1, 0xffff03ff    61 	and $k1, $k0, $k1    62 	mtc0 $k1, $12    63 	sw $k0, -120($sp)    64     65 	sw $at, -4($sp)    66 	sw $v0, -8($sp)    67 	sw $v1, -12($sp)    68 	sw $a0, -16($sp)    69 	sw $a1, -20($sp)    70 	sw $a2, -24($sp)    71 	sw $a3, -28($sp)    72 	sw $t0, -32($sp)    73 	sw $t1, -36($sp)    74 	sw $t2, -40($sp)    75 	sw $t3, -44($sp)    76 	sw $t4, -48($sp)    77 	sw $t5, -52($sp)    78 	sw $t6, -56($sp)    79 	sw $t7, -60($sp)    80 	sw $s0, -64($sp)    81 	sw $s1, -68($sp)    82 	sw $s2, -72($sp)    83 	sw $s3, -76($sp)    84 	sw $s4, -80($sp)    85 	sw $s5, -84($sp)    86 	sw $s6, -88($sp)    87 	sw $s7, -92($sp)    88 	sw $t8, -96($sp)    89 	sw $t9, -100($sp)    90 	sw $gp, -104($sp)    91 	sw $fp, -108($sp)    92 	/* sw $ra, -112($sp) */    93     94 	mfc0 $k0, $14 /* CP0_EPC */    95 	nop    96 	sw $k0, -116($sp)    97     98 	addi $sp, $sp, -120    99 	j $ra   100 	nop   101    102 load_and_return:   103    104 	addi $sp, $sp, 120   105    106 	lw $at, -4($sp)   107 	lw $v0, -8($sp)   108 	lw $v1, -12($sp)   109 	lw $a0, -16($sp)   110 	lw $a1, -20($sp)   111 	lw $a2, -24($sp)   112 	lw $a3, -28($sp)   113 	lw $t0, -32($sp)   114 	lw $t1, -36($sp)   115 	lw $t2, -40($sp)   116 	lw $t3, -44($sp)   117 	lw $t4, -48($sp)   118 	lw $t5, -52($sp)   119 	lw $t6, -56($sp)   120 	lw $t7, -60($sp)   121 	lw $s0, -64($sp)   122 	lw $s1, -68($sp)   123 	lw $s2, -72($sp)   124 	lw $s3, -76($sp)   125 	lw $s4, -80($sp)   126 	lw $s5, -84($sp)   127 	lw $s6, -88($sp)   128 	lw $s7, -92($sp)   129 	lw $t8, -96($sp)   130 	lw $t9, -100($sp)   131 	lw $gp, -104($sp)   132 	lw $fp, -108($sp)   133 	lw $ra, -112($sp)   134    135 	lw $k0, -116($sp)   136 	mtc0 $k0, $14 /* CP0_EPC */   137 	nop   138    139 	lw $k0, -120($sp)   140 	mtc0 $k0, $12 /* CP0_STATUS */   141 	nop   142    143 	eret   144 	nop   145    146 .set reorder   147 .set at