1 /* 2 * Initialisation code for the stage 2 payload. 3 * 4 * Copyright 2009 (C) Qi Hardware Inc. 5 * Author: Wolfgang Spraul <wolfgang@sharism.cc> 6 * 7 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation, either version 3 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 .text 24 .extern c_main 25 .extern _tlb_entry 26 .extern _exc_entry 27 .extern _irq_entry 28 .extern _end_entries 29 .globl _start 30 .set noreorder 31 32 _start: 33 /* Initialise the stack. */ 34 35 la $sp, 0x80080000 36 37 /* Copy TLB handling instructions. */ 38 39 lui $t0, %hi(_tlb_entry) /* start */ 40 ori $t0, $t0, %lo(_tlb_entry) 41 li $t1, 0x80000000 42 lui $t2, %hi(_exc_entry) /* end */ 43 ori $t2, $t2, %lo(_exc_entry) 44 _tlb_copy: 45 lw $t3, 0($t0) 46 addiu $t0, $t0, 4 47 sw $t3, 0($t1) 48 bne $t0, $t2, _tlb_copy 49 addiu $t1, $t1, 4 /* executed in delay slot before branch */ 50 51 /* Copy exception handling instructions. */ 52 53 move $t0, $t2 /* start */ 54 li $t1, 0x80000180 55 lui $t2, %hi(_irq_entry) /* end */ 56 ori $t2, $t2, %lo(_irq_entry) 57 _exc_copy: 58 lw $t3, 0($t0) 59 addiu $t0, $t0, 4 60 sw $t3, 0($t1) 61 bne $t0, $t2, _exc_copy 62 addiu $t1, $t1, 4 /* executed in delay slot before branch */ 63 64 /* Copy IRQ handling instructions. */ 65 66 move $t0, $t2 /* start */ 67 li $t1, 0x80000200 68 lui $t2, %hi(_end_entries) /* end */ 69 ori $t2, $t2, %lo(_end_entries) 70 _irq_copy: 71 lw $t3, 0($t0) 72 addiu $t0, $t0, 4 73 sw $t3, 0($t1) 74 bne $t0, $t2, _irq_copy 75 addiu $t1, $t1, 4 /* executed in delay slot before branch */ 76 77 /* Initialise interrupts. */ 78 79 mfc0 $t3, $12 /* CP0_STATUS */ 80 nop 81 li $t4, 0xffbf00e0 /* BEV = 0 (not bootloader vectors); IM = disable all */ 82 and $t3, $t3, $t4 /* ... KSU = 0 (kernel mode); ERL = 0; EXL = 0; IE = 0 */ 83 li $t4, 0x0000ff04 /* IM = enable IM7..IM0; ERL = 1 (set by default) */ 84 or $t3, $t3, $t4 85 mtc0 $t3, $12 86 nop 87 88 li $t3, 0x00800000 /* IV = 1 (use 0x80000200 for interrupts) */ 89 mtc0 $t3, $13 /* CP0_CAUSE */ 90 nop 91 92 mtc0 $zero, $15 /* CP0_EBASE (should be zero anyway) */ 93 nop 94 95 /* Start the program. */ 96 97 j c_main 98 nop 99 100 .set reorder