1 /* 2 * U-Boot and JzRISC LCD controller definitions 3 * 4 * Copyright (C) 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * Copyright (C) 2005-2007, Ingenic Semiconductor Inc. 6 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> 7 * Copyright (C) 2015, 2016, 2017 Paul Boddie <paul@boddie.org.uk> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 22 * Boston, MA 02110-1301, USA 23 */ 24 25 #ifndef __JZLCD_H__ 26 #define __JZLCD_H__ 27 28 #include <stdint.h> 29 30 void lcd_set_bpp(uint8_t bpp); 31 uint32_t lcd_ctrl_init(); 32 void lcd_enable(); 33 void lcd_disable(); 34 35 /* Framebuffer characteristics. */ 36 37 struct jzfb_info { 38 uint32_t cfg; /* panel mode and pin usage etc. */ 39 uint16_t w; /* display width in pixels */ 40 uint16_t h; /* display height in pixels */ 41 uint8_t bpp; /* bits per pixel */ 42 uint32_t fclk; /* frame clock */ 43 uint32_t hsw; /* hsync width, in pixel clock */ 44 uint32_t vsw; /* vsync width, in line count */ 45 uint32_t elw; /* end of line, in pixel clock */ 46 uint32_t blw; /* begin of line, in pixel clock */ 47 uint32_t efw; /* end of frame, in line count */ 48 uint32_t bfw; /* begin of frame, in line count */ 49 }; 50 51 /* LCD controller stucture for jz4740. */ 52 53 struct jz_fb_dma_descriptor { 54 struct jz_fb_dma_descriptor *fdadr; /* frame descriptor address register */ 55 uint32_t fsadr; /* frame source address register */ 56 uint32_t fidr; /* frame identifier register */ 57 uint32_t ldcmd; /* command register */ 58 }; 59 60 /* Framebuffer and controller memory information. */ 61 62 struct jz_mem_info { 63 64 /* DMA descriptor references (updated for transfers). */ 65 66 struct jz_fb_dma_descriptor *fdadr0; /* physical address of frame descriptor */ 67 struct jz_fb_dma_descriptor *fdadr1; /* physical address of frame/palette descriptor */ 68 69 /* DMA descriptor references (indicating allocated regions). */ 70 71 struct jz_fb_dma_descriptor *dmadesc_fb0; 72 struct jz_fb_dma_descriptor *dmadesc_fb1; 73 struct jz_fb_dma_descriptor *dmadesc_palette; 74 75 uint32_t screen; /* address of first frame buffer (base of memory used) */ 76 uint32_t palette; /* address of palette memory */ 77 uint32_t total; /* total memory used */ 78 }; 79 80 /* Display characteristics and memory resources. */ 81 82 typedef struct vidinfo { 83 struct jzfb_info *jz_fb; /* framebuffer and panel properties */ 84 struct jz_mem_info jz_mem; /* framebuffer memory information */ 85 void *lcd; /* address of LCD controller registers */ 86 } vidinfo_t; 87 88 /* Alignment/rounding macros. */ 89 90 #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) 91 #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) 92 93 /* Transfer and display types. */ 94 95 #define MODE_MASK 0x0f 96 #define MODE_TFT_GEN 0x00 97 #define MODE_TFT_SHARP 0x01 98 #define MODE_TFT_CASIO 0x02 99 #define MODE_TFT_SAMSUNG 0x03 100 #define MODE_CCIR656_NONINT 0x04 101 #define MODE_CCIR656_INT 0x05 102 #define MODE_STN_COLOR_SINGLE 0x08 103 #define MODE_STN_MONO_SINGLE 0x09 104 #define MODE_STN_COLOR_DUAL 0x0a 105 #define MODE_STN_MONO_DUAL 0x0b 106 #define MODE_8BIT_SERIAL_TFT 0x0c 107 108 #define MODE_TFT_18BIT (1<<7) 109 110 #define STN_DAT_PIN1 (0x00 << 4) 111 #define STN_DAT_PIN2 (0x01 << 4) 112 #define STN_DAT_PIN4 (0x02 << 4) 113 #define STN_DAT_PIN8 (0x03 << 4) 114 #define STN_DAT_PINMASK STN_DAT_PIN8 115 116 #define STFT_PSHI (1 << 15) 117 #define STFT_CLSHI (1 << 14) 118 #define STFT_SPLHI (1 << 13) 119 #define STFT_REVHI (1 << 12) 120 121 #define SYNC_MASTER (0 << 16) 122 #define SYNC_SLAVE (1 << 16) 123 124 #define DE_P (0 << 9) 125 #define DE_N (1 << 9) 126 127 #define PCLK_P (0 << 10) 128 #define PCLK_N (1 << 10) 129 130 #define HSYNC_P (0 << 11) 131 #define HSYNC_N (1 << 11) 132 133 #define VSYNC_P (0 << 8) 134 #define VSYNC_N (1 << 8) 135 136 #define DATA_NORMAL (0 << 17) 137 #define DATA_INVERSE (1 << 17) 138 139 /* Palette buffer (LCD_CMDx.PAL). */ 140 141 #define LCD_CMD_PAL (1 << 28) 142 143 #endif /* __JZLCD_H__ */