1 /* 2 * Common SDRAM configuration. 3 * 4 * Copyright (C) 2009 Qi Hardware Inc. 5 * Authors: Xiangfu Liu <xiangfu@openmobilefree.net> 6 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 7 * 8 * This program is free software: you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation, either version 3 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef __SDRAM_H__ 23 #define __SDRAM_H__ 24 25 /* virt_to_phys() from u-boot/arch/mips/include/asm/addrspace.h 26 via u-boot/arch/mips/include/asm/io.h */ 27 /* #define virt_to_phys(n) (((int) n) & 0x1fffffff) */ 28 #define virt_to_phys(n) ((int) n) 29 30 /* 31 * RAM configuration 32 */ 33 #define CONFIG_SYS_SDRAM_BASE 0x80000000 34 35 /* 36 * SDRAM configuration (timings in ns) 37 */ 38 #ifdef CONFIG_CPU_JZ4730_MINIPC 39 #define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */ 40 #else 41 #define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ 42 #endif 43 44 #define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ 45 #define SDRAM_ROW 13 /* Row address: 11 to 13 */ 46 #define SDRAM_COL 9 /* Column address: 8 to 12 */ 47 #define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ 48 #define SDRAM_TRAS 45 /* RAS# Active Time */ 49 #define SDRAM_RCD 20 /* RAS# to CAS# Delay */ 50 #define SDRAM_TPC 20 /* RAS# Precharge Time */ 51 #define SDRAM_TRWL 7 /* Write Latency Time */ 52 53 #ifdef CONFIG_CPU_JZ4730_MINIPC 54 #define SDRAM_TREF 7812 /* Refresh period: 8192 cycles/64ms */ 55 #else 56 #define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ 57 #endif 58 59 #define SDRAM_ROW0 11 /* Row address minimum */ 60 #define SDRAM_COL0 8 /* Column address minimum */ 61 #define SDRAM_BANK40 0 /* Bank minimum */ 62 63 /* 64 * Cache configuration 65 */ 66 #define CONFIG_SYS_DCACHE_SIZE 16384 67 #define CONFIG_SYS_ICACHE_SIZE 16384 68 #define CONFIG_SYS_CACHELINE_SIZE 32 69 70 /* 71 * Memory configuration 72 */ 73 #define KSEG0 0x80000000 74 #define PAGE_SIZE 4096 75 76 #endif /* __SDRAM_H__ */