1 /* 2 * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools. 3 * 4 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 5 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> 6 * Copyright (c) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn> 7 * 8 * This program is free software; you can redistribute it and/or modify it under 9 * the terms of the GNU General Public License as published by the Free Software 10 * Foundation; either version 3 of the License, or (at your option) any later 11 * version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 15 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 16 * details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "jz4740.h" 23 #include "configs.h" 24 #include "nanonote.h" 25 26 void gpio_init(void) 27 { 28 /* 29 * Initialize NAND Flash Pins 30 */ 31 __gpio_as_nand(); 32 33 /* 34 * Initialize SDRAM pins 35 */ 36 __gpio_as_sdram_32bit(); 37 } 38 39 void gpio_init2(void) 40 { 41 /* 42 * Initialize LCD pins 43 */ 44 __gpio_as_slcd_8bit(); 45 46 /* 47 * Initialize MSC pins 48 */ 49 __gpio_as_msc(); 50 51 /* 52 * Initialize Other pins 53 */ 54 unsigned int i; 55 for (i = 0; i < 7; i++){ 56 __gpio_as_input(GPIO_KEYIN_BASE + i); 57 __gpio_enable_pull(GPIO_KEYIN_BASE + i); 58 } 59 60 for (i = 0; i < 8; i++) { 61 __gpio_as_output(GPIO_KEYOUT_BASE + i); 62 __gpio_clear_pin(GPIO_KEYOUT_BASE + i); 63 } 64 65 /* enable the TP4, TP5 as UART0 */ 66 __gpio_jtag_to_uart0(); 67 68 __gpio_as_input(GPIO_KEYIN_8); 69 __gpio_enable_pull(GPIO_KEYIN_8); 70 71 __gpio_as_output(GPIO_AUDIO_POP); 72 __gpio_set_pin(GPIO_AUDIO_POP); 73 74 __gpio_as_output(GPIO_LCD_CS); 75 __gpio_clear_pin(GPIO_LCD_CS); 76 77 __gpio_as_output(GPIO_AMP_EN); 78 __gpio_clear_pin(GPIO_AMP_EN); 79 80 __gpio_as_output(GPIO_SDPW_EN); 81 __gpio_disable_pull(GPIO_SDPW_EN); 82 __gpio_clear_pin(GPIO_SDPW_EN); 83 84 __gpio_as_input(GPIO_SD_DETECT); 85 __gpio_disable_pull(GPIO_SD_DETECT); 86 87 __gpio_as_input(GPIO_USB_DETECT); 88 __gpio_enable_pull(GPIO_USB_DETECT); 89 } 90 91 void cpm_init(void) 92 { 93 __cpm_stop_ipu(); 94 __cpm_stop_cim(); 95 __cpm_stop_i2c(); 96 __cpm_stop_ssi(); 97 __cpm_stop_uart1(); 98 __cpm_stop_sadc(); 99 __cpm_stop_uhc(); 100 __cpm_stop_udc(); 101 __cpm_stop_aic1(); 102 /* __cpm_stop_aic2();*/ 103 } 104 105 void pll_init(void) 106 { 107 register unsigned int cfcr, plcr1; 108 int n2FR[33] = { 109 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 110 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 111 9 112 }; 113 int nf, pllout2; 114 115 cfcr = CPM_CPCCR_CLKOEN | 116 (n2FR[PHM_DIV] << CPM_CPCCR_CDIV_BIT) | 117 (n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) | 118 (n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) | 119 (n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) | 120 (n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT); 121 122 pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2); 123 124 /* Init USB Host clock, pllout2 must be n*48MHz */ 125 REG_CPM_UHCCDR = pllout2 / 48000000 - 1; 126 127 nf = CFG_CPU_SPEED * 2 / CFG_EXTAL; 128 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ 129 (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ 130 (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ 131 (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ 132 CPM_CPPCR_PLLEN; /* enable PLL */ 133 134 /* init PLL */ 135 REG_CPM_CPCCR = cfcr; 136 REG_CPM_CPPCR = plcr1; 137 } 138 139 void sdram_init(void) 140 { 141 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; 142 143 unsigned int cas_latency_sdmr[2] = { 144 EMC_SDMR_CAS_2, 145 EMC_SDMR_CAS_3, 146 }; 147 148 unsigned int cas_latency_dmcr[2] = { 149 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ 150 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ 151 }; 152 153 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 154 155 cpu_clk = CFG_CPU_SPEED; 156 mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; 157 158 REG_EMC_BCR = 0; /* Disable bus release */ 159 REG_EMC_RTCSR = 0; /* Disable clock for counting */ 160 161 /* Fault DMCR value for mode register setting*/ 162 #define SDRAM_ROW0 11 163 #define SDRAM_COL0 8 164 #define SDRAM_BANK40 0 165 166 dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | 167 ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | 168 (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | 169 (SDRAM_BW16<<EMC_DMCR_BW_BIT) | 170 EMC_DMCR_EPIN | 171 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 172 173 /* Basic DMCR value */ 174 dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | 175 ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | 176 (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | 177 (SDRAM_BW16<<EMC_DMCR_BW_BIT) | 178 EMC_DMCR_EPIN | 179 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 180 181 /* SDRAM timimg */ 182 ns = 1000000000 / mem_clk; 183 tmp = SDRAM_TRAS/ns; 184 if (tmp < 4) tmp = 4; 185 if (tmp > 11) tmp = 11; 186 dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); 187 tmp = SDRAM_RCD/ns; 188 if (tmp > 3) tmp = 3; 189 dmcr |= (tmp << EMC_DMCR_RCD_BIT); 190 tmp = SDRAM_TPC/ns; 191 if (tmp > 7) tmp = 7; 192 dmcr |= (tmp << EMC_DMCR_TPC_BIT); 193 tmp = SDRAM_TRWL/ns; 194 if (tmp > 3) tmp = 3; 195 dmcr |= (tmp << EMC_DMCR_TRWL_BIT); 196 tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; 197 if (tmp > 14) tmp = 14; 198 dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); 199 200 /* SDRAM mode value */ 201 sdmode = EMC_SDMR_BT_SEQ | 202 EMC_SDMR_OM_NORMAL | 203 EMC_SDMR_BL_4 | 204 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; 205 206 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ 207 REG_EMC_DMCR = dmcr; 208 REG8(EMC_SDMR0|sdmode) = 0; 209 210 /* Wait for precharge, > 200us */ 211 tmp = (cpu_clk / 1000000) * 1000; 212 while (tmp--); 213 214 /* Stage 2. Enable auto-refresh */ 215 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; 216 217 tmp = SDRAM_TREF/ns; 218 tmp = tmp/64 + 1; 219 if (tmp > 0xff) tmp = 0xff; 220 REG_EMC_RTCOR = tmp; 221 REG_EMC_RTCNT = 0; 222 REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ 223 224 /* Wait for number of auto-refresh cycles */ 225 tmp = (cpu_clk / 1000000) * 1000; 226 while (tmp--); 227 228 /* Stage 3. Mode Register Set */ 229 REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 230 REG8(EMC_SDMR0|sdmode) = 0; 231 232 /* Set back to basic DMCR value */ 233 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 234 235 /* everything is ok now */ 236 }