1 /* 2 * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools. 3 * 4 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 5 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> 6 * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn> 7 * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 8 * 9 * This program is free software; you can redistribute it and/or modify it under 10 * the terms of the GNU General Public License as published by the Free Software 11 * Foundation; either version 3 of the License, or (at your option) any later 12 * version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 16 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "jz4740.h" 24 #include "nanonote.h" 25 #include "usb_boot_defines.h" 26 27 /* These arguments are initialised by usbboot and are defined in... 28 /etc/xburst-tools/usbboot.cfg. */ 29 30 struct fw_args *fw_args; 31 volatile u32 FW_CPU_ID; 32 volatile u8 FW_SDRAM_BW16; 33 volatile u8 FW_SDRAM_BANK4; 34 volatile u8 FW_SDRAM_ROW; 35 volatile u8 FW_SDRAM_COL; 36 volatile u8 FW_CONFIG_MOBILE_SDRAM; 37 volatile u8 FW_IS_SHARE; 38 39 void load_args(void) 40 { 41 /* Get the fw args from memory. See head1.S for the memory layout. */ 42 43 fw_args = (struct fw_args *)0x80002008; 44 FW_CPU_ID = fw_args->cpu_id ; 45 FW_SDRAM_BW16 = fw_args->bus_width; 46 FW_SDRAM_BANK4 = fw_args->bank_num; 47 FW_SDRAM_ROW = fw_args->row_addr; 48 FW_SDRAM_COL = fw_args->col_addr; 49 FW_CONFIG_MOBILE_SDRAM = fw_args->is_mobile; 50 FW_IS_SHARE = fw_args->is_busshare; 51 } 52 53 /* Initialisation functions. */ 54 55 void gpio_init(void) 56 { 57 /* 58 * Initialize NAND Flash Pins 59 */ 60 __gpio_as_nand(); 61 62 /* 63 * Initialize SDRAM pins 64 */ 65 __gpio_as_sdram_16bit_4720(); 66 } 67 68 void pll_init(void) 69 { 70 register unsigned int cfcr, plcr1; 71 int nf, pllout2; 72 73 /* See CPCCR (Clock Control Register). 74 * 0 == same frequency; 2 == f/3 75 */ 76 77 cfcr = CPM_CPCCR_CLKOEN | 78 CPM_CPCCR_PCS | 79 (0 << CPM_CPCCR_CDIV_BIT) | 80 (2 << CPM_CPCCR_HDIV_BIT) | 81 (2 << CPM_CPCCR_PDIV_BIT) | 82 (2 << CPM_CPCCR_MDIV_BIT) | 83 (2 << CPM_CPCCR_LDIV_BIT); 84 85 /* Determine the divider clock output based on the PCS bit. */ 86 87 pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); 88 89 /* Init USB Host clock. 90 * Divisor == UHCCDR + 1 91 * Desired frequency == 48MHz 92 */ 93 94 REG_CPM_UHCCDR = pllout2 / 48000000 - 1; 95 96 nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; 97 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ 98 (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ 99 (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ 100 CPM_CPPCR_PLLEN; /* enable PLL */ 101 102 /* Update PLL and wait. */ 103 104 REG_CPM_CPCCR = cfcr; 105 REG_CPM_CPPCR = plcr1; 106 while (!__cpm_pll_is_on()); 107 } 108 109 void sdram_init(void) 110 { 111 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; 112 unsigned int pllout = __cpm_get_pllout(); 113 114 unsigned int cas_latency_sdmr[2] = { 115 EMC_SDMR_CAS_2, 116 EMC_SDMR_CAS_3, 117 }; 118 119 unsigned int cas_latency_dmcr[2] = { 120 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ 121 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ 122 }; 123 124 /* Divisors for CPCCR values. */ 125 126 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 127 128 cpu_clk = pllout / div[__cpm_get_cdiv()]; 129 mem_clk = pllout / div[__cpm_get_mdiv()]; 130 131 REG_EMC_BCR = 0; /* Disable bus release */ 132 REG_EMC_RTCSR = 0; /* Disable clock for counting */ 133 134 /* Fault DMCR value for mode register setting*/ 135 dmcr0 = (0<<EMC_DMCR_RA_BIT) | 136 (0<<EMC_DMCR_CA_BIT) | 137 (0<<EMC_DMCR_BA_BIT) | 138 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | 139 EMC_DMCR_EPIN | 140 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 141 142 /* Basic DMCR value */ 143 dmcr = ((FW_SDRAM_ROW-SDRAM_ROW0)<<EMC_DMCR_RA_BIT) | 144 ((FW_SDRAM_COL-SDRAM_COL0)<<EMC_DMCR_CA_BIT) | 145 ((FW_SDRAM_BANK4-SDRAM_BANK40)<<EMC_DMCR_BA_BIT) | 146 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | 147 EMC_DMCR_EPIN | 148 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 149 150 /* SDRAM timimg */ 151 ns = 1000000000 / mem_clk; 152 tmp = SDRAM_TRAS/ns; 153 if (tmp < 4) tmp = 4; 154 if (tmp > 11) tmp = 11; 155 dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); 156 tmp = SDRAM_RCD/ns; 157 if (tmp > 3) tmp = 3; 158 dmcr |= (tmp << EMC_DMCR_RCD_BIT); 159 tmp = SDRAM_TPC/ns; 160 if (tmp > 7) tmp = 7; 161 dmcr |= (tmp << EMC_DMCR_TPC_BIT); 162 tmp = SDRAM_TRWL/ns; 163 if (tmp > 3) tmp = 3; 164 dmcr |= (tmp << EMC_DMCR_TRWL_BIT); 165 tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; 166 if (tmp > 14) tmp = 14; 167 dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); 168 169 /* SDRAM mode value */ 170 sdmode = EMC_SDMR_BT_SEQ | 171 EMC_SDMR_OM_NORMAL | 172 EMC_SDMR_BL_4 | 173 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; 174 175 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ 176 REG_EMC_DMCR = dmcr; 177 REG8(EMC_SDMR0|sdmode) = 0; 178 179 /* Wait for precharge, > 200us */ 180 tmp = (cpu_clk / 1000000) * 1000; 181 while (tmp--); 182 183 /* Stage 2. Enable auto-refresh */ 184 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; 185 186 tmp = SDRAM_TREF/ns; 187 tmp = tmp/64 + 1; 188 if (tmp > 0xff) tmp = 0xff; 189 REG_EMC_RTCOR = tmp; 190 REG_EMC_RTCNT = 0; 191 REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ 192 193 /* Wait for number of auto-refresh cycles */ 194 tmp = (cpu_clk / 1000000) * 1000; 195 while (tmp--); 196 197 /* Stage 3. Mode Register Set */ 198 REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 199 REG8(EMC_SDMR0|sdmode) = 0; 200 201 /* Set back to basic DMCR value */ 202 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 203 204 /* everything is ok now */ 205 }