1 /* 2 * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools. 3 * 4 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 5 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> 6 * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn> 7 * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 8 * 9 * This program is free software; you can redistribute it and/or modify it under 10 * the terms of the GNU General Public License as published by the Free Software 11 * Foundation; either version 3 of the License, or (at your option) any later 12 * version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 16 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "jz4740.h" 24 #include "configs.h" 25 #include "nanonote.h" 26 #include "usb_boot_defines.h" 27 28 /* These arguments are initialised by usbboot and are defined in... 29 /etc/xburst-tools/usbboot.cfg. */ 30 31 struct fw_args *fw_args; 32 volatile u32 CPU_ID; 33 volatile u32 UART_BASE; 34 volatile u32 CONFIG_BAUDRATE; 35 volatile u8 SDRAM_BW16; 36 volatile u8 SDRAM_BANK4; 37 volatile u8 SDRAM_ROW; 38 volatile u8 SDRAM_COL; 39 volatile u8 CONFIG_MOBILE_SDRAM; 40 volatile u32 CFG_CPU_SPEED; 41 volatile u32 CFG_EXTAL; 42 volatile u8 PHM_DIV; 43 volatile u8 IS_SHARE; 44 45 void load_args(void) 46 { 47 /* Get the fw args from memory. See head.S for the memory layout. */ 48 49 fw_args = (struct fw_args *)0x80002008; 50 CPU_ID = fw_args->cpu_id ; 51 CFG_EXTAL = (u32)fw_args->ext_clk * 1000000; 52 CFG_CPU_SPEED = (u32)fw_args->cpu_speed * CFG_EXTAL ; 53 if (CFG_EXTAL == 19000000) { 54 CFG_EXTAL = 19200000; 55 CFG_CPU_SPEED = 192000000; 56 } 57 PHM_DIV = fw_args->phm_div; 58 UART_BASE = UART0_BASE + fw_args->use_uart * 0x1000; 59 CONFIG_BAUDRATE = fw_args->boudrate; 60 SDRAM_BW16 = fw_args->bus_width; 61 SDRAM_BANK4 = fw_args->bank_num; 62 SDRAM_ROW = fw_args->row_addr; 63 SDRAM_COL = fw_args->col_addr; 64 CONFIG_MOBILE_SDRAM = fw_args->is_mobile; 65 IS_SHARE = fw_args->is_busshare; 66 } 67 68 /* Initialisation functions. */ 69 70 void gpio_init(void) 71 { 72 /* 73 * Initialize NAND Flash Pins 74 */ 75 __gpio_as_nand(); 76 77 /* 78 * Initialize SDRAM pins 79 */ 80 __gpio_as_sdram_32bit(); 81 } 82 83 void gpio_init2(void) 84 { 85 /* 86 * Initialize LCD pins 87 */ 88 __gpio_as_slcd_8bit(); 89 90 /* 91 * Initialize MSC pins 92 */ 93 __gpio_as_msc(); 94 95 /* 96 * Initialize Other pins 97 */ 98 unsigned int i; 99 for (i = 0; i < 7; i++){ 100 __gpio_as_input(GPIO_KEYIN_BASE + i); 101 __gpio_enable_pull(GPIO_KEYIN_BASE + i); 102 } 103 104 for (i = 0; i < 8; i++) { 105 __gpio_as_output(GPIO_KEYOUT_BASE + i); 106 __gpio_clear_pin(GPIO_KEYOUT_BASE + i); 107 } 108 109 /* enable the TP4, TP5 as UART0 */ 110 __gpio_jtag_to_uart0(); 111 112 __gpio_as_input(GPIO_KEYIN_8); 113 __gpio_enable_pull(GPIO_KEYIN_8); 114 115 __gpio_as_output(GPIO_AUDIO_POP); 116 __gpio_set_pin(GPIO_AUDIO_POP); 117 118 __gpio_as_output(GPIO_LCD_CS); 119 __gpio_clear_pin(GPIO_LCD_CS); 120 121 __gpio_as_output(GPIO_AMP_EN); 122 __gpio_clear_pin(GPIO_AMP_EN); 123 124 __gpio_as_output(GPIO_SDPW_EN); 125 __gpio_disable_pull(GPIO_SDPW_EN); 126 __gpio_clear_pin(GPIO_SDPW_EN); 127 128 __gpio_as_input(GPIO_SD_DETECT); 129 __gpio_disable_pull(GPIO_SD_DETECT); 130 131 __gpio_as_input(GPIO_USB_DETECT); 132 __gpio_enable_pull(GPIO_USB_DETECT); 133 } 134 135 void cpm_init(void) 136 { 137 __cpm_stop_ipu(); 138 __cpm_stop_cim(); 139 __cpm_stop_i2c(); 140 __cpm_stop_ssi(); 141 __cpm_stop_uart1(); 142 __cpm_stop_sadc(); 143 __cpm_stop_uhc(); 144 __cpm_stop_udc(); 145 __cpm_stop_aic1(); 146 /* __cpm_stop_aic2();*/ 147 } 148 149 void pll_init(void) 150 { 151 register unsigned int cfcr, plcr1; 152 int n2FR[33] = { 153 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 154 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 155 9 156 }; 157 int nf, pllout2; 158 159 cfcr = CPM_CPCCR_CLKOEN | 160 (n2FR[PHM_DIV] << CPM_CPCCR_CDIV_BIT) | 161 (n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) | 162 (n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) | 163 (n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) | 164 (n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT); 165 166 pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2); 167 168 /* Init USB Host clock, pllout2 must be n*48MHz */ 169 REG_CPM_UHCCDR = pllout2 / 48000000 - 1; 170 171 nf = CFG_CPU_SPEED * 2 / CFG_EXTAL; 172 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ 173 (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ 174 (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ 175 (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ 176 CPM_CPPCR_PLLEN; /* enable PLL */ 177 178 /* init PLL */ 179 REG_CPM_CPCCR = cfcr; 180 REG_CPM_CPPCR = plcr1; 181 } 182 183 void sdram_init(void) 184 { 185 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; 186 187 unsigned int cas_latency_sdmr[2] = { 188 EMC_SDMR_CAS_2, 189 EMC_SDMR_CAS_3, 190 }; 191 192 unsigned int cas_latency_dmcr[2] = { 193 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ 194 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ 195 }; 196 197 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 198 199 cpu_clk = CFG_CPU_SPEED; 200 mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; 201 202 REG_EMC_BCR = 0; /* Disable bus release */ 203 REG_EMC_RTCSR = 0; /* Disable clock for counting */ 204 205 /* Fault DMCR value for mode register setting*/ 206 #define SDRAM_ROW0 11 207 #define SDRAM_COL0 8 208 #define SDRAM_BANK40 0 209 210 dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | 211 ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | 212 (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | 213 (SDRAM_BW16<<EMC_DMCR_BW_BIT) | 214 EMC_DMCR_EPIN | 215 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 216 217 /* Basic DMCR value */ 218 dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | 219 ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | 220 (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | 221 (SDRAM_BW16<<EMC_DMCR_BW_BIT) | 222 EMC_DMCR_EPIN | 223 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 224 225 /* SDRAM timimg */ 226 ns = 1000000000 / mem_clk; 227 tmp = SDRAM_TRAS/ns; 228 if (tmp < 4) tmp = 4; 229 if (tmp > 11) tmp = 11; 230 dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); 231 tmp = SDRAM_RCD/ns; 232 if (tmp > 3) tmp = 3; 233 dmcr |= (tmp << EMC_DMCR_RCD_BIT); 234 tmp = SDRAM_TPC/ns; 235 if (tmp > 7) tmp = 7; 236 dmcr |= (tmp << EMC_DMCR_TPC_BIT); 237 tmp = SDRAM_TRWL/ns; 238 if (tmp > 3) tmp = 3; 239 dmcr |= (tmp << EMC_DMCR_TRWL_BIT); 240 tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; 241 if (tmp > 14) tmp = 14; 242 dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); 243 244 /* SDRAM mode value */ 245 sdmode = EMC_SDMR_BT_SEQ | 246 EMC_SDMR_OM_NORMAL | 247 EMC_SDMR_BL_4 | 248 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; 249 250 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ 251 REG_EMC_DMCR = dmcr; 252 REG8(EMC_SDMR0|sdmode) = 0; 253 254 /* Wait for precharge, > 200us */ 255 tmp = (cpu_clk / 1000000) * 1000; 256 while (tmp--); 257 258 /* Stage 2. Enable auto-refresh */ 259 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; 260 261 tmp = SDRAM_TREF/ns; 262 tmp = tmp/64 + 1; 263 if (tmp > 0xff) tmp = 0xff; 264 REG_EMC_RTCOR = tmp; 265 REG_EMC_RTCNT = 0; 266 REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ 267 268 /* Wait for number of auto-refresh cycles */ 269 tmp = (cpu_clk / 1000000) * 1000; 270 while (tmp--); 271 272 /* Stage 3. Mode Register Set */ 273 REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 274 REG8(EMC_SDMR0|sdmode) = 0; 275 276 /* Set back to basic DMCR value */ 277 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 278 279 /* everything is ok now */ 280 } 281 282 void rtc_init(void) 283 { 284 while ( !__rtc_write_ready()) ; 285 __rtc_enable_alarm(); /* enable alarm */ 286 287 while ( !__rtc_write_ready()) 288 ; 289 REG_RTC_RGR = 0x00007fff; /* type value */ 290 291 while ( !__rtc_write_ready()) 292 ; 293 REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */ 294 295 while ( !__rtc_write_ready()) 296 ; 297 REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */ 298 } 299 300 /* 301 * Timer routines 302 */ 303 304 #define TIMER_CHAN 0 305 #define TIMER_FDATA 0xffff /* Timer full data value */ 306 #define TIMER_HZ CONFIG_SYS_HZ 307 308 #define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */ 309 310 static unsigned long timestamp; 311 static unsigned long lastdec; 312 313 void reset_timer_masked(void); 314 unsigned long get_timer_masked(void); 315 void udelay_masked(unsigned long usec); 316 317 /* 318 * timer without interrupts 319 */ 320 321 int timer_init(void) 322 { 323 REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN; 324 REG_TCU_TCNT(TIMER_CHAN) = 0; 325 REG_TCU_TDHR(TIMER_CHAN) = 0; 326 REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA; 327 328 REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */ 329 REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */ 330 REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */ 331 332 lastdec = 0; 333 timestamp = 0; 334 335 return 0; 336 } 337 338 void reset_timer(void) 339 { 340 reset_timer_masked (); 341 } 342 343 unsigned long get_timer(unsigned long base) 344 { 345 return get_timer_masked () - base; 346 } 347 348 void set_timer(unsigned long t) 349 { 350 timestamp = t; 351 } 352 353 void udelay (unsigned long usec) 354 { 355 unsigned long tmo,tmp; 356 357 /* normalize */ 358 if (usec >= 1000) { 359 tmo = usec / 1000; 360 tmo *= TIMER_HZ; 361 tmo /= 1000; 362 } 363 else { 364 if (usec >= 1) { 365 tmo = usec * TIMER_HZ; 366 tmo /= (1000*1000); 367 } 368 else 369 tmo = 1; 370 } 371 372 /* check for rollover during this delay */ 373 tmp = get_timer (0); 374 if ((tmp + tmo) < tmp ) 375 reset_timer_masked(); /* timer would roll over */ 376 else 377 tmo += tmp; 378 379 while (get_timer_masked () < tmo); 380 } 381 382 void reset_timer_masked (void) 383 { 384 /* reset time */ 385 lastdec = READ_TIMER; 386 timestamp = 0; 387 } 388 389 unsigned long get_timer_masked (void) 390 { 391 unsigned long now = READ_TIMER; 392 393 if (lastdec <= now) { 394 /* normal mode */ 395 timestamp += (now - lastdec); 396 } else { 397 /* we have an overflow ... */ 398 timestamp += TIMER_FDATA + now - lastdec; 399 } 400 lastdec = now; 401 402 return timestamp; 403 } 404 405 void udelay_masked (unsigned long usec) 406 { 407 unsigned long tmo; 408 unsigned long endtime; 409 signed long diff; 410 411 /* normalize */ 412 if (usec >= 1000) { 413 tmo = usec / 1000; 414 tmo *= TIMER_HZ; 415 tmo /= 1000; 416 } else { 417 if (usec > 1) { 418 tmo = usec * TIMER_HZ; 419 tmo /= (1000*1000); 420 } else { 421 tmo = 1; 422 } 423 } 424 425 endtime = get_timer_masked () + tmo; 426 427 do { 428 unsigned long now = get_timer_masked (); 429 diff = endtime - now; 430 } while (diff >= 0); 431 } 432 433 /* 434 * This function is derived from PowerPC code (read timebase as long long). 435 * On MIPS it just returns the timer value. 436 */ 437 unsigned long long get_ticks(void) 438 { 439 return get_timer(0); 440 } 441 442 /* 443 * This function is derived from PowerPC code (timebase clock frequency). 444 * On MIPS it returns the number of timer ticks per second. 445 */ 446 unsigned long get_tbclk (void) 447 { 448 return TIMER_HZ; 449 } 450 451 /* CPU-specific routines from U-Boot. 452 See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c 453 See: u-boot/arch/mips/include/asm/cacheops.h 454 */ 455 456 #define Index_Store_Tag_I 0x08 457 #define Index_Writeback_Inv_D 0x15 458 459 void flush_icache_all(void) 460 { 461 u32 addr, t = 0; 462 463 asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ 464 asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ 465 466 for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; 467 addr += CONFIG_SYS_CACHELINE_SIZE) { 468 asm volatile ( 469 ".set mips3\n\t" 470 " cache %0, 0(%1)\n\t" 471 ".set mips2\n\t" 472 : 473 : "I" (Index_Store_Tag_I), "r"(addr)); 474 } 475 476 /* invalicate btb */ 477 asm volatile ( 478 ".set mips32\n\t" 479 "mfc0 %0, $16, 7\n\t" 480 "nop\n\t" 481 "ori %0,2\n\t" 482 "mtc0 %0, $16, 7\n\t" 483 ".set mips2\n\t" 484 : 485 : "r" (t)); 486 } 487 488 void flush_dcache_all(void) 489 { 490 u32 addr; 491 492 for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; 493 addr += CONFIG_SYS_CACHELINE_SIZE) { 494 asm volatile ( 495 ".set mips3\n\t" 496 " cache %0, 0(%1)\n\t" 497 ".set mips2\n\t" 498 : 499 : "I" (Index_Writeback_Inv_D), "r"(addr)); 500 } 501 502 asm volatile ("sync"); 503 } 504 505 void flush_cache_all(void) 506 { 507 flush_dcache_all(); 508 flush_icache_all(); 509 }