1 /* 2 * JzRISC LCD controller 3 * 4 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> 5 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 20 * Boston, MA 02110-1301, USA 21 */ 22 23 #include "sdram.h" 24 #include "jzlcd.h" 25 #include "board.h" 26 27 #define align2(n) (n)=((((n)+1)>>1)<<1) 28 #define align4(n) (n)=((((n)+3)>>2)<<2) 29 #define align8(n) (n)=((((n)+7)>>3)<<3) 30 31 extern struct jzfb_info jzfb; 32 extern vidinfo_t panel_info; 33 34 unsigned long lcd_get_size(void) 35 { 36 int line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; 37 return line_length * panel_info.vl_row; 38 } 39 40 static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid); 41 static void jz_lcd_desc_init(vidinfo_t *vid); 42 static int jz_lcd_hw_init(vidinfo_t *vid); 43 44 void lcd_ctrl_init (void *lcdbase) 45 { 46 jz_lcd_init_mem(lcdbase, &panel_info); 47 jz_lcd_desc_init(&panel_info); 48 jz_lcd_hw_init(&panel_info); 49 } 50 51 /* 52 * Before enabled lcd controller, lcd registers should be configured correctly. 53 */ 54 void lcd_enable (void) 55 { 56 REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ 57 REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ 58 } 59 60 void lcd_disable (void) 61 { 62 REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ 63 /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */ 64 } 65 66 static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid) 67 { 68 unsigned long palette_mem_size; 69 struct jz_fb_info *fbi = &vid->jz_fb; 70 int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; 71 72 fbi->screen = (unsigned long)lcdbase; 73 fbi->palette_size = 256; 74 palette_mem_size = fbi->palette_size * sizeof(u16); 75 76 /* debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (unsigned long) palette_mem_size); */ 77 /* locate palette and descs at end of page following fb */ 78 fbi->palette = (unsigned long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; 79 80 return 0; 81 } 82 83 static void jz_lcd_desc_init(vidinfo_t *vid) 84 { 85 struct jz_fb_info * fbi; 86 fbi = &vid->jz_fb; 87 fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); 88 fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); 89 fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); 90 91 #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8) 92 93 /* populate descriptors */ 94 fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow); 95 fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL)); 96 fbi->dmadesc_fblow->fidr = 0; 97 fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ; 98 99 fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */ 100 101 fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); 102 fbi->dmadesc_fbhigh->fidr = 0; 103 fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */ 104 105 fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette); 106 fbi->dmadesc_palette->fidr = 0; 107 fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); 108 109 if(NBITS(vid->vl_bpix) < 12) 110 { 111 /* assume any mode with <12 bpp is palette driven */ 112 fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh); 113 fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette); 114 /* flips back and forth between pal and fbhigh */ 115 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette); 116 } else { 117 /* palette shouldn't be loaded in true-color mode */ 118 fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh); 119 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */ 120 } 121 122 flush_cache_all(); 123 } 124 125 static int jz_lcd_hw_init(vidinfo_t *vid) 126 { 127 struct jz_fb_info *fbi = &vid->jz_fb; 128 unsigned int val = 0; 129 unsigned int pclk; 130 unsigned int stnH; 131 #ifndef CONFIG_CPU_JZ4730 132 int pll_div; 133 #endif 134 135 /* Setting Control register */ 136 switch (jzfb.bpp) { 137 case 1: 138 val |= LCD_CTRL_BPP_1; 139 break; 140 case 2: 141 val |= LCD_CTRL_BPP_2; 142 break; 143 case 4: 144 val |= LCD_CTRL_BPP_4; 145 break; 146 case 8: 147 val |= LCD_CTRL_BPP_8; 148 break; 149 case 15: 150 val |= LCD_CTRL_RGB555; 151 case 16: 152 val |= LCD_CTRL_BPP_16; 153 break; 154 #ifndef CONFIG_CPU_JZ4730 155 case 17 ... 32: 156 val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ 157 break; 158 #endif 159 default: 160 /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */ 161 val |= LCD_CTRL_BPP_16; 162 break; 163 } 164 165 switch (jzfb.cfg & MODE_MASK) { 166 case MODE_STN_MONO_DUAL: 167 case MODE_STN_COLOR_DUAL: 168 case MODE_STN_MONO_SINGLE: 169 case MODE_STN_COLOR_SINGLE: 170 switch (jzfb.bpp) { 171 case 1: 172 /* val |= LCD_CTRL_PEDN; */ 173 case 2: 174 val |= LCD_CTRL_FRC_2; 175 break; 176 case 4: 177 val |= LCD_CTRL_FRC_4; 178 break; 179 case 8: 180 default: 181 val |= LCD_CTRL_FRC_16; 182 break; 183 } 184 break; 185 } 186 187 val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ 188 val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ 189 190 switch (jzfb.cfg & MODE_MASK) { 191 case MODE_STN_MONO_DUAL: 192 case MODE_STN_COLOR_DUAL: 193 case MODE_STN_MONO_SINGLE: 194 case MODE_STN_COLOR_SINGLE: 195 switch (jzfb.cfg & STN_DAT_PINMASK) { 196 case STN_DAT_PIN1: 197 /* Do not adjust the hori-param value. */ 198 break; 199 case STN_DAT_PIN2: 200 align2(jzfb.hsw); 201 align2(jzfb.elw); 202 align2(jzfb.blw); 203 break; 204 case STN_DAT_PIN4: 205 align4(jzfb.hsw); 206 align4(jzfb.elw); 207 align4(jzfb.blw); 208 break; 209 case STN_DAT_PIN8: 210 align8(jzfb.hsw); 211 align8(jzfb.elw); 212 align8(jzfb.blw); 213 break; 214 } 215 break; 216 } 217 218 REG_LCD_CTRL = val; 219 220 switch (jzfb.cfg & MODE_MASK) { 221 case MODE_STN_MONO_DUAL: 222 case MODE_STN_COLOR_DUAL: 223 case MODE_STN_MONO_SINGLE: 224 case MODE_STN_COLOR_SINGLE: 225 if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || 226 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 227 stnH = jzfb.h >> 1; 228 else 229 stnH = jzfb.h; 230 231 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 232 REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); 233 234 /* Screen setting */ 235 REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); 236 REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); 237 REG_LCD_DAV = (0 << 16) | (stnH); 238 239 /* AC BIAs signal */ 240 REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); 241 242 break; 243 244 case MODE_TFT_GEN: 245 case MODE_TFT_SHARP: 246 case MODE_TFT_CASIO: 247 case MODE_TFT_SAMSUNG: 248 case MODE_8BIT_SERIAL_TFT: 249 case MODE_TFT_18BIT: 250 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; 251 REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; 252 REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); 253 REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); 254 REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ 255 | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); 256 break; 257 } 258 259 switch (jzfb.cfg & MODE_MASK) { 260 case MODE_TFT_SAMSUNG: 261 { 262 unsigned int total, tp_s, tp_e, ckv_s, ckv_e; 263 unsigned int rev_s, rev_e, inv_s, inv_e; 264 265 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 266 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 267 268 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 269 tp_s = jzfb.blw + jzfb.w + 1; 270 tp_e = tp_s + 1; 271 /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ 272 ckv_s = tp_s - pclk/(1000000000/4100); 273 ckv_e = tp_s + total; 274 rev_s = tp_s - 11; /* -11.5 clk */ 275 rev_e = rev_s + total; 276 inv_s = tp_s; 277 inv_e = inv_s + total; 278 REG_LCD_CLS = (tp_s << 16) | tp_e; 279 REG_LCD_PS = (ckv_s << 16) | ckv_e; 280 REG_LCD_SPL = (rev_s << 16) | rev_e; 281 REG_LCD_REV = (inv_s << 16) | inv_e; 282 jzfb.cfg |= STFT_REVHI | STFT_SPLHI; 283 break; 284 } 285 case MODE_TFT_SHARP: 286 { 287 unsigned int total, cls_s, cls_e, ps_s, ps_e; 288 unsigned int spl_s, spl_e, rev_s, rev_e; 289 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; 290 spl_s = 1; 291 spl_e = spl_s + 1; 292 cls_s = 0; 293 cls_e = total - 60; /* > 4us (pclk = 80ns) */ 294 ps_s = cls_s; 295 ps_e = cls_e; 296 rev_s = total - 40; /* > 3us (pclk = 80ns) */ 297 rev_e = rev_s + total; 298 jzfb.cfg |= STFT_PSHI; 299 REG_LCD_SPL = (spl_s << 16) | spl_e; 300 REG_LCD_CLS = (cls_s << 16) | cls_e; 301 REG_LCD_PS = (ps_s << 16) | ps_e; 302 REG_LCD_REV = (rev_s << 16) | rev_e; 303 break; 304 } 305 case MODE_TFT_CASIO: 306 break; 307 } 308 309 /* Configure the LCD panel */ 310 REG_LCD_CFG = jzfb.cfg; 311 312 /* Timing setting */ 313 __cpm_stop_lcd(); 314 315 val = jzfb.fclk; /* frame clk */ 316 if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { 317 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * 318 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 319 } else { 320 /* serial mode: Hsync period = 3*Width_Pixel */ 321 pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * 322 (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ 323 } 324 325 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 326 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) 327 pclk = (pclk * 3); 328 329 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || 330 ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 331 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || 332 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 333 pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); 334 335 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 336 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 337 pclk >>= 1; 338 339 #ifdef CONFIG_CPU_JZ4730 340 val = __cpm_get_pllout() / pclk; 341 REG_CPM_CFCR2 = val - 1; 342 val = pclk * 4 ; 343 if ( val > 150000000 ) { 344 val = 150000000; 345 } 346 val = __cpm_get_pllout() / val; 347 val--; 348 if ( val > 0xF ) 349 val = 0xF; 350 __cpm_set_lcdclk_div(val); 351 REG_CPM_CFCR |= CPM_CFCR_UPE; 352 #else 353 pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ 354 pll_div = pll_div ? 1 : 2 ; 355 val = ( __cpm_get_pllout()/pll_div ) / pclk; 356 val--; 357 if ( val > 0x1ff ) { 358 val = 0x1ff; 359 } 360 __cpm_set_pixdiv(val); 361 362 val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ 363 if ( val > 150000000 ) { 364 val = 150000000; 365 } 366 val = ( __cpm_get_pllout()/pll_div ) / val; 367 val--; 368 if ( val > 0x1f ) { 369 val = 0x1f; 370 } 371 __cpm_set_ldiv( val ); 372 REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ 373 #endif 374 __cpm_start_lcd(); 375 udelay(1000); 376 377 REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/ 378 379 if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || 380 ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) 381 REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/ 382 383 return 0; 384 } 385 386 void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue) 387 { 388 } 389 390 void lcd_initcolregs (void) 391 { 392 }