# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1456445631 -3600
# Node ID 00392b6b6878bf4de5b64581ac0ef2ee47f66543
# Parent  a2d51d81fa864870d7866340b372504624a3eb09
Added a potentially useful TLB page miss mapping function.

diff -r a2d51d81fa86 -r 00392b6b6878 stage2/cpu.c
--- a/stage2/cpu.c	Fri Feb 26 01:09:43 2016 +0100
+++ b/stage2/cpu.c	Fri Feb 26 01:13:51 2016 +0100
@@ -239,6 +239,28 @@
 		);
 }
 
+void map_page_miss(u32 physical, u32 pagesize, u8 flags)
+{
+	u32 lower = ((physical & 0xfffff000) >> 6) | flags;
+	u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags;
+	u32 pagemask = ((pagesize - 1) & 0xfffff000) << 1;
+
+	asm volatile(
+		"mtc0 %2, $5\n"		/* CP0_PAGEMASK */
+
+		/* Set physical address. */
+
+		"mtc0 %0, $2\n"		/* CP0_ENTRYLO0 */
+		"mtc0 %1, $3\n"		/* CP0_ENTRYLO1 */
+		"nop\n"
+
+		"tlbwr\n"
+		"nop"
+		:
+		: "r" (lower), "r" (upper), "r" (pagemask)
+		);
+}
+
 void unmap_page(u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid)
 {
 	u32 start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/
diff -r a2d51d81fa86 -r 00392b6b6878 stage2/cpu.h
--- a/stage2/cpu.h	Fri Feb 26 01:09:43 2016 +0100
+++ b/stage2/cpu.h	Fri Feb 26 01:13:51 2016 +0100
@@ -12,6 +12,7 @@
 void init_interrupts(void);
 void init_tlb(void);
 void map_page(u32, u32, u32, u8, u8);
+void map_page_miss(u32, u32, u8);
 void map_page_index(u32, u32, u32, u8, u8, u32);
 void unmap_page(u32, u32, u32, u8, u8);
 
diff -r a2d51d81fa86 -r 00392b6b6878 stage2/irq.c
--- a/stage2/irq.c	Fri Feb 26 01:09:43 2016 +0100
+++ b/stage2/irq.c	Fri Feb 26 01:13:51 2016 +0100
@@ -138,7 +138,7 @@
 	Pages employ C=3, dirty, valid, with the task number as the ASID.
 	*/
         
-	map_page(virtual, physical, pagesize, 0x1e, asid);
+	map_page_miss(physical, pagesize, 0x1e);
 }       
 
 void start_task(unsigned short task)