# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1456769350 -3600
# Node ID 1ee72222a36d49836bd53e7dee9fc9c8db8c4249
# Parent  c39fcc82cc152e153cd983605fa4353e2fe0053a
Fixed page table indexing in the TLB miss handler.

diff -r c39fcc82cc15 -r 1ee72222a36d stage2/cpu.h
--- a/stage2/cpu.h	Sun Feb 28 01:18:09 2016 +0100
+++ b/stage2/cpu.h	Mon Feb 29 19:09:10 2016 +0100
@@ -19,6 +19,5 @@
 
 #define page_table_start 0x80040000
 #define page_table_task_size 0x00008000
-#define page_table_task_size_log2 15
 
 #endif /* __CPU_H__ */
diff -r c39fcc82cc15 -r 1ee72222a36d stage2/entry.S
--- a/stage2/entry.S	Sun Feb 28 01:18:09 2016 +0100
+++ b/stage2/entry.S	Mon Feb 29 19:09:10 2016 +0100
@@ -30,7 +30,7 @@
 /* NOTE: Duplicated from cpu.h. */
 
 #define page_table_start 0x80040000
-#define page_table_task_size_log2 15
+#define page_table_task_size 0x00008000
 
 _tlb_entry:
 	/* Get the bad address. */
@@ -54,17 +54,19 @@
 	/* Otherwise, load the page table entries. */
 
 	andi $k1, $k0, 0xff			/* ASID */
-	sll $k1, $k1, page_table_task_size_log2	/* [ASID] */
-	li $k0, page_table_start		/* page_table */
-	add $k0, $k0, $k1			/* page_table[ASID] */
+	li $k0, page_table_task_size
+	mul $k0, $k0, $k1			/* [ASID] (ASID * page_table_task_size) */
+	li $k1, page_table_start		/* page_table */
+	addu $k1, $k0, $k1			/* page_table[ASID] */
 
-	mfc0 $k1, $4				/* CP0_CONTEXT */
+	mfc0 $k0, $4				/* CP0_CONTEXT */
 	nop
-	srl $k1, $k1, 1				/* use 8 byte - not 16 byte - entries */
-	add $k0, $k0, $k1			/* page_table[ASID][entry] */
+	srl $k0, $k0, 1				/* use 8 byte - not 16 byte - entries */
+	addu $k0, $k0, $k1			/* page_table[ASID][entry] */
 
 	lw $k1, 0($k0)				/* page_table[ASID][entry][0] */
 	mtc0 $k1, $2				/* CP0_ENTRYLO0 */
+
 	lw $k1, 4($k0)				/* page_table[ASID][entry][1] */
 	mtc0 $k1, $3				/* CP0_ENTRYLO1 */
 						/* page size is 4KB */