# HG changeset patch # User Paul Boddie # Date 1434309428 -7200 # Node ID 3409e830613438598dbf5a5c4631ac20fbd139bd # Parent 9d3a0971108d7b5602566cbdd249d9a092c0055b Made a separate file containing CPU-specific operations. diff -r 9d3a0971108d -r 3409e8306134 stage2/Makefile --- a/stage2/Makefile Sun Jun 14 21:14:30 2015 +0200 +++ b/stage2/Makefile Sun Jun 14 21:17:08 2015 +0200 @@ -62,8 +62,8 @@ # Ordering of objects is important and cannot be left to replacement rules. -SRC = head2.S stage2.c lcd.c jzlcd.c board.c $(BOARD_SRC) -OBJ = head2.o stage2.o lcd.o jzlcd.o board.o $(BOARD_OBJ) +SRC = head2.S stage2.c cpu.c lcd.c jzlcd.c board.c $(BOARD_SRC) +OBJ = head2.o stage2.o cpu.o lcd.o jzlcd.o board.o $(BOARD_OBJ) .PHONY: all clean distclean diff -r 9d3a0971108d -r 3409e8306134 stage2/board.c --- a/stage2/board.c Sun Jun 14 21:14:30 2015 +0200 +++ b/stage2/board.c Sun Jun 14 21:17:08 2015 +0200 @@ -1,7 +1,6 @@ /* * Common routines supporting board initialisation. * - * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, * Copyright (C) 2005-2006 Ingenic Semiconductor, * Copyright (C) Xiangfu Liu * Copyright (C) 2015 Paul Boddie @@ -157,63 +156,3 @@ { return TIMER_HZ; } - -/* CPU-specific routines from U-Boot. - See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c - See: u-boot/arch/mips/include/asm/cacheops.h -*/ - -#define Index_Store_Tag_I 0x08 -#define Index_Writeback_Inv_D 0x15 - -void flush_icache_all(void) -{ - u32 addr, t = 0; - - asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ - asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ - - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; - addr += CONFIG_SYS_CACHELINE_SIZE) { - asm volatile ( - ".set mips3\n\t" - " cache %0, 0(%1)\n\t" - ".set mips2\n\t" - : - : "I" (Index_Store_Tag_I), "r"(addr)); - } - - /* invalicate btb */ - asm volatile ( - ".set mips32\n\t" - "mfc0 %0, $16, 7\n\t" - "nop\n\t" - "ori %0,2\n\t" - "mtc0 %0, $16, 7\n\t" - ".set mips2\n\t" - : - : "r" (t)); -} - -void flush_dcache_all(void) -{ - u32 addr; - - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; - addr += CONFIG_SYS_CACHELINE_SIZE) { - asm volatile ( - ".set mips3\n\t" - " cache %0, 0(%1)\n\t" - ".set mips2\n\t" - : - : "I" (Index_Writeback_Inv_D), "r"(addr)); - } - - asm volatile ("sync"); -} - -void flush_cache_all(void) -{ - flush_dcache_all(); - flush_icache_all(); -} diff -r 9d3a0971108d -r 3409e8306134 stage2/board.h --- a/stage2/board.h Sun Jun 14 21:14:30 2015 +0200 +++ b/stage2/board.h Sun Jun 14 21:17:08 2015 +0200 @@ -4,7 +4,6 @@ /* Utility functions. */ void udelay(unsigned long usec); -void flush_cache_all(void); unsigned long get_memory_size(void); #ifdef CONFIG_CPU_JZ4730 diff -r 9d3a0971108d -r 3409e8306134 stage2/cpu.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/cpu.c Sun Jun 14 21:17:08 2015 +0200 @@ -0,0 +1,80 @@ +/* + * CPU-specific routines from U-Boot. + * See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c + * See: u-boot/arch/mips/include/asm/cacheops.h + * + * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA + */ + +#include "xburst_types.h" +#include "sdram.h" + +#define Index_Store_Tag_I 0x08 +#define Index_Writeback_Inv_D 0x15 + +void flush_icache_all(void) +{ + u32 addr, t = 0; + + asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ + asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ + + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; + addr += CONFIG_SYS_CACHELINE_SIZE) { + asm volatile ( + ".set mips3\n\t" + " cache %0, 0(%1)\n\t" + ".set mips2\n\t" + : + : "I" (Index_Store_Tag_I), "r"(addr)); + } + + /* invalicate btb */ + asm volatile ( + ".set mips32\n\t" + "mfc0 %0, $16, 7\n\t" + "nop\n\t" + "ori %0,2\n\t" + "mtc0 %0, $16, 7\n\t" + ".set mips2\n\t" + : + : "r" (t)); +} + +void flush_dcache_all(void) +{ + u32 addr; + + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; + addr += CONFIG_SYS_CACHELINE_SIZE) { + asm volatile ( + ".set mips3\n\t" + " cache %0, 0(%1)\n\t" + ".set mips2\n\t" + : + : "I" (Index_Writeback_Inv_D), "r"(addr)); + } + + asm volatile ("sync"); +} + +void flush_cache_all(void) +{ + flush_dcache_all(); + flush_icache_all(); +} diff -r 9d3a0971108d -r 3409e8306134 stage2/cpu.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/cpu.h Sun Jun 14 21:17:08 2015 +0200 @@ -0,0 +1,6 @@ +#ifndef __CPU_H__ +#define __CPU_H__ + +void flush_cache_all(void); + +#endif /* __CPU_H__ */ diff -r 9d3a0971108d -r 3409e8306134 stage2/jzlcd.c --- a/stage2/jzlcd.c Sun Jun 14 21:14:30 2015 +0200 +++ b/stage2/jzlcd.c Sun Jun 14 21:17:08 2015 +0200 @@ -22,6 +22,7 @@ #include "sdram.h" #include "jzlcd.h" +#include "cpu.h" #include "board.h" #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)