# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1435093500 -7200
# Node ID 5151ff3c7a768b74df545dfaaa9f552bd700eb8b
# Parent  838dee70e9cfad0e0e69921aadea204ec74258bd
Moved definitions and corrected them, adding also an interrupt enable function.

diff -r 838dee70e9cf -r 5151ff3c7a76 include/sdram.h
--- a/include/sdram.h	Tue Jun 23 23:04:17 2015 +0200
+++ b/include/sdram.h	Tue Jun 23 23:05:00 2015 +0200
@@ -1,8 +1,11 @@
 /*
  * Common SDRAM configuration.
  *
+ * Copyright (C) 1996, 1997 by Ralf Baechle
+ *
  * Copyright (C) 2009 Qi Hardware Inc.
  * Authors: Xiangfu Liu <xiangfu@openmobilefree.net>
+ *
  * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
  *
  * This program is free software: you can redistribute it and/or modify
@@ -67,6 +70,15 @@
 #define CONFIG_SYS_ICACHE_SIZE		16384
 #define CONFIG_SYS_CACHELINE_SIZE	32
 
+#define Index_Invalidate_I		0x00
+#define Index_Writeback_Inv_D		0x01
+#define Index_Store_Tag_I		0x08
+#define Index_Store_Tag_D		0x09
+#define Hit_Writeback_Inv_D		0x15
+
+#define CONFIG_CM_UNCACHED		2
+#define CONFIG_CM_CACHABLE_NONCOHERENT	3
+
 /*
  * Memory configuration
  */
diff -r 838dee70e9cf -r 5151ff3c7a76 stage2/cpu.c
--- a/stage2/cpu.c	Tue Jun 23 23:04:17 2015 +0200
+++ b/stage2/cpu.c	Tue Jun 23 23:05:00 2015 +0200
@@ -24,9 +24,6 @@
 #include "xburst_types.h"
 #include "sdram.h"
 
-#define Index_Store_Tag_I	0x08
-#define Index_Writeback_Inv_D	0x15
-
 void flush_icache_all(void)
 {
 	u32 addr, t = 0;
@@ -78,3 +75,14 @@
 	flush_dcache_all();
 	flush_icache_all();
 }
+
+void enable_interrupts(void)
+{
+	asm volatile(
+		"mfc0 $t3, $12\n" /* CP0_STATUS */
+		"nop\n"
+		"li $t4, 0x00000001\n" /* IE = enable interrupts */
+		"or $t3, $t3, $t4\n"
+		"mtc0 $t3, $12\n"
+		"nop\n");
+}
diff -r 838dee70e9cf -r 5151ff3c7a76 stage2/cpu.h
--- a/stage2/cpu.h	Tue Jun 23 23:04:17 2015 +0200
+++ b/stage2/cpu.h	Tue Jun 23 23:05:00 2015 +0200
@@ -2,5 +2,6 @@
 #define __CPU_H__
 
 void flush_cache_all(void);
+void enable_interrupts(void);
 
 #endif /* __CPU_H__ */